Changes

Summary

  1. [mlir][tosa] Disable tosa shape verification between operands/results (details)
  2. [WebAssembly] Improve pseudocode in LowerEmscriptenEHSjLj (details)
  3. [libc] add scudo wrappers to llvm libc (details)
  4. [GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner. (details)
  5. [AArch64][GlobalISel] Enable some select combines after legalization. (details)
  6. [LLVM IR] Allow volatile stores to trap. (details)
  7. [AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT. (details)
  8. [LLDB][GUI] Resolve paths in file/directory fields (details)
  9. [FPEnv][InstSimplify] Enable more folds for constrained fadd (details)
  10. [lld][WebAssembly] Do not remove name section with --strip-debug (details)
  11. [PowerPC] Implement partial vector ld/st builtins for XL compatibility (details)
  12. [compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources (details)
  13. [TypePromotion] Remove redundant if. NFC (details)
  14. [amdgpu] Add 64-bit PC support when expanding unconditional branches. (details)
  15. Fix clang regression test after 5c486ce0 (details)
  16. [libc++] Set the target triple by default in the standalone build (details)
  17. [libc++] Implement the output_iterator and output_range concepts (details)
  18. [OpenMP][NFC] Remove unncessary capture in RAII struct (details)
  19. [PowerPC] Add implicit-def RM to instructions mtfsb[01] (details)
  20. Fix clang debug info irgen of i128 enums (details)
  21. [SimplifyCFG] Remove stale comment after d7378259aa, NFC (details)
  22. [lldb][NFC] Delete unused and commented out DWARF constants (details)
  23. [AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic. (details)
  24. [LV] Don't let ForceTargetInstructionCost override Invalid cost. (details)
Commit 055fa446fd4412c2006e9bc56b31da5afcc5da62 by rob.suderman
[mlir][tosa] Disable tosa shape verification between operands/results

Tosa shape verification prevent shape propagation when coming from a dialect
of known shape. Relax this constraint to allow ingestion / shape propagation
from these other dialects.

Differential Revision: https://reviews.llvm.org/D106610
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
Commit 6b9aba43a2392c307694229261c2be66557b6e88 by aheejin
[WebAssembly] Improve pseudocode in LowerEmscriptenEHSjLj

Both `__THREW__` and `__threwValue` are global variables, and we have
been distinguishing the global variable `__THREW__` and the loaded value
`%__THREW__.val` in comments but not doing it for `__threwValue`. Made
the pseudocode comments consistent for both variables.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D106524
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit 016ae7df95f2d30bc8e44d5e06571e7510770379 by michaelrj
[libc] add scudo wrappers to llvm libc

The previous patch included the implementations for the scudo allocator,
but not the wrappers. This change fixes that.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106718
The file was modifiedlibc/lib/CMakeLists.txt
Commit dec34104bfa505f39bb81d24c9ca064a4a03c88a by Amara Emerson
[GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner.

Differential Revision: https://reviews.llvm.org/D106761
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
Commit 0d41d21929d4366997e67f986689eef0253547b6 by Amara Emerson
[AArch64][GlobalISel] Enable some select combines after legalization.

The legalizer generates selects for some operations, which can have constant
condition values, resulting in lots of dead code if it's not folded away.

Differential Revision: https://reviews.llvm.org/D106762
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
Commit 5c486ce04db4d33ae5be65dac4a03d1b0f46f3e2 by efriedma
[LLVM IR] Allow volatile stores to trap.

Proposed alternative to D105338.

This is ugly, but short-term I think it's the best way forward: first,
let's formalize the hacks into a coherent model. Then we can consider
extensions of that model (we could have different flavors of volatile
with different rules).

Differential Revision: https://reviews.llvm.org/D106309
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/FunctionAttrs/nosync.ll
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/LICM/sink-debuginfo-preserve.ll
Commit 6af8d360546e01ee2e8c8c45fb5d0cf39fcda462 by Amara Emerson
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.

These are generated as a byproduce of legalization.

Differential Revision: https://reviews.llvm.org/D106768
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
Commit a98f394e81f4dd70dc2a4a3a6640b10a6144cc3f by gclayton
[LLDB][GUI] Resolve paths in file/directory fields

This patch resolves the paths in the file/directory fields before
performing checks. Those checks are applied on the file system if
m_need_to_exist is true, so remote files can set this to false to avoid
performing host-side file system checks. Additionally, methods to get
a resolved and a direct file specs were added to be used by client code.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D106553
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
Commit 2a7ee6b5c12444255726b9fd1b276468a7a698d9 by kevin.neal
[FPEnv][InstSimplify] Enable more folds for constrained fadd

Precommit tests, try 2. My tree is up-to-date as of this morning so this
should go better than my first try.
The file was addedllvm/test/Transforms/InstSimplify/strictfp-fadd.ll
Commit cf54424a46ffb505bd1a117a44fc30c01bbff882 by dschuff
[lld][WebAssembly] Do not remove name section with --strip-debug

Leave the name section in the output when using the --strip-debug
flag. This treats it more like ELF symbol tables, as the name
section has similar uses at runtime (e.g. wasm engines understand
it and it can be used for symbolization at runtime).

Fixes https://github.com/emscripten-core/emscripten/issues/14623

Differential Revision: https://reviews.llvm.org/D106728
The file was modifiedlld/test/wasm/weak-undefined.s
The file was modifiedlld/wasm/SyntheticSections.h
The file was modifiedlld/test/wasm/strip-debug.test
Commit 1c50a5da364fd57905ec170ed9ba64d3c7e416f3 by nemanja.i.ibm
[PowerPC] Implement partial vector ld/st builtins for XL compatibility

XL provides functions __vec_ldrmb/__vec_strmb for loading/storing a
sequence of 1 to 16 bytes in big endian order, right justified in the
vector register (regardless of target endianness).
This is equivalent to vec_xl_len_r/vec_xst_len_r which are only
available on Power9.

This patch simply uses the Power9 functions when compiled for Power9,
but provides a more general implementation for Power8.

Differential revision: https://reviews.llvm.org/D106757
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-vec-error.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/CodeGen/builtins-ppc-ld-st-rmb.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
Commit b31080c596246bc26d2493cfd5e07f053cf9541c by raul
[compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources

On Apple platforms the builtins may be built for both arm64 and arm64e.
With Makefile generators separate targets are built using Make sub-invocations.
This causes a race when creating the symlink which may sometimes fail.

Work around this by using a custom target that the builtin targets depend on.
This causes any sub-invocations to depend on the symlinks having been created before.

Mailing list thread: https://lists.llvm.org/pipermail/llvm-dev/2021-July/151822.html

Reviewed By: thakis, steven_wu

Differential Revision: https://reviews.llvm.org/D106305
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt
Commit 14e356d121cd3f49a1f78f67a5b2e605c7d063f6 by craig.topper
[TypePromotion] Remove redundant if. NFC

The same condition was checked in the previous if. Maybe this was
a bad merge resolution?
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
Commit b0402a35fc882ad582ddf128833e531cf2b7f657 by michael.hliao
[amdgpu] Add 64-bit PC support when expanding unconditional branches.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D106445
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
The file was modifiedllvm/test/MC/AMDGPU/expressions.s
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was addedllvm/test/MC/AMDGPU/offset-expr.s
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
Commit 0fb16d5ad126a14213ceee6b20b86c721ea49d4e by efriedma
Fix clang regression test after 5c486ce0
The file was modifiedclang/test/CodeGenOpenCL/convergent.cl
Commit 069428b6f73bdfb7bba13d461a2f57beb86b6aa7 by Louis Dionne
[libc++] Set the target triple by default in the standalone build

Even though the standalone build is deprecated, some people are still
relying on it (including libc++ itself for some configurations). Setting
the target triple will ensure that the build and the test suite behaves
consistently in the standalone and normal builds.

Differential Revision: https://reviews.llvm.org/D106800
The file was modifiedlibcxx/utils/libcxx/test/dsl.py
The file was modifiedlibcxx/cmake/Modules/HandleOutOfTreeLLVM.cmake
The file was modifiedlibcxx/utils/libcxx/test/params.py
Commit 7b28c5d3765c5f48a1502693331b22330d609f88 by Louis Dionne
[libc++] Implement the output_iterator and output_range concepts

Differential Revision: https://reviews.llvm.org/D106704
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was addedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.output/output_iterator.compile.pass.cpp
The file was modifiedlibcxx/include/__iterator/concepts.h
The file was addedlibcxx/test/std/ranges/range.req/range.refinements/output_range.compile.pass.cpp
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/docs/Status/RangesPaper.csv
The file was modifiedlibcxx/include/ranges
Commit e757a3b05fd99bb5b5e6460c1d59cd0a170a6033 by huberjn
[OpenMP][NFC] Remove unncessary capture in RAII struct

Summary:
There was an unnecessary variable assigned to the information cache when we
only need it in the constructor to extract the function declaration.
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit 2d788959edda2155398ed760d19aee84259ed814 by lei
[PowerPC] Add implicit-def RM to instructions mtfsb[01]

This is a followup patch for D105930 to add implicit-def of RM for
mtfsb[01] instructions as per review comments.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D106603
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
Commit 323049329939becf690adbeeff9f5f7e219075ec by rnk
Fix clang debug info irgen of i128 enums

DIEnumerator stores an APInt as of April 2020, so now we don't need to
truncate the enumerator value to 64 bits. Fixes assertions during IRGen.

Split from D105320, thanks to Matheus Izvekov for the test case and
report.

Differential Revision: https://reviews.llvm.org/D106585
The file was modifiedllvm/include/llvm/IR/DIBuilder.h
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedllvm/lib/IR/DIBuilder.cpp
The file was addedclang/test/CodeGenCXX/debug-info-enum-i128.cpp
Commit d56e6985528bae0305c1633fd8db1658d1b28356 by rnk
[SimplifyCFG] Remove stale comment after d7378259aa, NFC
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit e42edce4a349efeedde2ffd07a26a6335178d24b by apl
[lldb][NFC] Delete unused and commented out DWARF constants

I cannot find any users of these anywhere and they have been commented out
for years.
The file was modifiedlldb/include/lldb/Core/dwarf.h
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbdwarf.py
Commit e745277012ec05d1e6f980e05f2a3ea7c827eeec by sander.desmalen
[AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic.

This change moves most of `sve-inductions.ll` to non-AArch64 specific
LV tests using the `-target-supports-scalable-vectors` flag, because they're
not explicitly AArch64-specific. One test builds on AArch64-specific
knowledge regarding masked loads/stores, and remains in sve-inductions.ll.
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
The file was addedllvm/test/Transforms/LoopVectorize/scalable-inductions.ll
Commit 13ccb097258a244498aa760b878a23de721af29f by sander.desmalen
[LV] Don't let ForceTargetInstructionCost override Invalid cost.

Invalid costs can be used to avoid vectorization with a given VF, which is
used for scalable vectors to avoid things that the code-generator cannot
handle. If we override the cost using the -force-target-instruction-cost
option of the LV, we would override this mechanism, rendering the flag useless.

This change ensures the cost is only overriden when the original cost that
was calculated is valid. That allows the flag to be used in combination
with the -scalable-vectorization option.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106677
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll