Commit
2e5c47eda14a547c21e57d869a1e51ffd9938289
by contactRevert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h"
This reverts commit 6f99e1aa58e3566fcce689bc986b7676e818c038.
|
 | lldb/source/Symbol/Type.cpp |
| lldb/include/lldb/Symbol/Type.h |
Commit
25a7e4b9f7c60883c677a246641287744b0bb479
by Vitaly Buka[sanitizer] Add Leb128 encoding/decoding
Reviewed By: dvyukov, kstoimenov
Differential Revision: https://reviews.llvm.org/D114464
|
| compiler-rt/lib/sanitizer_common/CMakeLists.txt |
 | compiler-rt/lib/sanitizer_common/sanitizer_leb128.h |
| compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt |
| compiler-rt/lib/sanitizer_common/tests/sanitizer_leb128_test.cpp |
Commit
fde937748b7def9f9d349b85bf9077f07a84b724
by mtrofin[NFC] Header comment in X86RegisterBanks.td referred to Aarch64
Differential Revision: https://reviews.llvm.org/D114763
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| llvm/lib/Target/X86/X86RegisterBanks.td |
Commit
4ae2222e143b8541b6567f9852d9600a17cc9426
by kai.wang[RISCV] Add a test case to show the bug in RISCVFrameLowering.
If the number of arguments is too large to use register passing, it
needs to occupy stack space to pass the arguments to the callee. There
are two scenarios. One is to reserve the space in prologue and the other
is to reserve the space before the function calls. When we need to
reserve the stack space before function calls, the stack pointer is
adjusted. Under the scenario, we should not use stack pointer to access
the stack objects. It looks like,
callseq_start -> sp = sp - reserved_space
//
// We should not use SP to access stack objects in this area.
//
call @foo
callseq_end -> sp = sp + reserved_space
Differential Revision: https://reviews.llvm.org/D114245
|
| llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll |
Commit
9a88566537177df75af1fcde69e0626fed2b1145
by kai.wang[RISCV] Fix a bug in RISCVFrameLowering.
When we have out-going arguments passing through stack and we do not
reserve the stack space in the prologue. Use BP to access stack objects
after adjusting the stack pointer before function calls.
callseq_start -> sp = sp - reserved_space
//
// Use FP to access fixed stack objects.
// Use BP to access non-fixed stack objects.
//
call @foo
callseq_end -> sp = sp + reserved_space
Differential Revision: https://reviews.llvm.org/D114246
|
| llvm/lib/Target/RISCV/RISCVFrameLowering.cpp |
| llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll |
Commit
a06d3527563503f17794bf119ee471d0ca2669ca
by Vitaly Buka[NFC][sanitizer] Track progress of populating the block
In multi-threaded application concurrent StackStore::Store may
finish in order different from assigned Id. So we can't assume
that after we switch writing the next block the previous is done.
The workaround is to count exact number of uptr stored into the block,
including skipped tail/head which were not able to fit entire trace.
Depends on D114490.
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D114493
|
| compiler-rt/lib/sanitizer_common/sanitizer_stack_store.h |
| compiler-rt/lib/sanitizer_common/sanitizer_stack_store.cpp |
| compiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp |
| compiler-rt/lib/sanitizer_common/tests/sanitizer_stack_store_test.cpp |
Commit
b121d23a9cea711e832505c0b2495de6a51591c1
by craig.topper[RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls.
Prevents crashes or cannot select errors.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D113822
|
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
| llvm/test/CodeGen/RISCV/half-intrinsics.ll |
Commit
f1d8345a2ab3c343929212d1c62174cfaa46e71a
by carrot[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
Currently we create register mappings for registers used only once in current
MBB. For registers with multiple uses, when all the uses are in the current MBB,
we can also create mappings for them similarly according to the last use.
For example
%reg101 = ...
= ... reg101
%reg103 = ADD %reg101, %reg102
We can create mapping between %reg101 and %reg103.
Differential Revision: https://reviews.llvm.org/D113193
|
| llvm/test/CodeGen/X86/setcc-combine.ll |
| llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll |
| llvm/test/CodeGen/X86/lzcnt-cmp.ll |
| llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll |
| llvm/test/CodeGen/X86/vector-trunc-usat.ll |
| llvm/test/CodeGen/X86/fpclamptosat.ll |
| llvm/test/CodeGen/X86/vector-narrow-binop.ll |
| llvm/test/CodeGen/X86/sat-add.ll |
| llvm/test/CodeGen/X86/pmulh.ll |
| llvm/test/CodeGen/X86/haddsub-3.ll |
| llvm/test/CodeGen/X86/vector-shift-ashr-128.ll |
| llvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll |
| llvm/test/CodeGen/X86/nontemporal-loads.ll |
| llvm/test/CodeGen/SystemZ/int-div-01.ll |
| llvm/test/CodeGen/X86/smul_fix.ll |
| llvm/test/CodeGen/X86/sdiv_fix_sat.ll |
| llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll |
| llvm/test/CodeGen/X86/vector-lzcnt-128.ll |
| llvm/test/CodeGen/X86/vselect-packss.ll |
| llvm/lib/CodeGen/TwoAddressInstructionPass.cpp |
| llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll |
| llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll |
| llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll |
| llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll |
| llvm/test/CodeGen/X86/bypass-slow-division-32.ll |
| llvm/test/CodeGen/SystemZ/int-mul-08.ll |
| llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll |
| llvm/test/CodeGen/X86/vector-fshr-128.ll |
| llvm/test/CodeGen/X86/atomic-unordered.ll |
| llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll |
| llvm/test/CodeGen/X86/combine-bitselect.ll |
| llvm/test/CodeGen/X86/ctpop-combine.ll |
| llvm/test/CodeGen/X86/rem.ll |
| llvm/test/CodeGen/X86/slow-pmulld.ll |
| llvm/test/CodeGen/X86/uadd_sat.ll |
| llvm/test/CodeGen/X86/vector-trunc-ssat.ll |
| llvm/test/CodeGen/X86/popcnt.ll |
| llvm/test/CodeGen/X86/combine-sdiv.ll |
| llvm/test/CodeGen/X86/vector-trunc-packus.ll |
| llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll |
| llvm/test/CodeGen/X86/haddsub.ll |
| llvm/test/CodeGen/X86/vector-fshl-128.ll |
| llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll |
| llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll |
| llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll |
| llvm/test/CodeGen/X86/bmi2.ll |
| llvm/test/CodeGen/SystemZ/int-div-03.ll |
| llvm/test/CodeGen/X86/vec-strict-cmp-128.ll |
| llvm/test/CodeGen/X86/vector-shift-lshr-128.ll |
| llvm/test/CodeGen/X86/pull-binop-through-shift.ll |
| llvm/test/CodeGen/ARM/usat.ll |
| llvm/test/CodeGen/ARM/ssat.ll |
| llvm/test/CodeGen/ARM/fpclamptosat.ll |
| llvm/test/CodeGen/X86/divide-by-constant.ll |
| llvm/test/CodeGen/X86/horizontal-sum.ll |
| llvm/test/CodeGen/X86/umul_fix.ll |
| llvm/test/CodeGen/X86/haddsub-shuf.ll |
| llvm/test/CodeGen/X86/bitreverse.ll |
| llvm/test/CodeGen/X86/vector-bitreverse.ll |
| llvm/test/CodeGen/X86/vector-tzcnt-128.ll |
| llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll |
| llvm/test/CodeGen/X86/umul_fix_sat.ll |
| llvm/test/CodeGen/X86/vector-popcnt-128.ll |
| llvm/test/CodeGen/X86/uadd_sat_vec.ll |
| llvm/test/CodeGen/X86/vec_umulo.ll |
| llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll |
| llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll |
| llvm/test/CodeGen/SystemZ/int-div-04.ll |
| llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll |
| llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll |
| llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll |
| llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll |
| llvm/test/CodeGen/X86/umul-with-overflow.ll |
| llvm/test/CodeGen/X86/vec_ctbits.ll |
| llvm/test/CodeGen/X86/shl-crash-on-legalize.ll |
| llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll |
| llvm/test/CodeGen/X86/vector-ext-logic.ll |
| llvm/test/CodeGen/X86/smul_fix_sat.ll |
| llvm/test/CodeGen/X86/shift-combine.ll |
Commit
5297cbf04532f61fe18570982f4f2a3095d08c13
by Christudasan.Devadasan[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc
Greedy register allocator prefers to move a constrained
live range into a larger allocatable class over spilling
them. This patch defines the necessary superclasses for
vector registers. For subtargets that support copy between
VGPRs and AGPRs, the vector register spills during regalloc
now become just copies.
Reviewed By: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D109301
|
| llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll |
| llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll |
| llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll |
| llvm/lib/Target/AMDGPU/SIRegisterInfo.h |
| llvm/test/CodeGen/AMDGPU/spill-agpr.ll |
| llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp |
| llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir |
| llvm/lib/Target/AMDGPU/SIInstrInfo.cpp |
| llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir |
Commit
0150645bf5ae0d55866e77d2bec5aad4e5226b7c
by kyulee[DebugInfo] Do not replace existing nodes from DICompileUnit
When creating a new DIBuilder with an existing DICompileUnit, load the
DINodes from the current DICompileUnit so they don't get overwritten.
This is done in the MachineOutliner pass, but it didn't change the CU so
the bug never appeared. We need this if we ever want to add DINodes to
the CU after it has been created, e.g., DIGlobalVariables.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D114556
|
| llvm/unittests/IR/IRBuilderTest.cpp |
| llvm/lib/IR/DIBuilder.cpp |
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