1. Revert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h" (details)
  2. [sanitizer] Add Leb128 encoding/decoding (details)
  3. [NFC] Header comment in referred to Aarch64 (details)
  4. [RISCV] Add a test case to show the bug in RISCVFrameLowering. (details)
  5. [RISCV] Fix a bug in RISCVFrameLowering. (details)
  6. [NFC][sanitizer] Track progress of populating the block (details)
  7. [RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls. (details)
  8. [TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB (details)
  9. [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc (details)
  10. [DebugInfo] Do not replace existing nodes from DICompileUnit (details)
Commit 2e5c47eda14a547c21e57d869a1e51ffd9938289 by contact
Revert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h"

This reverts commit 6f99e1aa58e3566fcce689bc986b7676e818c038.
The file was modifiedlldb/source/Symbol/Type.cpp
The file was modifiedlldb/include/lldb/Symbol/Type.h
Commit 25a7e4b9f7c60883c677a246641287744b0bb479 by Vitaly Buka
[sanitizer] Add Leb128 encoding/decoding

Reviewed By: dvyukov, kstoimenov

Differential Revision:
The file was modifiedcompiler-rt/lib/sanitizer_common/CMakeLists.txt
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_leb128.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
The file was addedcompiler-rt/lib/sanitizer_common/tests/sanitizer_leb128_test.cpp
Commit fde937748b7def9f9d349b85bf9077f07a84b724 by mtrofin
[NFC] Header comment in referred to Aarch64

Differential Revision:
The file was modifiedllvm/lib/Target/X86/
Commit 4ae2222e143b8541b6567f9852d9600a17cc9426 by
[RISCV] Add a test case to show the bug in RISCVFrameLowering.

If the number of arguments is too large to use register passing, it
needs to occupy stack space to pass the arguments to the callee. There
are two scenarios. One is to reserve the space in prologue and the other
is to reserve the space before the function calls. When we need to
reserve the stack space before function calls, the stack pointer is
adjusted. Under the scenario, we should not use stack pointer to access
the stack objects. It looks like,

callseq_start  ->  sp = sp - reserved_space
// We should not use SP to access stack objects in this area.
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision:
The file was addedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
Commit 9a88566537177df75af1fcde69e0626fed2b1145 by
[RISCV] Fix a bug in RISCVFrameLowering.

When we have out-going arguments passing through stack and we do not
reserve the stack space in the prologue. Use BP to access stack objects
after adjusting the stack pointer before function calls.

callseq_start  ->  sp = sp - reserved_space
// Use FP to access fixed stack objects.
// Use BP to access non-fixed stack objects.
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision:
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
Commit a06d3527563503f17794bf119ee471d0ca2669ca by Vitaly Buka
[NFC][sanitizer] Track progress of populating the block

In multi-threaded application concurrent StackStore::Store may
finish in order different from assigned Id. So we can't assume
that after we switch writing the next block the previous is done.

The workaround is to count exact number of uptr stored into the block,
including skipped tail/head which were not able to fit entire trace.

Depends on D114490.

Reviewed By: morehouse

Differential Revision:
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stack_store.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stack_store.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stack_store_test.cpp
Commit b121d23a9cea711e832505c0b2495de6a51591c1 by craig.topper
[RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls.

Prevents crashes or cannot select errors.

Reviewed By: frasercrmck

Differential Revision:
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/half-intrinsics.ll
Commit f1d8345a2ab3c343929212d1c62174cfaa46e71a by carrot
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB

Currently we create register mappings for registers used only once in current
MBB. For registers with multiple uses, when all the uses are in the current MBB,
we can also create mappings for them similarly according to the last use.
For example

    %reg101 = ...
            = ... reg101
    %reg103 = ADD %reg101, %reg102

We can create mapping between %reg101 and %reg103.

Differential Revision:
The file was modifiedllvm/test/CodeGen/X86/setcc-combine.ll
The file was modifiedllvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
The file was modifiedllvm/test/CodeGen/X86/lzcnt-cmp.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
The file was modifiedllvm/test/CodeGen/X86/fpclamptosat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-narrow-binop.ll
The file was modifiedllvm/test/CodeGen/X86/sat-add.ll
The file was modifiedllvm/test/CodeGen/X86/pmulh.ll
The file was modifiedllvm/test/CodeGen/X86/haddsub-3.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-128.ll
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
The file was modifiedllvm/test/CodeGen/X86/nontemporal-loads.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-01.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix.ll
The file was modifiedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-lzcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/vselect-packss.ll
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/sse3-avx-addsub-2.ll
The file was modifiedllvm/test/CodeGen/X86/bypass-slow-division-32.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-mul-08.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-128.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
The file was modifiedllvm/test/CodeGen/X86/combine-bitselect.ll
The file was modifiedllvm/test/CodeGen/X86/ctpop-combine.ll
The file was modifiedllvm/test/CodeGen/X86/rem.ll
The file was modifiedllvm/test/CodeGen/X86/slow-pmulld.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/popcnt.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sdiv.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/haddsub.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-128.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
The file was modifiedllvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
The file was modifiedllvm/test/CodeGen/X86/bmi2.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-03.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-cmp-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-128.ll
The file was modifiedllvm/test/CodeGen/X86/pull-binop-through-shift.ll
The file was modifiedllvm/test/CodeGen/ARM/usat.ll
The file was modifiedllvm/test/CodeGen/ARM/ssat.ll
The file was modifiedllvm/test/CodeGen/ARM/fpclamptosat.ll
The file was modifiedllvm/test/CodeGen/X86/divide-by-constant.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
The file was modifiedllvm/test/CodeGen/X86/umul_fix.ll
The file was modifiedllvm/test/CodeGen/X86/haddsub-shuf.ll
The file was modifiedllvm/test/CodeGen/X86/bitreverse.ll
The file was modifiedllvm/test/CodeGen/X86/vector-bitreverse.ll
The file was modifiedllvm/test/CodeGen/X86/vector-tzcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
The file was modifiedllvm/test/CodeGen/X86/umul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-04.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/X86/umul-with-overflow.ll
The file was modifiedllvm/test/CodeGen/X86/vec_ctbits.ll
The file was modifiedllvm/test/CodeGen/X86/shl-crash-on-legalize.ll
The file was modifiedllvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/X86/vector-ext-logic.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/shift-combine.ll
Commit 5297cbf04532f61fe18570982f4f2a3095d08c13 by Christudasan.Devadasan
[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc

Greedy register allocator prefers to move a constrained
live range into a larger allocatable class over spilling
them. This patch defines the necessary superclasses for
vector registers. For subtargets that support copy between
VGPRs and AGPRs, the vector register spills during regalloc
now become just copies.

Reviewed By: rampitec, arsenm

Differential Revision:
The file was addedllvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
The file was addedllvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
Commit 0150645bf5ae0d55866e77d2bec5aad4e5226b7c by kyulee
[DebugInfo] Do not replace existing nodes from DICompileUnit

When creating a new DIBuilder with an existing DICompileUnit, load the
DINodes from the current DICompileUnit so they don't get overwritten.
This is done in the MachineOutliner pass, but it didn't change the CU so
the bug never appeared. We need this if we ever want to add DINodes to
the CU after it has been created, e.g., DIGlobalVariables.

Reviewed By: dblaikie

Differential Revision:
The file was modifiedllvm/unittests/IR/IRBuilderTest.cpp
The file was modifiedllvm/lib/IR/DIBuilder.cpp