1. [mlir][python] Add python binding for AffineMapAttribute. (details)
  2. Basic block sections should enable function sections implicitly. (details)
  3. [SampleFDO] Reapply: Refactor SampleProfile.cpp (details)
  4. [gn build] Port 6fd5ccff72ee (details)
  5. [AMDGPU] Correct rmw atomics s_waitcnt generation (details)
  6. [llvm-libtool] Emit warnings for files without symbols (details)
Commit 4c3f1be84f76ef31f767d3d271ee8bdcd2be5a02 by stellaraccident
[mlir][python] Add python binding for AffineMapAttribute.

Differential Revision:
The file was modifiedmlir/test/Bindings/Python/
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
Commit d1a838babcc3360eb7e311006a4acd1eee61b8f2 by tmsriram
Basic block sections should enable function sections implicitly.

Basic block sections enables function sections implicitly, this is not needed
and is inefficient with "=list" option.

We had basic block sections enable function sections implicitly in clang. This
is particularly inefficient with "=list" option as it places functions that do
not have any basic block sections in separate sections. This causes unnecessary
object file overhead for large applications.

This patch disables this implicit behavior. It only creates function sections
for those functions that require basic block sections.

Further, there was an inconistent behavior with llc as llc was not turning on
function sections by default. This patch makes llc and clang consistent and
tests are added to check the new behavior.

This is the first of two patches and this adds functionality in LLVM to
create a new section for the entry block if function sections is not

Differential Revision:
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/lib/Target/TargetLoweringObjectFile.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-list.ll
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-unreachable.ll
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections_1.ll
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections.ll
Commit 6fd5ccff72eeaffcb3b3ba2696282015aab755bc by xur
[SampleFDO] Reapply: Refactor SampleProfile.cpp

Reapply patch after fixing buildbot failure.
Refactor SampleProfile.cpp to use the core code in CodeGen.
The main changes are:
(1) Move SampleProfileLoaderBaseImpl class to a header file.
(2) Split SampleCoverageTracker to a head file and a cpp file.
(3) Move the common codes (common options and callsiteIsHot())
to the common cpp file.

Differential Revision:
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was addedllvm/lib/Transforms/Utils/SampleProfileLoaderBaseUtil.cpp
The file was addedllvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
The file was modifiedllvm/lib/Transforms/Utils/CMakeLists.txt
The file was addedllvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseUtil.h
Commit f456959a9331e628e8214930e6d4dceb34d75ea0 by llvmgnsyncbot
[gn build] Port 6fd5ccff72ee
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/Utils/
Commit c62b737ad655f189cf76f4324ba04317133d6648 by Tony.Tye
[AMDGPU] Correct rmw atomics s_waitcnt generation

The AMD GPU SIMemoryLegalizer was using the ordering address space
rather than the instruction address space when determining the
s_waitcnt to generate to ensure that a read-modify-write atomic has
completed. This resulted in additional unnecessary counters being
waited on.

Differential Revision:
The file was modifiedllvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
Commit cdcb60a820571f7384920fb534ce23e7568bfc03 by alexshap
[llvm-libtool] Emit warnings for files without symbols

1. Emit warnings for files without symbols.
2. Add -no_warning_for_no_symbols.

Test plan: make check-all

Differential revision:
The file was modifiedllvm/docs/CommandGuide/llvm-libtool-darwin.rst
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was addedllvm/test/tools/llvm-libtool-darwin/no-symbols-warning.test


  1. [test-suite] Fix runtime-error of SPEC2017 CPU CactuBSSN floating point tests. (details)
Commit 553e5905b7bce187da50901e91f53097adc5122d by naromero
[test-suite] Fix runtime-error of SPEC2017 CPU CactuBSSN floating point tests.

Run CactcuBSSN tests out of run directory.

Reviewed By: Meinersbur

Differential Revision:
The file was modifiedExternal/SPEC/CFP2017rate/507.cactuBSSN_r/CMakeLists.txt (diff)