1. Add @llvm.coro.async.size.replace intrinsic. (details)
  2. [AMDGPU] Rename a prefix for sanity. NFC. (details)
  3. [JumpThreading] Update computeValueKnownInPredecessors to recognize logical and/or patterns (details)
  4. [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 (details)
  5. [LV] Allow tryToCreateWidenRecipe to return a VPValue, use for blends. (details)
Commit 01b4890e47f0988695e68ea4e1fd6961b645ee73 by aschwaighofer
Add @llvm.coro.async.size.replace intrinsic.

The new intrinsic replaces the size in one specified AsyncFunctionPointer with
the size in another.  This ability is necessary for functions which merely
forward to async functions such as those defined for partial applications.

Reviewed By: aschwaighofer

Differential Revision:
The file was modifiedllvm/lib/Transforms/Coroutines/CoroCleanup.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInstr.h
The file was modifiedllvm/test/Transforms/Coroutines/coro-async.ll
The file was modifiedllvm/include/llvm/IR/
The file was modifiedllvm/lib/Transforms/Coroutines/Coroutines.cpp
Commit 64831fb0896f7be507fb73618ad8d2c086b7721d by jay.foad
[AMDGPU] Rename a prefix for sanity. NFC.
The file was modifiedllvm/test/MC/AMDGPU/sopp-err.s
Commit 19c2e129475013a8a36696d475c9d8681ce52614 by aqjune
[JumpThreading] Update computeValueKnownInPredecessors to recognize logical and/or patterns

This allows JumpThreading's computeValueKnownInPredecessors to
recognize select form of and/or patterns as well.
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
Commit 52bc2e7577f338704438e18c95dea756657eca21 by jay.foad
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24

Prefer to keep uniform (non-divergent) multiplies on the scalar ALU when
possible. This significantly improves some game cases by eliminating
v_readfirstlane instructions when the result feeds into a scalar
operation, like the address calculation for a scalar load or store.

Since isDivergent is only an approximation of whether a value is in
SGPRs, it can potentially regress some situations where a uniform value
ends up in a VGPR. These should be rare in real code, although the test
changes do contain a number of examples.

Most of the test changes are just using s_mul instead of v_mul/mad which
is generally better for both register pressure and latency (at least on
GFX10 where sgpr pressure doesn't affect occupancy and vector ALU
instructions have significantly longer latency than scalar ALU). Some
R600 tests now use MULLO_INT instead of MUL_UINT24.

GlobalISel appears to handle more scenarios in the desirable way,
although it can also be thrown off and fails to select the 24-bit
multiplies in some cases.

Alternative solution considered and rejected was to allow selecting
MUL_[UI]24 to S_MUL_I32. I've rejected this because the definition of
those SD operations works is don't-care on the most significant 8 bits,
and this fact is used in some combines via SimplifyDemandedBits.

Based on a patch by Nicolai Hähnle.

Differential Revision:
The file was modifiedllvm/test/CodeGen/AMDGPU/
The file was modifiedllvm/test/CodeGen/AMDGPU/mad_uint24.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/trunc-combine.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-r600.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_int24.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mad_int24.ll
Commit 4efa097eb4c87d7ffe09a95a5b4ff372bdddda85 by flo
[LV] Allow tryToCreateWidenRecipe to return a VPValue, use for blends.

Generalize the return value of tryToCreateWidenRecipe to return either a
newly create recipe or an existing VPValue. Use this to avoid creating
unnecessary VPBlendRecipes.

Fixes PR44800.
The file was modifiedllvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp