SuccessChanges

Summary

  1. [clang][sema] Ignore xor-used-as-pow if both sides are macros (details)
  2. Fix a test case that should check whether or not it is passed into lld (details)
  3. [RISCV] Add isel pattern to match X > -1 to bgez. (details)
  4. [arm builtin crosscompile docs] alphabetize flags, no behavior change (details)
  5. [arm builtin crosscompile docs] add COMPILER_RT_BUILD_MEMPROF=OFF (details)
  6. [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli (details)
  7. [IndVars] Add test cases inspired by PR48965. (details)
Commit 2cc58463caf4c8a43c2954e4206d3647c762ba30 by tbaeder
[clang][sema] Ignore xor-used-as-pow if both sides are macros

This happens in codebases a lot, which use xor where both sides are
macros. Using xor in that case is not the common error-prone 2^6 code
that the warning was introduced for.

Don't diagnose such a use of xor.

Differential Revision: https://reviews.llvm.org/D97445
The file was modifiedclang/lib/Sema/SemaExpr.cpp (diff)
The file was modifiedclang/test/SemaCXX/warn-xor-as-pow.cpp (diff)
Commit 3b7104a2f2033d100aebb605c46fbe0495ea320b by conanap
Fix a test case that should check whether or not it is passed into lld

This test case was causing a PowerPC buildbot to fail as it happened to
be named lld-multistage,
which matches with the original regex and therefore fails the check-not.
This should better represent the desired check.

Differential Revision: https://reviews.llvm.org/D97423
The file was modifiedclang/test/Driver/hip-sanitize-options.hip (diff)
Commit 25c6b7ddd2b4d9631d0aff312b076843c16239d7 by craig.topper
[RISCV] Add isel pattern to match X > -1 to bgez.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D97262
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/branch.ll (diff)
Commit b4f8daa5ec6c7c5a84fe6d36859f1ff38780ffa2 by thakis
[arm builtin crosscompile docs] alphabetize flags, no behavior change
The file was modifiedllvm/docs/HowToCrossCompileBuiltinsOnArm.rst (diff)
Commit 03b7bc0ba1ce3804f92f1c9e990b4aaa54583862 by thakis
[arm builtin crosscompile docs] add COMPILER_RT_BUILD_MEMPROF=OFF

Reported by artok on irc, thanks!
The file was modifiedllvm/docs/HowToCrossCompileBuiltinsOnArm.rst (diff)
Commit 95c68249952803330739b7311dd2bdc7b18e272f by craig.topper
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli

Reviewed By: frasercrmck, arcbbb

Differential Revision: https://reviews.llvm.org/D97408
The file was modifiedllvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll (diff)
Commit 261f219ffc2ad0a0c7b45912e288ba6448911120 by flo
[IndVars] Add test cases inspired by PR48965.
The file was addedllvm/test/Transforms/IndVarSimplify/simplify-pointer-arithmetic.ll