Changes

Summary

  1. [DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes (details)
  2. [ADT] Remove set_is_strict_subset (NFC) (details)
  3. AMDGPU/GlobalISel: Check some remarks for failed legalizations (details)
  4. GlobalISel: Scalarize unaligned vector stores (details)
  5. [VPlan] Add interleave group printing test. (details)
  6. [ARM] Regenerate Thumb PR35481.ll test. NFC (details)
  7. [ARM] Switch order of creating VADDV and VMLAV. (details)
  8. Fixed syntax error that occured in the patch D104974 (details)
  9. [TTI] Make SK_ExtractSubvector matching length-changing only and simplify nested shuffle mask detection chain. (details)
  10. [InstCombine] canonicalize cmp-of-bitcast-of-vector-cmp to use zero constant (details)
  11. [SROA] prevent crash on large memset length (PR50910) (details)
  12. [RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC (details)
  13. [Analysis] improve function signature checking for snprintf (details)
  14. [mlir][sparse] add sparse tensor type conversion operation (details)
  15. [ConstantFold] Get rid of special cases for sizeof etc. (details)
  16. Fix a couple regression tests I missed updating in 2a284782 (details)
  17. Fix the default alignment of i1 vectors. (details)
  18. [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. (details)
  19. [RISCV][Docs] Add description about inline asm constraint for V. (details)
Commit 3a7c82efb8db57f0bf1cfbbd681b3905556bd049 by llvm-dev
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes

If all demanded elements of the BUILD_VECTOR pass a isGuaranteedNotToBeUndefOrPoison check, then we can treat this specific demanded use of the BUILD_VECTOR as guaranteed not to be undef or poison either.

Differential Revision: https://reviews.llvm.org/D107174
The file was modifiedllvm/test/CodeGen/X86/freeze-legalize.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/freeze-constant-fold.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff)
Commit 5f5ce6e9a7eb0f735791662cd49efc2d934796fd by kazu
[ADT] Remove set_is_strict_subset (NFC)

The last use was removed on Mar 13, 2020 in commit
6b57d7f57d2cec7ec717757a6a52f2203d6e9db7.
The file was modifiedllvm/include/llvm/ADT/SetOperations.h (diff)
Commit 43c7cb9a3cf528a6e4e81acb6752b273c6e60300 by Matthew.Arsenault
AMDGPU/GlobalISel: Check some remarks for failed legalizations

The load/store tests are giant and have some cases that fail in them,
but it's hard to tell which ones are really failing. Check the remarks
to make it easier to track.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (diff)
Commit ebc17a0d68208a967fe8e13e1874874228dda622 by Matthew.Arsenault
GlobalISel: Scalarize unaligned vector stores

This has the same problems and limitations as the load path.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (diff)
Commit c726b627ad0ba29af9e46901f695b2f7fcc2a661 by flo
[VPlan] Add interleave group printing test.
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll (diff)
Commit 85d6045b88aee1d7d92eacec0099984911d7202d by david.green
[ARM] Regenerate Thumb PR35481.ll test. NFC
The file was modifiedllvm/test/CodeGen/Thumb/PR35481.ll (diff)
Commit 15a1d7e839229f3d9f5fd0a2e1255236a8f3565a by david.green
[ARM] Switch order of creating VADDV and VMLAV.

It can be beneficial to attempt to try the larger VMLAV patterns before
VADDV, in case both may match the same code.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
Commit ad28ff71647503c0a93f8b23a04844484f26f52b by pyadav2299
Fixed syntax error that occured in the patch D104974
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst (diff)
Commit 66743d772682f4f09adf32b5503e3434233d6891 by llvm-dev
[TTI] Make SK_ExtractSubvector matching length-changing only and simplify nested shuffle mask detection chain.

Match style and don't use an else after a return.

Minor cleanup for an upcoming SK_InsertSubvector patch.
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h (diff)
Commit a22c99c3c187bf30717b191503dab5726d3476aa by spatel
[InstCombine] canonicalize cmp-of-bitcast-of-vector-cmp to use zero constant

We can invert a compare constant and preserve the logic
as shown in this sampling:
https://alive2.llvm.org/ce/z/YAXbfs
(In theory, we could deal with non-all-ones/zero as well,
but it doesn't seem worthwhile.)

I noticed this as a part of the x86 codegen difference in
https://llvm.org/PR51259 - it ends up using "test"
instead of "not + cmp" in that example.

This pattern also shows up in https://llvm.org/PR41312
and https://llvm.org/PR50798 .

Differential Revision: https://reviews.llvm.org/D107170
The file was modifiedllvm/test/Transforms/InstCombine/icmp-vec.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h (diff)
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll (diff)
Commit f2a322bfcfbc62b5523f32c4eded6faf2cad2e24 by spatel
[SROA] prevent crash on large memset length (PR50910)

I don't know much about this pass, but we need a stronger
check on the memset length arg to avoid an assert. The
current code was added with D59000.
The test is reduced from:
https://llvm.org/PR50910

Differential Revision: https://reviews.llvm.org/D106462
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp (diff)
The file was modifiedllvm/test/Transforms/SROA/slice-width.ll (diff)
Commit 593059b328cf297d456e08dce8a2e1f8964df0c7 by craig.topper
[RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC

fcvt.w(u) supports multiple rounding modes, but the ISD node
doesn't encode that. So name it to match the rounding mode it uses.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td (diff)
Commit 7f5555776513f174729a686ed01270e23462aaf7 by spatel
[Analysis] improve function signature checking for snprintf

The check for size_t parameter 1 was already here for snprintf_chk,
but it wasn't applied to regular snprintf. This could lead to
mismatching and eventually crashing as shown in:
https://llvm.org/PR50885
The file was modifiedllvm/test/Transforms/InstCombine/simplify-libcalls.ll (diff)
The file was modifiedllvm/lib/Analysis/TargetLibraryInfo.cpp (diff)
Commit 697ea09d47a93d92e40990a38fccf9e246cc22e6 by ajcbik
[mlir][sparse] add sparse tensor type conversion operation

Introduces a conversion from one (sparse) tensor type to another
(sparse) tensor type. See the operation doc for details. Actual
codegen for all cases is still TBD.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D107205
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp (diff)
The file was modifiedmlir/test/Dialect/SparseTensor/invalid.mlir (diff)
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp (diff)
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir (diff)
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td (diff)
Commit 2a2847823f0d13188c43ebdd0baf42a95df750c7 by efriedma
[ConstantFold] Get rid of special cases for sizeof etc.

Target-dependent constant folding will fold these down to simple
constants (or at least, expressions that don't involve a GEP).  We don't
need heroics to try to optimize the form of the expression before that
happens.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51232 .

Differential Revision: https://reviews.llvm.org/D107116
The file was modifiedllvm/lib/IR/ConstantFold.cpp (diff)
The file was modifiedllvm/test/tools/llvm-as/slow-ptrtoint.ll (diff)
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/taskloop_reduction_codegen.cpp (diff)
The file was modifiedllvm/test/Transforms/LowerTypeTests/function-disjoint.ll (diff)
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp (diff)
The file was modifiedllvm/test/Other/constant-fold-gep.ll (diff)
The file was modifiedclang/test/CodeGenCXX/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.cpp (diff)
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.c (diff)
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c (diff)
The file was modifiedclang/test/OpenMP/for_reduction_codegen.cpp (diff)
Commit 6eb2ffbaeb56c8b08ad17c823e1699b964e10b8b by efriedma
Fix a couple regression tests I missed updating in 2a284782
The file was modifiedmlir/test/Target/LLVMIR/openacc-llvm.mlir (diff)
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c (diff)
Commit bdd55b2f1810eb5a2474a36229d08a9e5ca870fc by efriedma
Fix the default alignment of i1 vectors.

Currently, the default alignment is much larger than the actual size of
the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway.  If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).

Differential Revision: https://reviews.llvm.org/D88994
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/spillfill-sve.ll (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c (diff)
The file was modifiedllvm/lib/IR/DataLayout.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/pr41619.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll (diff)
The file was modifiedllvm/test/CodeGen/NVPTX/f16x2-instructions.ll (diff)
The file was modifiedllvm/test/Transforms/SROA/vector-promotion-different-size.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/select-min-max.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-globals.c (diff)
The file was modifiedclang/test/CodeGen/builtins-ppc-pair-mma.c (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c (diff)
The file was modifiedllvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c (diff)
The file was modifiedllvm/test/CodeGen/X86/load-local-v3i129.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-sext.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/avx512-select.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/icmp-vec.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/shufflevec-bitcast.ll (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c (diff)
The file was modifiedllvm/test/CodeGen/NVPTX/param-load-store.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/abs-intrinsic.ll (diff)
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/lower-kernargs.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll (diff)
Commit 8b33839f010fe780fdaf68160be7c45d07fdfcad by kai.wang
[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision: https://reviews.llvm.org/D107139
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/inline-asm.ll (diff)
The file was modifiedclang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c (diff)
Commit ee3aef93b73646ef98f0241498d807a4fb68b78c by kai.wang
[RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision: https://reviews.llvm.org/D106633
The file was modifiedllvm/docs/LangRef.rst (diff)