Commit
3191e8e19f1a7007ddd0e55cee60a51a058c99f5
by jperier[flang] Lower binary and unary elemental array operations
Lower binary and unary elemental operations with an array argument using hlfir.elemental, hlfir.yield_element, and hlfir.apply.
Concat implementation, which is a binary operation, is moved to a BinaryOp struct so that it can leverage this new code.
This patch implements the "not yet implemented: character array expression temp with dynamic length" TODO of the current lowering by splitting the result length computation from the result value computation. That way, the result length computation can be done before lowering the operation to an hlfir.elemental, and the length of the hlfir.elemental is known and storage for it can later be allocated.
It adds a DesignatorOp builder to make "dumb" indexing (without triplets, component, substrings or derived type component ref) easier since indexing needs to be generated for array variables in elemental expression (in the added hlfir::genElementAt helper).
Differential Revision: https://reviews.llvm.org/D140040
|
 | flang/include/flang/Optimizer/HLFIR/HLFIROps.td |
 | flang/lib/Optimizer/Builder/HLFIRTools.cpp |
 | flang/test/Lower/HLFIR/elemental-array-ops.f90 |
 | flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td |
 | flang/include/flang/Optimizer/Builder/HLFIRTools.h |
 | flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp |
 | flang/lib/Lower/ConvertExprToHLFIR.cpp |
Commit
7b36538156b7742627b422c0e6a3a18ec13b99b3
by backlight.zzk[clang-format] make doc for SLS_Inline more clearly
Reviewed By: HazardyKnusperkeks, MyDeveloperDay Differential Revision: https://reviews.llvm.org/D139937
|
 | clang/docs/ClangFormatStyleOptions.rst |
 | clang/include/clang/Format/Format.h |
Commit
8efee510be3c2dd02db0b070055aedf095a3acce
by spatel[InstCombine] limit pair-of-insertelement folds to avoid miscompile
This transform was added with 4446f71ce392. However, as noted in the post-commit feedback, the transform is not safe with an arbitrary base vector because we may leak poison from a narrow element into an adjacent element when bitcasting.
I made the least invasive code change in case we do figure out a way to make this safe.
|
 | llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp |
 | llvm/test/Transforms/InstCombine/insertelt-trunc.ll |
Commit
260ba2f2242253a1e9f5eada5a14ebb25ba689cf
by yjhdandan[NFC][LLDB] Using namespace llvm in EmulateInstructionRISCV
The `EmulateInstructionRISCV` uses a lot of types and functions in `llvm` and `lldb`, this change is to make the code look cleaner.
PS: This patch should be merged before D140032.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D140092
|
 | lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp |
 | lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h |
 | lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp |
 | lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h |
Commit
1cdffa359a3344f966ed309de17af17f8abfbe4d
by anton.sidorenko[MachineCombiner][RISCV] Support inverse instructions reassociation
This patch adds reassociation of FADD/FSUB instruction pairs.
Differential Revision: https://reviews.llvm.org/D138660
|
 | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp |
 | llvm/lib/Target/RISCV/RISCVInstrInfo.h |
 | llvm/test/CodeGen/RISCV/machine-combiner.ll |
Commit
3010f60381bcd828d1b409cfaa576328bcd05bbc
by benjamin.maxwellReland "[TargetLowering] Teach DemandedBits about VSCALE"
Reland with a fixup to avoid converting APInts to int64_t which allowed for overflows (UB) with sufficiently high/low multiplier values.
This allows DemandedBits to see the result of VSCALE will be at most VScaleMax * some compile-time constant. This relies on the vscale_range() attribute being present on the function, with a max set. (This is done by default when clang is targeting AArch64+SVE).
Using this various redundant operations (zexts, sexts, ands, ors, etc) can be eliminated.
Differential Revision: https://reviews.llvm.org/D138508
|
 | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
 | llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll |