|
 | cross-project-tests/debuginfo-tests/llgdb-tests/static-member-2.cpp (diff) |
Commit
51fa03200f7e7e456ccd9b62d522d29429b2d4e6
by Jessica Paquette[MachineOutliner] NFC: Add debug output to overlap pruning code
This had no debug output. Since it was committed as NFC, it had no testcase.
The me of today was nerdsniped by the me of 6 years ago and decided that this
ought to have a testcase and some debug output.
|
| llvm/lib/CodeGen/MachineOutliner.cpp (diff) |
 | llvm/test/CodeGen/AArch64/machine-outliner-overlap.mir |
Commit
5fd51fcba6a5d675e60a59b4ed6c449efe70f41b
by mtrofinReland "[mlgo] Hook up the interactive runner to the mlgo-ed passes"
This reverts commit a772f0bb920a4957fb94dd8dbe45943809fd0ec3.
The main problem was related to how we handled `dbgs()` from the hosted
compiler. Using explicit `subprocess.communicate`, and not relying on
dbgs() being flushed until the end appears to address the problem.
Also some fixes due to some bots running older pythons, so we can't have
nice things like `int | float` and such.
|
| llvm/include/llvm/Analysis/ReleaseModeModelRunner.h (diff) |
| llvm/test/Transforms/Inline/ML/interactive-mode.ll |
| llvm/include/llvm/Analysis/InteractiveModelRunner.h (diff) |
| llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp (diff) |
| llvm/test/Transforms/Inline/ML/Inputs/interactive_main.py |
| llvm/include/llvm/Analysis/InlineModelFeatureMaps.h (diff) |
| llvm/test/CodeGen/MLRegalloc/interactive-mode.ll |
| llvm/lib/Analysis/DevelopmentModeInlineAdvisor.cpp (diff) |
| llvm/lib/CodeGen/MLRegallocPriorityAdvisor.cpp (diff) |
| llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp (diff) |
| llvm/lib/Analysis/models/interactive_host.py |
| llvm/lib/Analysis/MLInlineAdvisor.cpp (diff) |
| llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp (diff) |
| llvm/include/llvm/Analysis/MLModelRunner.h (diff) |
| llvm/test/CodeGen/MLRegalloc/Inputs/interactive_main.py |
| llvm/lib/Analysis/InlineAdvisor.cpp (diff) |
Commit
a7686db801ff6a96da4b6245362c87a627fdafbe
by thomasraoux[mlir][gpu] Allow distributing to different level of IDs without failing
Change map_nested_foreach_to_threads to ignore foreach_thread not
mapping to threads, this will allow us to call
mapNestedForeachToThreadsImpl with different set of ids to lower
multiple levels. Also adds warpIds attributes.
Differential Revision: https://reviews.llvm.org/D143298
|
| mlir/include/mlir/Dialect/GPU/TransformOps/GPUDeviceMappingAttr.td (diff) |
| mlir/lib/Dialect/GPU/IR/GPUDialect.cpp (diff) |
| mlir/test/Dialect/GPU/transform-gpu-failing.mlir (diff) |
| mlir/test/Dialect/GPU/transform-gpu.mlir (diff) |
| mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td (diff) |
| mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp (diff) |
|
| llvm/lib/Analysis/models/log_reader.py (diff) |
|
| llvm/lib/Analysis/models/interactive_host.py (diff) |
| llvm/lib/Analysis/models/log_reader.py (diff) |
Commit
abbd4da2043856f443e3d1c8d2c7627cac93a6ac
by m_borsa[Sanitizers] Fix read buffer overrun in scanning loader commands
The fix only affects Darwin, but to write the test I had to modify
the MemoryMappingLayout class which is used by all OSes,
to allow for mocking of image header (this change should be NFC). Hence no [Darwin] in the subject
so I can get more eyes on it.
While looking for a memory gap to put the shadow area into, the sanitizer code
scans through the loaded images, and for each image it scans through its
loader command to determine the occupied memory ranges.
While doing so, if the 'segment load' (kLCSegment) loader comand is encountered, the command scanning function
returns success (true), but does not decrement the command list iterator counter.
The result is that the function is called again and again, with the iterator counter
now being too high. The command scanner keeps updating the loader command pointer,
by using the command size field.
If the loop counter is too high, the command pointer
lands into unintended area ( beyond <header addr>+sizeof(mac_header64)+header->sizeofcmds ),
and result depends on the random content found there.
The random content interpreted as loader command might contain a large integer value in the
cmdsize field - this value is added to the current loader command pointer,
which might now point to an inaccessible memory address. It can occasionally result
in a crash if it happens to run beyond the mapped memory segment.
Note that when the area after the loader command list
contains zeros or small integers only, the loop will end normally and the problem
will go unnoticed. So it happened until now since having a some big value
after the header area, falling into command size field is a pretty rare situation.
The fix makes sure that the iterator counter gets updated when the segment load (kLCSegment)
loader command is found too, and in the same code location so the updates will always go together.
Undo the changes in the sanitizer_procmaps_mac.cpp to see the test failing.
rdar://101161047
rdar://102819707
Differential Revision: https://reviews.llvm.org/D142164
|
| compiler-rt/lib/sanitizer_common/tests/sanitizer_procmaps_mac_test.cpp |
| compiler-rt/lib/sanitizer_common/sanitizer_procmaps_mac.cpp (diff) |
| compiler-rt/lib/sanitizer_common/sanitizer_procmaps.h (diff) |
| compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt (diff) |
|
| llvm/utils/update_mca_test_checks.py (diff) |
| llvm/utils/update_mir_test_checks.py (diff) |
| llvm/utils/update_test_checks.py (diff) |
| llvm/utils/update_analyze_test_checks.py (diff) |
| llvm/utils/update_cc_test_checks.py (diff) |
| llvm/utils/update_llc_test_checks.py (diff) |
| llvm/utils/UpdateTestChecks/common.py (diff) |
Commit
9921197920fc3e9ad9605bd8fe0e835ca2dd41a5
by spop[AArch64] fix bug #55005 handle DW_CFA_GNU_NegateRAState
GCC on AArch64 uses DW_CFA_GNU_NegateRAState for return address signing.
Differential Revision: https://reviews.llvm.org/D142572
|
| bolt/test/AArch64/Inputs/dw_cfa_gnu_window_save.yaml |
| bolt/lib/Core/Exceptions.cpp (diff) |
| bolt/test/AArch64/dw_cfa_gnu_window_save.test |
|
| llvm/lib/Analysis/models/interactive_host.py (diff) |
| llvm/test/Transforms/Inline/ML/lit.local.cfg |
| llvm/test/CodeGen/MLRegalloc/lit.local.cfg |
|
| llvm/test/CodeGen/MLRegalloc/interactive-mode.ll (diff) |
| llvm/test/Transforms/Inline/ML/interactive-mode.ll (diff) |
|
| mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp (diff) |
| mlir/test/Dialect/Linalg/vectorization.mlir (diff) |
|
| mlir/test/Dialect/Linalg/vectorization.mlir (diff) |
| mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp (diff) |
| mlir/lib/Dialect/Linalg/Utils/Utils.cpp (diff) |
|
| llvm/lib/CodeGen/MachineOutliner.cpp (diff) |
| llvm/test/CodeGen/AArch64/machine-outliner-mapper-debug-output.mir |
 | llvm/test/CodeGen/AArch64/machine-outliner-nooutline-attribute.mir |
|
| clang/include/clang/Driver/Options.td (diff) |
Commit
92d3672452db260f431b9219faf57c5f8c7b876b
by Jessica Paquette[MachineOutliner] Improve mapper statistics
Add a test for statistics as well.
The mapper size stats were nested in a loop unnecessarily. Move them out.
Give existing stats better names, and add one which also tracks the number of
sentinels added.
|
| llvm/lib/CodeGen/MachineOutliner.cpp (diff) |
| llvm/test/CodeGen/AArch64/machine-outliner-mapper-stats.mir |
Commit
d02b9869b2422a7995505e3ef0900da7ef822497
by hankuan.chen[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
In addition, this commit does the following combine
vfmv.v.f + fmv.[dhw].x -> vmv.v.x
vfmv.s.f + fmv.[dhw].x -> vmv.s.x
vfmerge.vfm + fmv.[dhw].x -> vmerge.vxm
Differential Revision: https://reviews.llvm.org/D142953
|
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/float-intrinsics.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/half-imm.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll (diff) |
| llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll (diff) |
| llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (diff) |
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
| llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/round-vp.ll (diff) |
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h (diff) |
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff) |
| llvm/test/CodeGen/RISCV/float-select-verify.ll (diff) |
| llvm/test/CodeGen/RISCV/half-intrinsics.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/rint-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/half-convert.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll (diff) |
| llvm/test/CodeGen/RISCV/half-round-conv.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/select-const.ll (diff) |
| llvm/test/CodeGen/RISCV/zfhmin-imm.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/float-round-conv-sat.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/zfh-imm.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/float-round-conv.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/codemodel-lowering.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll (diff) |
| llvm/test/CodeGen/RISCV/select-optimize-multiple.ll (diff) |
| llvm/test/CodeGen/RISCV/fp-imm.ll (diff) |
| llvm/test/CodeGen/RISCV/float-convert.ll (diff) |
| llvm/test/CodeGen/RISCV/float-imm.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/floor-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/calling-conv-half.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/half-round-conv-sat.ll (diff) |
|
| llvm/test/CodeGen/AArch64/machine-outliner-mapping-stats.mir (diff) |
|
| llvm/test/CodeGen/X86/avx512-cvt.ll (diff) |
| llvm/test/CodeGen/X86/vec-strict-fptoint-256-fp16.ll (diff) |
| llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll (diff) |
| llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
|
| llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll (diff) |
|
| llvm/test/CodeGen/MLRegalloc/lit.local.cfg (diff) |
Commit
8f25e382c5b1bbaafd738f44de856c85ce845bbe
by llvm-dev[X86] Add basic vector handling for ISD::ABDS/ABDU (absolute difference) nodes
I'm intending to add generic legalization in the future, but for now I've added basic support to targets that have the necessary MIN/MAX support to expand to SUB(MAX(X,Y),MIN(X,Y)).
This exposed a couple of issues with the DAG combines - in particular we need to catch trunc(abs(sub(ext(x),ext(y)))) patterns earlier before the SSE/AVX vector trunc expansion folds trigger.
Differential Revision: https://reviews.llvm.org/D142288
|
| llvm/test/CodeGen/X86/abdu-vector-512.ll (diff) |
| llvm/test/CodeGen/X86/abdu-vector-128.ll (diff) |
| llvm/test/CodeGen/X86/midpoint-int-vec-512.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/abds-vector-256.ll (diff) |
| llvm/test/CodeGen/X86/abds-vector-512.ll (diff) |
| llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff) |
| llvm/test/CodeGen/X86/abdu-vector-256.ll (diff) |
| llvm/test/CodeGen/X86/midpoint-int-vec-256.ll (diff) |
| llvm/test/CodeGen/X86/abds-vector-128.ll (diff) |
Commit
5b2549b0d2834a653be60b52885bdc9f21abc2ee
by geek4civicRevert "[AArch64] Unconditionally use DW_EH_PE_indirect|DW_EH_PE_pcrel personality/lsda/ttype encodings"
It causes failurs in clang-interpreter.
This reverts commit 565a1fb1334b8cf510af1338cae3f50815a99f90, aka llvmorg-17-init-1048-g565a1fb1334b
|
| llvm/test/CodeGen/AArch64/pic-eh-stubs.ll (diff) |
| llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll (diff) |
| llvm/test/DebugInfo/AArch64/eh_frame_personality.ll (diff) |
| llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll (diff) |
| llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (diff) |
Commit
4b051b4248bb6f9971dd1cf87fe311ebe9be917e
by paul.walker[SVE][CodeGen] Relax all true isel requirement for predicated operations that have no side effects.
We have isel patterns to allow predicated operations to emit
unpredicated instructions when the predicate is all true. However,
the predicated operations named #_PRED have no requirement for the
result of the inactive lanes and so when those operations have no
side effects, floating point exceptions for example, we can also
safely emit unpredicated instructions. Doing this allows better
register allocation, instruction scheduling and also enables more
usage of instructions that take immediate operands.
NOTE: This patch does not convert all possible instances but
instead focuses on the cases that are testable once D141937 lands.
Depends on D141937
Differential Revision: https://reviews.llvm.org/D141938
|
| llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll (diff) |
| llvm/test/CodeGen/AArch64/sve2-sra.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-undef.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll (diff) |
| llvm/lib/Target/AArch64/SVEInstrFormats.td (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll (diff) |
| llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (diff) |
| llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-undef.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll (diff) |
| llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll (diff) |
|
| llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll (diff) |
|
| llvm/test/CodeGen/AArch64/vldn_shuffle.ll (diff) |
Commit
71fb11ff34691ab08cdb0d174ea058e44ad2fea6
by jhuber6[Libomptarget] Fix disabling amdgpu on non-Linux.
Previously, on non-Linux, amdgpu would get enabled whatever the CPU architecture.
Reviewed By: jhuber6
Differential Revision: https://reviews.llvm.org/D143017
|
| openmp/libomptarget/plugins/cuda/CMakeLists.txt (diff) |
| openmp/libomptarget/plugins-nextgen/cuda/CMakeLists.txt (diff) |
| openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt (diff) |
Commit
cc72df2b7bf091d1c7109460e1ad6656d782eb23
by jhuber6[Libomptarget] Add the same to the other AMD plugin
Summary:
The previous patch also needed to apply this to the other AMDGPU plugin,
this will be removed soon but it should be correct while it's here at
least.
|
| openmp/libomptarget/plugins/amdgpu/CMakeLists.txt (diff) |
Commit
c72aeaad28e1206dac007be9bc27e2c266906645
by llvm-dev[X86] Swap bool reduction predicates in v2i64/v4i32 tests
The v2i64 case has more scope for optimization with ne than ugt cases, and we already have very similar icmp sgt coverage via the v4i64 tests
|
| llvm/test/CodeGen/X86/vector-compare-any_of.ll (diff) |
| llvm/test/CodeGen/X86/vector-compare-all_of.ll (diff) |
Commit
cfba328183f56765721b59e7fe8eb2a261bff340
by arsenm2[GlobalISel] Enable patterns with multiple output operands for the GlobalISelEmitter
This enables writing patterns with mutliple output operands in the input pattern for GlobalISel
|
| llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td |
| llvm/test/TableGen/GlobalISelEmitter-multiple-output.td |
| llvm/utils/TableGen/GlobalISelEmitter.cpp (diff) |
Commit
d0a7bb9b1ad768dfd9b08f66a0e744584b49181f
by springerm[mlir][SCF] Disallow multiple blocks in scf.if "else" region
The "then" region allows only a single block. The same should be the case for the "else" region.
Differential Revision: https://reviews.llvm.org/D143253
|
| mlir/include/mlir/IR/OpBase.td (diff) |
| mlir/include/mlir/Dialect/SCF/IR/SCFOps.td (diff) |
|
| llvm/test/CodeGen/X86/pr53419.ll (diff) |
|
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/vector-compare-any_of.ll (diff) |
Commit
d4a8a59441052165ccdd6ca493ce124be5e80d9e
by david.green[AArch64][GlobalISel] Selection for i8 buildvectors
Legalization for i8 buildvectors is available (as in
615695de27e417d6b444cd983e6f636373afc8c9), but selection
would fail due to i8 types not being handled. This adds
basic support like other type sizes.
Differential Revision: https://reviews.llvm.org/D143002
|
| llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir (diff) |
| llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (diff) |
|
| llvm/include/llvm/ADT/STLFunctionalExtras.h (diff) |
|
| llvm/include/llvm/TableGen/Error.h (diff) |
Commit
8ab762557fb057af1a3015211ee116a975027e78
by sam[compiler-rt] Disable default config files for tests
Without this, if hardening measures like FORTIFY_SOURCE are are in
/etc/clang/*.cfg, many sanitizer tests will die before the sanitizer
can trap the problem being tested, because e.g. the _chk variants
of common functions will abort first.
This gets the number of failing tests down from 42->3 for me (and the
remaining 3 are unrelated).
See: 52ce6776cf98e993c6ec04ae54b52e1354fff917
See: 136f77805fd89cd30e69b3d1204fbf7efedd9a12
Closes: https://github.com/llvm/llvm-project/issues/60394
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D143322
|
| compiler-rt/test/lit.common.cfg.py (diff) |
|
| compiler-rt/test/lit.common.cfg.py (diff) |
|
| llvm/test/Transforms/LoopVectorize/fixed-order-recurrences-memory-instructions.ll |
Commit
056769cdbc60569b01c2f1ff67507f64ad83771f
by douglas.yungRevert "[Sanitizers] Fix read buffer overrun in scanning loader commands"
This reverts commit abbd4da2043856f443e3d1c8d2c7627cac93a6ac.
This change is breaking many bots including:
- http://45.33.8.238/linux/98629/step_10.txt
- https://buildkite.com/llvm-project/llvm-main/builds/6461#01861c4f-9d9c-4781-88f7-d6ccddcb4b06/919-8848
- https://lab.llvm.org/buildbot/#/builders/94/builds/13196
- https://lab.llvm.org/buildbot/#/builders/45/builds/10633
- https://lab.llvm.org/buildbot/#/builders/247/builds/1238
- https://lab.llvm.org/buildbot/#/builders/70/builds/33424
- https://lab.llvm.org/buildbot/#/builders/168/builds/11693
- https://lab.llvm.org/buildbot/#/builders/74/builds/17006
- https://lab.llvm.org/buildbot/#/builders/85/builds/14120
|
| compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt (diff) |
| compiler-rt/lib/sanitizer_common/sanitizer_procmaps.h (diff) |
| compiler-rt/lib/sanitizer_common/sanitizer_procmaps_mac.cpp (diff) |
| compiler-rt/lib/sanitizer_common/tests/sanitizer_procmaps_mac_test.cpp |
|
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
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