Changes

Summary

  1. Tests for D112754 (details)
  2. X86: Fold masked-merge when and-not is not available (details)
  3. [mlir][sparse] generalize sparse tensor output implementation (details)
  4. Add missing header (details)
  5. Revert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h" (details)
  6. [sanitizer] Add Leb128 encoding/decoding (details)
  7. [NFC] Header comment in X86RegisterBanks.td referred to Aarch64 (details)
  8. [RISCV] Add a test case to show the bug in RISCVFrameLowering. (details)
  9. [RISCV] Fix a bug in RISCVFrameLowering. (details)
  10. [NFC][sanitizer] Track progress of populating the block (details)
  11. [RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls. (details)
  12. [TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB (details)
Commit 53dfa52546833d4c8443d976e67fef820ff54426 by Matthias Braun
Tests for D112754

Differential Revision: https://reviews.llvm.org/D113151
The file was addedllvm/test/CodeGen/X86/fold-masked-merge.ll
Commit 87ba99c263afd4c1c090c17eaf51089b1edbc280 by Matthias Braun
X86: Fold masked-merge when and-not is not available

Differential Revision: https://reviews.llvm.org/D112754
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
The file was modifiedllvm/test/CodeGen/X86/fold-masked-merge.ll
The file was modifiedllvm/test/CodeGen/X86/or-lea.ll
The file was modifiedllvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll
Commit 7d4da4e1ab7f79e51db0d5c2a0f5ef1711122dd7 by ajcbik
[mlir][sparse] generalize sparse tensor output implementation

Moves sparse tensor output support forward by generalizing from injective
insertions only to include reductions. This revision accepts the case with all
parallel outer and all reduction inner loops, since that can be handled with
an injective insertion still. Next revision will allow the inner parallel loop
to move inward (but that will require "access pattern expansion" aka "workspace").

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D114399
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_out.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
Commit bd4c6a476fd037fb07a1c484f75d93ee40713d3d by dblaikie
Add missing header
The file was modifiedllvm/lib/Demangle/DLangDemangle.cpp
Commit 2e5c47eda14a547c21e57d869a1e51ffd9938289 by contact
Revert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h"

This reverts commit 6f99e1aa58e3566fcce689bc986b7676e818c038.
The file was modifiedlldb/source/Symbol/Type.cpp
The file was modifiedlldb/include/lldb/Symbol/Type.h
Commit 25a7e4b9f7c60883c677a246641287744b0bb479 by Vitaly Buka
[sanitizer] Add Leb128 encoding/decoding

Reviewed By: dvyukov, kstoimenov

Differential Revision: https://reviews.llvm.org/D114464
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
The file was modifiedcompiler-rt/lib/sanitizer_common/CMakeLists.txt
The file was addedcompiler-rt/lib/sanitizer_common/tests/sanitizer_leb128_test.cpp
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_leb128.h
Commit fde937748b7def9f9d349b85bf9077f07a84b724 by mtrofin
[NFC] Header comment in X86RegisterBanks.td referred to Aarch64

Differential Revision: https://reviews.llvm.org/D114763
The file was modifiedllvm/lib/Target/X86/X86RegisterBanks.td
Commit 4ae2222e143b8541b6567f9852d9600a17cc9426 by kai.wang
[RISCV] Add a test case to show the bug in RISCVFrameLowering.

If the number of arguments is too large to use register passing, it
needs to occupy stack space to pass the arguments to the callee. There
are two scenarios. One is to reserve the space in prologue and the other
is to reserve the space before the function calls. When we need to
reserve the stack space before function calls, the stack pointer is
adjusted. Under the scenario, we should not use stack pointer to access
the stack objects. It looks like,

callseq_start  ->  sp = sp - reserved_space
//
// We should not use SP to access stack objects in this area.
//
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision: https://reviews.llvm.org/D114245
The file was addedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
Commit 9a88566537177df75af1fcde69e0626fed2b1145 by kai.wang
[RISCV] Fix a bug in RISCVFrameLowering.

When we have out-going arguments passing through stack and we do not
reserve the stack space in the prologue. Use BP to access stack objects
after adjusting the stack pointer before function calls.

callseq_start  ->  sp = sp - reserved_space
//
// Use FP to access fixed stack objects.
// Use BP to access non-fixed stack objects.
//
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision: https://reviews.llvm.org/D114246
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
Commit a06d3527563503f17794bf119ee471d0ca2669ca by Vitaly Buka
[NFC][sanitizer] Track progress of populating the block

In multi-threaded application concurrent StackStore::Store may
finish in order different from assigned Id. So we can't assume
that after we switch writing the next block the previous is done.

The workaround is to count exact number of uptr stored into the block,
including skipped tail/head which were not able to fit entire trace.

Depends on D114490.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D114493
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stack_store.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stack_store_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stack_store.cpp
Commit b121d23a9cea711e832505c0b2495de6a51591c1 by craig.topper
[RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls.

Prevents crashes or cannot select errors.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D113822
The file was modifiedllvm/test/CodeGen/RISCV/half-intrinsics.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit f1d8345a2ab3c343929212d1c62174cfaa46e71a by carrot
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB

Currently we create register mappings for registers used only once in current
MBB. For registers with multiple uses, when all the uses are in the current MBB,
we can also create mappings for them similarly according to the last use.
For example

    %reg101 = ...
            = ... reg101
    %reg103 = ADD %reg101, %reg102

We can create mapping between %reg101 and %reg103.

Differential Revision: https://reviews.llvm.org/D113193
The file was modifiedllvm/test/CodeGen/X86/haddsub.ll
The file was modifiedllvm/test/CodeGen/X86/sat-add.ll
The file was modifiedllvm/test/CodeGen/X86/shift-combine.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/rem.ll
The file was modifiedllvm/test/CodeGen/X86/shl-crash-on-legalize.ll
The file was modifiedllvm/test/CodeGen/X86/bitreverse.ll
The file was modifiedllvm/test/CodeGen/ARM/ssat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
The file was modifiedllvm/test/CodeGen/ARM/usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
The file was modifiedllvm/test/CodeGen/X86/umul-with-overflow.ll
The file was modifiedllvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
The file was modifiedllvm/test/CodeGen/X86/vec_ctbits.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/combine-bitselect.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-03.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix.ll
The file was modifiedllvm/test/CodeGen/X86/vector-bitreverse.ll
The file was modifiedllvm/test/CodeGen/X86/vector-tzcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sdiv.ll
The file was modifiedllvm/test/CodeGen/X86/fpclamptosat.ll
The file was modifiedllvm/test/CodeGen/X86/nontemporal-loads.ll
The file was modifiedllvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
The file was modifiedllvm/test/CodeGen/X86/sse3-avx-addsub-2.ll
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
The file was modifiedllvm/test/CodeGen/X86/bypass-slow-division-32.ll
The file was modifiedllvm/test/CodeGen/X86/divide-by-constant.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-128.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-mul-08.ll
The file was modifiedllvm/test/CodeGen/X86/pmulh.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-128.ll
The file was modifiedllvm/test/CodeGen/X86/bmi2.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-01.ll
The file was modifiedllvm/test/CodeGen/X86/umul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-cmp-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/haddsub-3.ll
The file was modifiedllvm/test/CodeGen/X86/pull-binop-through-shift.ll
The file was modifiedllvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
The file was modifiedllvm/test/CodeGen/X86/ctpop-combine.ll
The file was modifiedllvm/test/CodeGen/X86/setcc-combine.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
The file was modifiedllvm/test/CodeGen/X86/slow-pmulld.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
The file was modifiedllvm/test/CodeGen/X86/vector-ext-logic.ll
The file was modifiedllvm/test/CodeGen/X86/popcnt.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
The file was modifiedllvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-128.ll
The file was modifiedllvm/test/CodeGen/ARM/fpclamptosat.ll
The file was modifiedllvm/test/CodeGen/X86/haddsub-shuf.ll
The file was modifiedllvm/test/CodeGen/X86/vector-lzcnt-128.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/umul_fix.ll
The file was modifiedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/vselect-packss.ll
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
The file was modifiedllvm/test/CodeGen/SystemZ/int-div-04.ll
The file was modifiedllvm/test/CodeGen/X86/vector-narrow-binop.ll
The file was modifiedllvm/test/CodeGen/X86/lzcnt-cmp.ll