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Summary

  1. Fixed misspelled builder name for e-mail notifications. (details)
Commit 388283cab6e6578f9e89d1ca122c24a922bbe280 by gkistanova
Fixed misspelled builder name for e-mail notifications.
The file was modifiedbuildbot/osuosl/master/config/status.py (diff)

Summary

  1. [CUDA][HIP] Support accessing static device variable in host code for -fgpu-rdc (details)
  2. [RISCV] Use a ComplexPattern for zexti32 to match sexti32. (details)
  3. [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. (details)
  4. Improve attribute documentation for nodebug on typedefs (details)
  5. [llvm] Check availability for os_signpost (details)
  6. update AMDGPU _Float16 support in clang doc (details)
  7. [test] Improve SanitizerCoverage tests on !associated and comdat (details)
  8. [lld-macho] add code signature for native arm64 macOS (details)
  9. [X86] Support amx-bf16 intrinsic. (details)
  10. [ThinLTO][NewPM] Clean up dead code under -O0 (details)
  11. [flang][fir][NFC] Move remaining types to TableGen type definition (details)
  12. [flang][fir][NFC] Remove dead code. (details)
Commit 47acdec1dd5d6d4c279727a97313c586c20e9c6f by Yaxun.Liu
[CUDA][HIP] Support accessing static device variable in host code for -fgpu-rdc

For -fgpu-rdc mode, static device vars in different TU's may have the same name.
To support accessing file-scope static device variables in host code, we need to give them
a distinct name and external linkage. This can be done by postfixing each static device variable with
a distinct CUID (Compilation Unit ID) hash.

Since the static device variables have different name across compilation units, now we let
them have external linkage so that they can be looked up by the runtime.

Reviewed by: Artem Belevich, and Jon Chesterfield

Differential Revision: https://reviews.llvm.org/D85223
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was addedclang/test/SemaCUDA/static-device-var.cu
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/test/CodeGenCUDA/device-var-linkage.cu
The file was addedclang/test/CodeGenCUDA/static-device-var-rdc.cu
The file was modifiedclang/test/CodeGenCUDA/managed-var.cu
Commit 9bde29629dfec420dbfbfe550073415452ae81f9 by craig.topper
[RISCV] Use a ComplexPattern for zexti32 to match sexti32.

We just started using a ComplexPattern for sexti32. This updates
zexti32 to match.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D97231
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
Commit efcdd598b766e764a7efb48b49e9ec8b0a590510 by craig.topper
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.

We always create the VL operand using a register, but if we can
determine that it came from an ADDI X0, imm with a sufficiently
small immediate, we can use VSETIVLI.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97332
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
Commit 7c926fee930012f9ec19cdaab23b7e154a3845ba by dblaikie
Improve attribute documentation for nodebug on typedefs

(followup to 8472fa6c54c9d044adcd147f6826bccebd730f30 )
The file was modifiedclang/include/clang/Basic/AttrDocs.td
Commit b03bb054e19c550ba895ec406e7b04cd1531407e by Jonas Devlieghere
[llvm] Check availability for os_signpost

Add availability checks to the os_signpost code so this can be used with
an older deployment target.

Differential revision: https://reviews.llvm.org/D97410
The file was modifiedllvm/lib/Support/Signposts.cpp
Commit 392fd3f1bf9f925942b385d8b99fb662d5739a83 by Yaxun.Liu
update AMDGPU _Float16 support in clang doc

Reviewed by: Matt Arsenault

Differential Revision: https://reviews.llvm.org/D97386
The file was modifiedclang/docs/LanguageExtensions.rst
Commit e9445765a5708a9097c253a5f783349ace2956ee by i
[test] Improve SanitizerCoverage tests on !associated and comdat
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/inline-bool-flag.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-comdat.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-nocomdat.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/interposable-symbol-nocomdat.ll
Commit 151990dd94e5087c94527553e9a91b64ae864a71 by gkm
[lld-macho] add code signature for native arm64 macOS

Differential Revision: https://reviews.llvm.org/D96164
The file was modifiedlld/MachO/SyntheticSections.h
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/OutputSegment.h
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/MachO.h
Commit 4bc7c8631ad62487a290dd4b7791848b67635787 by chen3.liu
[X86] Support amx-bf16 intrinsic.

Adding support for intrinsics of AMX-BF16.
This patch alse fix a bug that AMX-INT8 instructions will be selected with wrong
predicate.

Differential Revision: https://reviews.llvm.org/D97358
The file was modifiedclang/lib/Headers/amxintrin.h
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was modifiedllvm/lib/Target/X86/X86RegisterInfo.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsX86_64.def
The file was modifiedclang/test/CodeGen/X86/amx_api.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-tile-basic.ll
The file was modifiedllvm/lib/Target/X86/X86LowerAMXType.cpp
The file was modifiedllvm/lib/Target/X86/X86PreTileConfig.cpp
Commit a9b33ffb8f84f0f5b1c2253973ed04bc776bd710 by aeubanks
[ThinLTO][NewPM] Clean up dead code under -O0

We're running into undefined references using ThinLTO with -O0 on
Windows/Chrome. This fixes that.

This matches the legacy PM.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D97414
The file was modifiedllvm/test/Other/new-pm-O0-defaults.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 841f6995cd33b8891655b2aeb78deca548362c23 by clementval
[flang][fir][NFC] Move remaining types to TableGen type definition

Move the remaing of FIR types to TableGen type definition. This follow suggestion in D96422.

Reviewed By: schweitz, jeanPerier, rriddle

Differential Revision: https://reviews.llvm.org/D96987
The file was modifiedflang/lib/Optimizer/Dialect/FIRType.cpp
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRType.h
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRTypes.td
Commit 082ec3ab07760d1a6e47886246090c6f58708dbf by eschweitz
[flang][fir][NFC] Remove dead code.

This patch removes OpaqueAttr as it is no longer used.

Differential Revision: https://reviews.llvm.org/D97424
The file was modifiedflang/test/Fir/fir-ops.fir
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRAttr.h
The file was modifiedflang/lib/Optimizer/Dialect/FIRAttr.cpp
The file was modifiedflang/lib/Optimizer/Dialect/FIRDialect.cpp