SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Add missing closing quote to SVE 2 stage cmake options (details)
Commit 0b9e49366d6c3c39fabf7a20123cb37eac6297ca by david.spickett
Add missing closing quote to SVE 2 stage cmake options

Missing from 24c07902d058abcee3bcf908676bacaae1f3d448.
The file was modifiedbuildbot/osuosl/master/config/builders.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [Object] make SourceMgr available to MCContext during inline asm symbols (details)
  2. [Preprocessor] Implement -fminimize-whitespace. (details)
  3. [mlir] Added new RegionBranchTerminatorOpInterface and adapted uses of hasTrait<ReturnLike>. (details)
  4. [ORC][ORC-RT] Add initial Objective-C and Swift support to MachOPlatform. (details)
  5. [libc] fix LibcUnitTestMain when building with shared libraries (details)
  6. [mlir] Fix RankedTensorType::walkImmediateSubElements method (details)
  7. [libomptarget][nfc] Squash unused variable warning (details)
  8. [libomptarget] Build amdgpu plugin without hsa (details)
  9. Revert "Revert D106562 "[clangd] Get rid of arg adjusters in CommandMangler"" (details)
  10. [SelectionDAG] Support scalable-vector splats in yet more cases (details)
  11. [Analysis] Add simple cost model for strict (in-order) reductions (details)
  12. [AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc() (details)
  13. Revert "[clangd] Avoid range-loop init-list lifetime subtleties." (details)
  14. [X86][SSE] Don't scrub address math from interleaved shuffle tests (details)
  15. [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets (details)
  16. [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 (details)
  17. Fix test failures caused by 0aff1798b5721d5f95d16f465b99d357012bb8d1 (details)
  18. [SVE][AArch64] Improve code generation for vector_splice for Imm > 0 (details)
  19. [SVE] Add support for folding for select + masked loads (details)
  20. [VPlan] Use stored value from recipes for interleave groups. (details)
  21. [Inliner] Make the CallPenalty configurable (details)
  22. [NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties. (details)
  23. [SLP]Fix costs calculations. (details)
  24. [mlir] split type conversion to two lines for GCC's sake (details)
  25. [AArch65][SVE] Remove vector_splice from AddedComplexity pattern (details)
  26. Revert "[SLP]Fix costs calculations." (details)
  27. [SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths (details)
  28. [SimplifyCFG] Improve store speculation check (details)
  29. AArch64: support i128 (& larger) returns in GlobalISel (details)
  30. [ARM] Ensure correct regclass in distributing postinc (details)
  31. [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset (details)
  32. [AMDGPU] Pre-commit global-isel test case for D106451 (details)
  33. [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset (details)
  34. [llvm-readobj] Display multiple function names for stack size entries (details)
  35. [OpenCL] Change default standard version to CL1.2 (details)
  36. [SLP]Fix costs calculations. (details)
  37. [LV] Add test to store a first-order rec via interleave group. (details)
  38. [InstrRef][AArch64][1/4] Accept constant physreg variable locations (details)
  39. [Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation) (details)
  40. Simplify away some SmallVector copies. NFCI. (details)
  41. [IR] Consider non-willreturn as side effect (PR50511) (details)
  42. [libc++][ci] Detect not committed generated files. (details)
Commit 1558bb80c01b695ce12642527cbfccf16cf54ece by Yuanfang Chen
[Object] make SourceMgr available to MCContext during inline asm symbols
collection

Fixes PR51210.
The file was modifiedllvm/lib/Object/ModuleSymbolTable.cpp
Commit ae6b40000238e5faaaa319ffcfc713a15e459be8 by llvm-project
[Preprocessor] Implement -fminimize-whitespace.

This patch adds the -fminimize-whitespace with the following effects:

* If combined with -E, remove as much non-line-breaking whitespace as
   possible.

* If combined with -E -P, removes as much whitespace as possible,
   including line-breaks.

The motivation is to reduce the amount of insignificant changes in the
preprocessed output with source files where only whitespace has been
changed (add/remove comments, clang-format, etc.) which is in particular
useful with ccache.

A patch for ccache for using this flag has been proposed to ccache as well:
https://github.com/ccache/ccache/pull/815, which will use
-fnormalize-whitespace when clang-13 has been detected, and additionally
uses -P in "unify_mode". ccache already had a unify_mode in an older
version which was removed because of problems that using the
preprocessor itself does not have (such that the custom tokenizer did
not recognize C++11 raw strings).

This patch slightly reorganizes which part is responsible for adding
newlines that are required for semantics. It is now either
startNewLineIfNeeded() or MoveToLine() but never both; this avoids the
ShouldUpdateCurrentLine workaround and avoids redundant lines being
inserted in some cases. It also fixes a mandatory newline not inserted
after a _Pragma("...") that is expanded into a #pragma.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D104601
The file was modifiedclang/include/clang/Driver/Types.h
The file was modifiedclang/lib/Driver/Types.cpp
The file was modifiedclang/test/Preprocessor/stringize_space.c
The file was modifiedclang/test/Preprocessor/line-directive-output.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was addedclang/test/Preprocessor/minimize-whitespace.c
The file was modifiedclang/include/clang/Frontend/PreprocessorOutputOptions.h
The file was addedclang/test/Preprocessor/minimize-whitespace-messages.c
The file was modifiedclang/lib/Lex/Preprocessor.cpp
The file was modifiedclang/test/Preprocessor/print_line_include.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Preprocessor/comment_save.c
The file was modifiedclang/test/Preprocessor/macro_space.c
The file was modifiedclang/test/Preprocessor/hash_line.c
The file was modifiedclang/test/Preprocessor/first-line-indent.c
The file was addedclang/test/Preprocessor/line-directive-output-mincol.c
The file was modifiedclang/lib/Frontend/PrintPreprocessedOutput.cpp
The file was modifiedclang/docs/ClangCommandLineReference.rst
Commit 0425332015f479a89226c684c33659aa9cfff4b5 by marcel.koester
[mlir] Added new RegionBranchTerminatorOpInterface and adapted uses of hasTrait<ReturnLike>.

This CL adds a new RegionBranchTerminatorOpInterface to query information about operands that can be
passed to successor regions. Similar to the BranchOpInterface, it allows to freely define the
involved operands. However, in contrast to the BranchOpInterface, it expects an additional region
number to distinguish between various use cases which might require different operands passed to
different regions.

Moreover, we added new utility functions (namely getMutableRegionBranchSuccessorOperands and
getRegionBranchSuccessorOperands) to query (mutable) operand ranges for operations equiped with the
ReturnLike trait and/or implementing the newly added interface.  This simplifies reasoning about
terminators in the scope of the nested regions.

We also adjusted the SCF.ConditionOp to benefit from the newly added capabilities.

Differential Revision: https://reviews.llvm.org/D105018
The file was modifiedmlir/lib/Analysis/BufferViewFlowAnalysis.cpp
The file was modifiedmlir/lib/Transforms/BufferOptimizations.cpp
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.td
The file was modifiedmlir/lib/Interfaces/ControlFlowInterfaces.cpp
The file was modifiedmlir/lib/Analysis/DataFlowAnalysis.cpp
The file was modifiedmlir/test/Transforms/sccp-structured.mlir
The file was modifiedmlir/lib/Analysis/AliasAnalysis/LocalAliasAnalysis.cpp
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
The file was modifiedmlir/test/Dialect/SCF/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/SCF/SCFOps.td
The file was modifiedmlir/lib/Dialect/SCF/SCF.cpp
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.h
Commit cdcc35476833eca4f4996256e3ca0b21ecc26ad8 by Lang Hames
[ORC][ORC-RT] Add initial Objective-C and Swift support to MachOPlatform.

This allows ORC to execute code containing Objective-C and Swift classes and
methods (provided that the language runtime is loaded into the executor).
The file was modifiedllvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
The file was addedcompiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-objc-methods.S
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
The file was modifiedcompiler-rt/lib/orc/macho_platform.cpp
The file was modifiedcompiler-rt/lib/orc/macho_platform.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/Mangling.cpp
Commit 47afd43eaa9b6f713402aeca8c95f31d13ca5f3c by gchatelet
[libc] fix LibcUnitTestMain when building with shared libraries
The file was modifiedlibc/utils/UnitTest/CMakeLists.txt
Commit eb6c63cb0b6e6ead346f68e438f90ee0451906a3 by vlad.vinogradov
[mlir] Fix RankedTensorType::walkImmediateSubElements method

Add 'enconding' attribute visitor.
Without it ASM printer doesn't use attribute aliases for 'enconding'.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105554
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/test/IR/print-attr-type-aliases.mlir
Commit 93fe84d32fea8e1213bf7207b45e66667d3217f3 by jonathanchesterfield
[libomptarget][nfc] Squash unused variable warning

Suppress only current warning on openmp-clang-x86_64-linux-debian

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106777
The file was modifiedopenmp/libomptarget/src/device.cpp
Commit 2a613a77904467c77c4961cab60fcf6174a0856c by jonathanchesterfield
[libomptarget] Build amdgpu plugin without hsa

Default to building the amdgpu plugin to use dlopen when hsa is
not found instead of disabling it.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106600
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
Commit 0a3c7960cba15b57f679159c2bb4d20d10b86a5c by kadircet
Revert "Revert D106562 "[clangd] Get rid of arg adjusters in CommandMangler""

This reverts commit 2aa0cf19e7fe17c9eb5eb2555e10184061b933f1.
Get rid of reference to the temporary.
The file was modifiedclang-tools-extra/clangd/CompileCommands.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CompilerTests.cpp
The file was modifiedclang-tools-extra/clangd/CompileCommands.h
The file was modifiedclang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
The file was modifiedclang-tools-extra/clangd/Compiler.cpp
Commit f924a3d47492b7b586ccfd1333ca086a7e2d88b2 by fraser
[SelectionDAG] Support scalable-vector splats in yet more cases

This patch extends support for (scalable-vector) splats in the
DAGCombiner via the `ISD::matchBinaryPredicate` function, which enable a
variety of simple combines of constants.

Users of this function may now have to distinguish between
`BUILD_VECTOR` and `SPLAT_VECTOR` vector operands. The way of dealing
with this in-tree follows the approach added for
`ISD::matchUnaryPredicate` implemented in D94501.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106575
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/combine-splats.ll
Commit 0aff1798b5721d5f95d16f465b99d357012bb8d1 by david.sherwood
[Analysis] Add simple cost model for strict (in-order) reductions

I have added a new FastMathFlags parameter to getArithmeticReductionCost
to indicate what type of reduction we are performing:

  1. Tree-wise. This is the typical fast-math reduction that involves
  continually splitting a vector up into halves and adding each
  half together until we get a scalar result. This is the default
  behaviour for integers, whereas for floating point we only do this
  if reassociation is allowed.
  2. Ordered. This now allows us to estimate the cost of performing
  a strict vector reduction by treating it as a series of scalar
  operations in lane order. This is the case when FP reassociation
  is not permitted. For scalable vectors this is more difficult
  because at compile time we do not know how many lanes there are,
  and so we use the worst case maximum vscale value.

I have also fixed getTypeBasedIntrinsicInstrCost to pass in the
FastMathFlags, which meant fixing up some X86 tests where we always
assumed the vector.reduce.fadd/mul intrinsics were 'fast'.

New tests have been added here:

  Analysis/CostModel/AArch64/reduce-fadd.ll
  Analysis/CostModel/AArch64/sve-intrinsics.ll
  Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
  Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll

Differential Revision: https://reviews.llvm.org/D105432
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fadd.ll
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was addedllvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
Commit e6ff9179cee48096e7b2e739c9a79db62fa884bb by cullen.rhodes
[AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc()

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D106635
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/test/MC/AArch64/shift_extend_op_w_symbol.s
Commit e9274af7189333d1f50e47098d9ae30522d7193f by sam.mccall
Revert "[clangd] Avoid range-loop init-list lifetime subtleties."

This reverts commit 253b8145dedbe8d10792f44b4af7f52dbecd527f.

This doesn't actually fix anything - I should stop guessing.
See https://github.com/clangd/clangd/issues/800 for update
The file was modifiedclang-tools-extra/clangd/GlobalCompilationDatabase.cpp
Commit f64e251560203adf0258c96440c0cd637d3a43fc by llvm-dev
[X86][SSE] Don't scrub address math from interleaved shuffle tests
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit c8472db0a88701e8c1b183d6568028fefc3406c0 by llvm-dev
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets

Splatting the lower xmm with vinsertf128 is at least as quick as vperm2f128, and a lot faster on some AMD targets.

First step towards PR50053
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/test/CodeGen/X86/var-permute-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit 73e4e9cd007a71fb7186933abdcae024fe65cea7 by caroline.concatto
[AArch64][SVE] Improve code generation for vector_splice for Imm == -1

This patch implements vector_splice in tablegen for:
  a) when the immediate is equal to -1 (Imm==1) and uses:
       INSR  +  LASTB
For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, -1)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <D, E, F, G>
    LAST   RegLast, Vector_1                 // RegLast = D
    INSR   Res, (Vector_1 >> 1), RegLast     // Res = D + E, F, G

Differential Revision: https://reviews.llvm.org/D105633
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
Commit b2a5f0029f278dadb62f9e98dec12b1840020324 by david.sherwood
Fix test failures caused by 0aff1798b5721d5f95d16f465b99d357012bb8d1
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
Commit 0bfc26e3a4bf291f1d64610fe422c82789d752bc by caroline.concatto
[SVE][AArch64] Improve code generation for vector_splice for Imm > 0

This patch implements vector_splice in tablegen for all cases when the
Immediate is positive and lower than the known minimum value of
a scalable vector.
Vector_splice can be implemented using SVE instruction EXT.
For instance :
    @llvm.experimental.vector.splice(Vector_1, Vector_2, Imm)
    @llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <B, C, D, E>
        EXT  Vector_1, Vector_2, Imm              // Vector_1 = B, C, D + Vector_2 = E

Depends on D105633

Differential Revision: https://reviews.llvm.org/D106273
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
Commit 20b0fa91c9eebc7501e280049b61e8de352f3c94 by Dylan.Fleming
[SVE] Add support for folding for select + masked loads

Add folds to instcombine to support the removal of select instruction when the masked_load is guaranteed to zero the same lanes, i.e. select(mask, mload(,,mask,0), 0) -> mload(,,mask,0).

Patch originally authored by @paulwalker-arm

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106376
The file was addedllvm/test/Transforms/InstCombine/select-masked_load.ll
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
Commit d995d63767624a60a5d3276f9f16d7b995435af1 by flo
[VPlan] Use stored value from recipes for interleave groups.

Instead of getting the VPValue for the stored IR values through the
current plan, use the stored value of the recipes directly.

This way, the correct VPValues are used if the store recipes have been
modified in the VPlan and the IR value is not correct any longer. This
can happen, e.g. due to D105008.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 46c03668774c27877bd96957931fafae24383e3f by simon.cook
[Inliner] Make the CallPenalty configurable

Tests with multiple benchmarks, like Embench [1], showed that the
CallPenalty magic number has the most influence on inlining decisions
when optimizing for size.

On the other hand, there was no good default value for this parameter.
Some benchmarks profited strongly from a reduced call penalty. On
example is the picojpeg benchmark compiled for RISC-V, which got 6%
smaller with a CallPenalty of 10 instead of 12. Other benchmarks
increased in size, like matmult.

This commit makes the compromise of turning the magic number constant of
CallPenalty into a configurable value. This introduces the flag
`--inline-call-penalty`. With that flag users can fine tune the inliner
to their needs.

The CallPenalty constant was also used for loops. This commit replaces
the CallPenalty constant with a new LoopPenalty constant that is now
used instead.

This is a slimmed down version of https://reviews.llvm.org/D30899

[1]: https://github.com/embench/embench-iot

Differential Revision: https://reviews.llvm.org/D105976
The file was addedllvm/test/Transforms/Inline/inline-call-penalty-option.ll
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
The file was modifiedllvm/include/llvm/Analysis/InlineCost.h
Commit 8a8d01d58c14c65d6b1a40bf3335c72f6fcd1388 by paul.walker
[NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties.

Differential Revision: https://reviews.llvm.org/D106750
The file was modifiedllvm/unittests/Analysis/VectorFunctionABITest.cpp
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/unittests/Analysis/VectorUtilsTest.cpp
The file was modifiedllvm/lib/Analysis/VFABIDemangling.cpp
Commit a053afed49897aa34e08287f91c5255efa4e5131 by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit 539437e288f2395288a46a550c4c3070c4b16101 by tpopp
[mlir] split type conversion to two lines for GCC's sake
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
Commit bf28111ebdb760f46f168c867f7e8453c23814ed by caroline.concatto
[AArch65][SVE] Remove vector_splice from AddedComplexity pattern

The pattern for vector_splice with Index equal or bigger than
zero was misplaced in the AddedComplexity = 1 pattern in the AArch64
tablegen file. This patch fixes it by removing vector_splice pattern
from inside AddedComplexity = 1.
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit d7cb2a07967791867c245a6e2e8e4214d69140f7 by a.bataev
Revert "[SLP]Fix costs calculations."

This reverts commit a053afed49897aa34e08287f91c5255efa4e5131 to fix
buildbots.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
Commit e484e1ae03325823c469684d7d1532f2aadbe98d by kerry.mclaughlin
[SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths

Fixes more casts to `<FixedVectorType>` for the cases where the
instruction is a Insert/ExtractElementInst.

For fixed-width, this part of truncateToMinimalBitWidths is tested by
AArch64/type-shrinkage-insertelt.ll. I attempted to write a test case for this part
of truncateToMinimalBitWidths which uses scalable vectors, but was unable to add
one. The tests in type-shrinkage-insertelt.ll rely on scalarization to create extract
element instructions for instance, which is not possible for scalable vectors.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106163
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit ffb3277b0036909a8e622d5758a1e2850eabfd19 by nikita.ppv
[SimplifyCFG] Improve store speculation check

isSafeToSpeculateStore() looks for a preceding store to the same
location to make sure that introducing a new store of the same
value is safe. It currently bails on intervening mayHaveSideEffect()
instructions. However, I believe just checking mayWriteToMemory()
is sufficient there -- we just need to make sure that we know which
value was stored, we don't care if we can unwind in the meantime.

While looking into this, I started having some doubts about the
correctness of the transform with regard to thread safety. While
we don't try to hoist non-simple stores, I believe we also need
to make sure that the preceding store is simple as well. Otherwise
we could introduce a spurious non-atomic write after an atomic write
-- under our memory model this would result in a subsequent undef
atomic read, even if the second write stores the same value as the
first.

Example: https://alive2.llvm.org/ce/z/q_3YAL

Differential Revision: https://reviews.llvm.org/D106742
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-store.ll
Commit a487a49acc5a172909d706ffc43240ced1ac0693 by Tim Northover
AArch64: support i128 (& larger) returns in GlobalISel
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Commit 010f8e305705acb5128f409256e7f22ff3adc780 by david.green
[ARM] Ensure correct regclass in distributing postinc

The register class required for some MVE loads/stores is more
constrained than the register we use when creating postinc. Make sure we
constrain the register class to keep the code correct.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit 9ac10658aeda44d8a90ae372c1478610d143c8bb by jay.foad
[AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

Differential Revision: https://reviews.llvm.org/D106284
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
Commit 683b9ed0d593f249e992bed63768986b37b49dbb by jay.foad
[AMDGPU] Pre-commit global-isel test case for D106451

This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
Commit 59f6865231ff7d233e3728b21de2e5aa35189eb3 by jay.foad
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.

Differential Revision: https://reviews.llvm.org/D106451
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
Commit 87ed73fe6e01591998eed0dd769353f88919d056 by gbreynoo
[llvm-readobj] Display multiple function names for stack size entries

The current implementation of displaying .stack_size information
presumes that each entry represents a single function but this is not
always the case. For example with the use of ICF multiple functions can
be represented with the same code, meaning that the address found in a
.stack_size entry corresponds to multiple function symbols.
This change allows multiple function names to be displayed when
appropriate.

Differential Revision: https://reviews.llvm.org/D105884
The file was modifiedllvm/test/Object/BPF/yaml2obj-elf-bpf-rel.yaml
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 81600160b3f926746d02c52003d81180941fe9d0 by anastasia.stulova
[OpenCL] Change default standard version to CL1.2

Set default version for OpenCL C to 1.2. This means that the
absence of any standard flag will be equivalent to passing
'-cl-std=CL1.2'.

Note that this patch also fixes incorrect version check for
the pointer to pointer kernel arguments diagnostic and
atomic test.

Differential Revision: https://reviews.llvm.org/D106504
The file was modifiedclang/test/SemaOpenCL/func.cl
The file was modifiedclang/test/Preprocessor/predefined-macros.c
The file was modifiedclang/test/Parser/opencl-cl20.cl
The file was modifiedclang/test/Parser/opencl-storage-class.cl
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/CodeGenOpenCL/spir_version.cl
The file was modifiedclang/test/Parser/opencl-atomics-cl20.cl
The file was modifiedclang/test/SemaOpenCL/fp64-fp16-options.cl
Commit 6ca48efcf6e16adfcf33688d86de7bd2bb75a49a by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
Commit 93664503be6b3f47269cf617f8c46b6ce95f8076 by flo
[LV] Add test to store a first-order rec via interleave group.

This is a reduced version of the reproducer from
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/interleaved-store-of-first-order-recurrence.ll
Commit f86694cb808f22253e00742ccd279760ef0c688d by jeremy.morse
[InstrRef][AArch64][1/4] Accept constant physreg variable locations

Late in SelectionDAG we join up instruction numbers with their defining
instructions, if it couldn't be done during the main part of SelectionDAG.
One exception is function arguments, where we have to point a DBG_PHI
instruction at the incoming live register, as they don't have a defining
instruction. This patch adds another exception, for constant physregs, like
aarch64 has.

It may seem wasteful to use two instructions where we could use a single
DBG_VALUE, however the whole point of instruction referencing is to
decouple the identification of values from the specification of where
variable location ranges start.

(Part of my aarch64 work to ease adoption of  instruction referencing, as
in the meta comment on D104520)

Differential Revision: https://reviews.llvm.org/D104520
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
The file was addedllvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
Commit 4761321d49db01dce1e308f900add033cc26fb47 by gabor.marton
[Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation)

This change is an extension to D103967 where I added dump methods for
(dis)equality classes of the State. There, the (dis)equality classes and their
contents are dumped in an ordered fashion, they are ordered based on their
string representation. This is very useful once we start to use FileCheck to
test the State dump in certain tests.

Differential Revision: https://reviews.llvm.org/D106642
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 404f0d4f7cc7b7497c9725c6c6f20b21df8611bb by benny.kra
Simplify away some SmallVector copies. NFCI.

The lifetime of the initializer list is the full expression, so we can
skip storing it in a temporary vector.
The file was modifiedllvm/include/llvm/IR/Constants.h
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
Commit 33146857e9840a92840d48bbc3483e34ea545fc7 by nikita.ppv
[IR] Consider non-willreturn as side effect (PR50511)

This adjusts mayHaveSideEffect() to return true for !willReturn()
instructions. Just like other side-effects, non-willreturn calls
(aka "divergence") cannot be removed and cannot be reordered relative
to other side effects. This fixes a number of bugs where
non-willreturn calls are either incorrectly dropped or moved. In
particular, it also fixes the last open problem in
https://bugs.llvm.org/show_bug.cgi?id=50511.

I performed a cursory review of all current mayHaveSideEffect()
uses, which convinced me that these are indeed the desired default
semantics. Places that do not want to consider non-willreturn as a
sideeffect generally do not want mayHaveSideEffect() semantics at
all. I identified two such cases, which are addressed by D106591
and D106742. Finally, there is a use in SCEV for which we don't
really have an appropriate API right now -- what it wants is
basically "would this be considered forward progress". I've just
spelled out the previous semantics there.

Differential Revision: https://reviews.llvm.org/D106749
The file was modifiedllvm/lib/Analysis/DemandedBits.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/lib/Transforms/Scalar/ADCE.cpp
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
Commit 1139fd4270c7462a4bce8e1e91e6be174dcae88f by koraq
[libc++][ci] Detect not committed generated files.

The Generated output CI job only tests for modified files. This job
should also fail the generated output contains new files.

It would be possible to test modified and untracked files in one
execution of `git ls-files`. However the diff is stored as an artifact
so the execution of `git diff` would still be required.

Discussion: Would it be better to do `git ls-files -om` and remove the
excution of
`! grep -q '^--- a' ${BUILD_DIR}/generated_output.patch || false` ?
(Obviously then the name `generated_output.untracked` should change to
something like `generated_output.status`)

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D106534
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/run-buildbot