AbortedChanges

Summary

  1. [LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots (details)
Commit 2ba285961959af1928e9d9535c869f3334a2030e by omair.javaid
[LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots

We have started seeing some sporadic test failures on LLDB Arm/AArch64
Linux buildbots. This patch reduces no of parallel tests to 4 so
to provide some bandwidth for the timing critical and load dependent
test cases.
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. GlobalISel: Have lowerStore handle some unaligned stores (details)
  2. [DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes (details)
  3. [ADT] Remove set_is_strict_subset (NFC) (details)
  4. AMDGPU/GlobalISel: Check some remarks for failed legalizations (details)
  5. GlobalISel: Scalarize unaligned vector stores (details)
  6. [VPlan] Add interleave group printing test. (details)
  7. [ARM] Regenerate Thumb PR35481.ll test. NFC (details)
  8. [ARM] Switch order of creating VADDV and VMLAV. (details)
  9. Fixed syntax error that occured in the patch D104974 (details)
  10. [TTI] Make SK_ExtractSubvector matching length-changing only and simplify nested shuffle mask detection chain. (details)
  11. [InstCombine] canonicalize cmp-of-bitcast-of-vector-cmp to use zero constant (details)
  12. [SROA] prevent crash on large memset length (PR50910) (details)
  13. [RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC (details)
  14. [Analysis] improve function signature checking for snprintf (details)
  15. [mlir][sparse] add sparse tensor type conversion operation (details)
  16. [ConstantFold] Get rid of special cases for sizeof etc. (details)
  17. Fix a couple regression tests I missed updating in 2a284782 (details)
  18. Fix the default alignment of i1 vectors. (details)
  19. [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. (details)
  20. [RISCV][Docs] Add description about inline asm constraint for V. (details)
  21. [nfc] [lldb] Removed unused DWARFDebugInfo::GetDIEForDIEOffset (details)
  22. [GlobalOpt] support ConstantExpr use of global address for OptimizeGlobalAddressOfMalloc (details)
  23. [RISCV] Add some tests for SimplifyCFG's switch to lookup table transform (details)
  24. [ELF][test] Improve .symver & --version-script tests (details)
  25. [docs] Update outdated doxygen download link (details)
  26. [mlir] Add populateGpuToLLVMConversionPatterns function (details)
  27. [mlir] Change ABI breaking use of NDEBUG to LLVM_ENABLE_ABI_BREAKING_CHECKS (details)
  28. [Analysis] Remove unused declaration isGEPBaseAtNegativeOffset (NFC) (details)
  29. [InstCombine] Precommit tests for D106872 (NFC) (details)
  30. [lldb] Avoid moving ThreadPlanSP from plans vector (details)
  31. [clang-repl] Fix building with win32 dylibs (details)
  32. [LLD][MinGW] Accept joined format for --stack (details)
  33. [clang-tidy] Add new case type to check variables with Hungarian notation (details)
  34. [Preprocessor] Ensure newline after #pragma introduced by -fms-extensions. (details)
  35. [LLDB] Skip random failing tests on Arm/AArch64 Linux bots (details)
  36. Revert "Revert "[LLDB][GUI] Expand selected thread tree item by default"" (details)
  37. [LLDB] Change pexpect timeout to 30 to 60 (details)
  38. [X86] Support auto-detect for tigerlake and alderlake (details)
  39. [AMDGPU][GlobalISel] Add missing default mapping for BVH intrinsics (details)
  40. [examples] Fix incomplete_type on ZLinux when compiling RemoteJITUtils. (details)
  41. [docs]Update meeeting frequency to match new cal entry (details)
  42. [clangd] Fix the crash in getQualification (details)
  43. [GC][NFC] Make getGCStrategy by name available in IR (details)
  44. [ARM] Add trackLiveness to block-placement.mir. NFC (details)
  45. [mlir] Remove invalid DeallocOpLowering pattern insertion (details)
  46. Revert "[libcxx][CI] Work around Arm buildkite failures" (details)
  47. [mlir][linalg] Fix comments around ConstraintsSet (details)
  48. tsan: inline ProcessPendingSignals check (details)
  49. tsan: minor IgnoreSet refactoring (details)
  50. [clang-tidy] Always open files using UTF-8 encoding (details)
  51. [AArch64][AsmParser] NFC: Parser.Lex() -> Lex() (details)
  52. [OpenMPIRBuilder] Add a constructor to ReductionInfo to appease gcc5 (details)
  53. [ARM] Revert WLSTP to DLSTP if the target block is out of range (details)
  54. [flang][nfc] Fix variable names in `FrontendOptions` & `PreprocessorOptions` (details)
  55. [LoopFlatten] Fix missed LoopFlatten opportunity (details)
  56. Fix MSVC signed/unsigned comparison warning. NFCI. (details)
  57. [TTI] Add basic SK_InsertSubvector shuffle mask recognition (details)
  58. [hwasan] Detect use after scope within function. (details)
  59. [CostModel] Treat 'widen subvector' patterns as zero cost (details)
  60. GlobalISel: Fix infinite loop in legalization artifact combiner (details)
  61. [AMDGPU] Disable NSA for BVH instructions when appropriate (details)
  62. [CostModel][AArch64] Add some shuffle concat tests. NFC. (details)
  63. tsan: refactor MetaMap::GetAndLock interface (details)
  64. tsan: add LIKELY/UNLIKELY to MetaMap::GetSync (details)
  65. tsan: don't save creation stack for some sync objects (details)
  66. tsan: add new vector clock (details)
  67. [VectorCombine] Add PR30986 test case (details)
  68. [libc] Add a Google Benchmark target to support continuous monitoring of memory operation performance (details)
  69. tsan: remove unbalanced mutex unlock (details)
  70. [MLIR] FlatAffineConstraints: Fixed bug where some divisions were not being detected (details)
  71. [clang][NFC] Typo fixes. Test commit. (details)
  72. [AArch64] Optimise min/max lowering in ISel (details)
  73. [hwasan] Commit missed REQUIRES: stable-runtime. (details)
  74. [OpenCL] __cpp_threadsafe_static_init is by default undefined in OpenCL mode. (details)
  75. [ARM] Remove setPreservesCFG from ARMBlockPlacement (details)
  76. prfchwintrin.h: Make _m_prefetchw take a pointer to volatile (PR49124) (details)
  77. [VectorCombine] Fix PR30986 poison test case (details)
  78. Change code owner of libc++ from Marshall to Louis (details)
  79. [OpenMP][AMDGCN] Initial math headers support (details)
  80. [tsan] Complete renaming kMaxSid to kThreadSlotCount (details)
  81. [ADT] Remove PointerUnionTypeSelector (NFC) (details)
  82. [AArch64] Add shufflevector concat codegen tests. NFC. (details)
  83. [analyzer] Add control flow arrows to the analyzer's HTML reports (details)
  84. [analyzer] Highlight arrows for currently selected event (details)
  85. unwind: repair register restoration for OR1K (details)
  86. [flang] Fix IsSimplyContiguous() for the case of a pointer component (details)
  87. [WebAssembly] Compute known bits for SIMD bitmask intrinsics (details)
  88. Add script to bisect over files in an rsp file (details)
  89. [NFC][InstCombine] Add tests for xor reductions on i1 elt type (PR51259) (details)
  90. [InstCombine] `xor` reduction w/ i1 elt type is a parity check (details)
  91. [PatternRewriter] Disable copy/assign operators. (details)
  92. [VPlan] Use defined and ops VPValues to print VPInterleaveRecipe. (details)
  93. [WebAssembly] Add new pass to lower int/ptr conversions of reftypes (details)
  94. [DWARF] Don't process .debug_info relocations for DWO Context (details)
  95. [flang] Symbol representation for dummy SubprogramDetails (details)
  96. [unroll] Add clarifying comment (details)
  97. [AMDGPU][HIP] Switch default DWARF version to 5 (details)
  98. [gn build] (manually) port 5c2b48fdb0a6 (details)
  99. [lldb] Get rid of HAVE_SIGACTION (details)
  100. Revert "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" (details)
  101. [flang][nfc] Add a regression test for #50993 (details)
  102. Add Johannes to CODE_OWNERS for openmp offloading (details)
  103. [unrollruntime] Pull out a helper function for readability and eventual reuse [nfc] (details)
  104. [NFC][InstCombine] Add tests for mul reduction w/ i1 element type (PR51259) (details)
  105. [InstCombine] `vector_reduce_mul(?ext(<n x i1>))` --> `zext(vector_reduce_and(<n x i1>))` (PR51259) (details)
  106. [test] [lldb] Use filename instead of index in test (details)
  107. [DFAJumpThreading] Mark DT as preserved in LegacyPM (details)
  108. [DFAJumpThreading] Remove unnecessary includes (NFC) (details)
  109. [mlir] Async: clone constants into async.execute functions and parallel compute functions (details)
  110. [DFAJumpThreading] Use insert return value (NFC) (details)
  111. [libc] Add differential and performance targets for sqrtf (details)
  112. [DFAJumpThreading] Use SmallPtrSet for Visited (NFC) (details)
  113. [nfc] [lldb] Support moving support files instead of copy (details)
  114. [clang][darwin] Add support for the -mtargetos= option to the driver (details)
  115. [unroll] Move multiple exit costing into consumer pass [NFC] (details)
  116. [SLP][X86] Add fmuladd test coverage (details)
  117. [NFC][InstCombine] Add tests for umin reduction w/ i1 element type (PR51259) (details)
  118. [InstCombine] `vector_reduce_umin(?ext(<n x i1>))` --> `?ext(vector_reduce_and(<n x i1>))` (PR51259) (details)
  119. [NFC][InstCombine] Add tests for umax reduction w/ i1 element type (PR51259) (details)
  120. [InstCombine] `vector_reduce_umax(?ext(<n x i1>))` --> `?ext(vector_reduce_or(<n x i1>))` (PR51259) (details)
  121. [AArch64] Regenerate fp16 tests. (details)
  122. [ValueTracking] Fix computeConstantRange to use "may" instead of "always" semantics for llvm.assume (details)
  123. Revert "[unroll] Move multiple exit costing into consumer pass [NFC]" (details)
  124. [sanitizer] Fix __sanitizer_syscall_post_epoll_wait (details)
  125. [sanitizer] Add callbacks for epoll_pwait2 (details)
  126. [NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259) (details)
  127. [InstCombine] `vector_reduce_smin(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259) (details)
  128. [NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259) (details)
  129. [InstCombine] `vector_reduce_smax(?ext(<n x i1>))` --> `?ext(vector_reduce_{and,or}(<n x i1>))` (PR51259) (details)
  130. [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress (details)
  131. [NFC][InstCombine] Add tests for and reduction w/ i1 element type (PR51259) (details)
  132. [NFC][InstCombine] Add tests for or reduction w/ i1 element type (PR51259) (details)
  133. [InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259) (details)
  134. [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when advising against unrolling due to a call in a loop (details)
  135. Improve UBSan documentation (details)
  136. [mlir][sparse] use consistent type for COO object and sparse tensor storage (details)
  137. [profile] Move assertIsZero to InstrProfilingUtil.c (details)
  138. [clang] Add support for optional flag -fnew-infallible to restrict exception propagation (details)
  139. [AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types. (details)
  140. [GlobalOpt] Fix the assert for stored once non-pointer to global address (details)
  141. [NFC][tsan] clang-format two files (details)
  142. [llvm-profgen] Refactor PerfReader to allow different types of perf scripts (details)
  143. [mlir][SCF] Peel scf.for loops for even step divison (details)
  144. [mlir][affine] addLowerOrUpperBound: Disallow pos among boundOperands (details)
  145. [mlir][affine] addLowerOrUpperBound: Make map+operand composing optional (details)
  146. [RuntimeDyldChecker] Support offset in decode_operand expr (details)
  147. [RuntimeDyldChecker] Delete comparision of integers of different signs (details)
  148. [RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857). (details)
  149. [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need to be insert after it. (details)
  150. [Flang][Openmp] Upgrade TASKGROUP construct to 5.0. (details)
  151. [MILR][NFC] Silence clang-tidy warning in AffineOps.cpp (details)
  152. [NFC][sanitizer] Add static to internal functions (details)
  153. Reland: "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" (details)
  154. [hwasan] report failing thread for invalid free. (details)
  155. [LLD] [MinGW] Support both "--opt value" and "--opt=value" for more options (details)
  156. [clang] [MinGW] Let the last of -mconsole/-mwindows have effect (details)
  157. [AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends (details)
  158. [AArch64][AsmParser] NFC: Use helpers in matrix tile list parsing (details)
  159. [NFC] Rename enable-strict-reductions to force-ordered-reductions (details)
  160. tsan: new MemoryAccess interface (details)
  161. tsan: add AccessVptr (details)
  162. [llvm-readobj][XCOFF] Fix the error dumping for the first (details)
  163. tsan: avoid extra call indirection in unaligned access functions (details)
  164. [clang-format] don't break between function and function name in JS (details)
  165. [mlir] Fix delayed object interfaces registration (details)
  166. [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted (details)
  167. [MLIR] Add `getI8Type` to `OpBuilder` (details)
  168. [RISCV] Support simple fractional steps in matching VID sequences (details)
  169. [MLIR][OpenMP] Add support for critical construct (details)
  170. [clang] Make member var invalid when static initializer is invalid. (details)
Commit bc2cb91a20641f9685df1f3fb2ac4ea06756a252 by Matthew.Arsenault
GlobalISel: Have lowerStore handle some unaligned stores

This is NFC until some of the AMDGPU legalization rules are ripped
out.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 3a7c82efb8db57f0bf1cfbbd681b3905556bd049 by llvm-dev
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes

If all demanded elements of the BUILD_VECTOR pass a isGuaranteedNotToBeUndefOrPoison check, then we can treat this specific demanded use of the BUILD_VECTOR as guaranteed not to be undef or poison either.

Differential Revision: https://reviews.llvm.org/D107174
The file was modifiedllvm/test/CodeGen/X86/freeze-constant-fold.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/freeze-legalize.ll
Commit 5f5ce6e9a7eb0f735791662cd49efc2d934796fd by kazu
[ADT] Remove set_is_strict_subset (NFC)

The last use was removed on Mar 13, 2020 in commit
6b57d7f57d2cec7ec717757a6a52f2203d6e9db7.
The file was modifiedllvm/include/llvm/ADT/SetOperations.h
Commit 43c7cb9a3cf528a6e4e81acb6752b273c6e60300 by Matthew.Arsenault
AMDGPU/GlobalISel: Check some remarks for failed legalizations

The load/store tests are giant and have some cases that fail in them,
but it's hard to tell which ones are really failing. Check the remarks
to make it easier to track.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
Commit ebc17a0d68208a967fe8e13e1874874228dda622 by Matthew.Arsenault
GlobalISel: Scalarize unaligned vector stores

This has the same problems and limitations as the load path.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
Commit c726b627ad0ba29af9e46901f695b2f7fcc2a661 by flo
[VPlan] Add interleave group printing test.
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll
Commit 85d6045b88aee1d7d92eacec0099984911d7202d by david.green
[ARM] Regenerate Thumb PR35481.ll test. NFC
The file was modifiedllvm/test/CodeGen/Thumb/PR35481.ll
Commit 15a1d7e839229f3d9f5fd0a2e1255236a8f3565a by david.green
[ARM] Switch order of creating VADDV and VMLAV.

It can be beneficial to attempt to try the larger VMLAV patterns before
VADDV, in case both may match the same code.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
Commit ad28ff71647503c0a93f8b23a04844484f26f52b by pyadav2299
Fixed syntax error that occured in the patch D104974
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
Commit 66743d772682f4f09adf32b5503e3434233d6891 by llvm-dev
[TTI] Make SK_ExtractSubvector matching length-changing only and simplify nested shuffle mask detection chain.

Match style and don't use an else after a return.

Minor cleanup for an upcoming SK_InsertSubvector patch.
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Commit a22c99c3c187bf30717b191503dab5726d3476aa by spatel
[InstCombine] canonicalize cmp-of-bitcast-of-vector-cmp to use zero constant

We can invert a compare constant and preserve the logic
as shown in this sampling:
https://alive2.llvm.org/ce/z/YAXbfs
(In theory, we could deal with non-all-ones/zero as well,
but it doesn't seem worthwhile.)

I noticed this as a part of the x86 codegen difference in
https://llvm.org/PR51259 - it ends up using "test"
instead of "not + cmp" in that example.

This pattern also shows up in https://llvm.org/PR41312
and https://llvm.org/PR50798 .

Differential Revision: https://reviews.llvm.org/D107170
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/test/Transforms/InstCombine/icmp-vec.ll
Commit f2a322bfcfbc62b5523f32c4eded6faf2cad2e24 by spatel
[SROA] prevent crash on large memset length (PR50910)

I don't know much about this pass, but we need a stronger
check on the memset length arg to avoid an assert. The
current code was added with D59000.
The test is reduced from:
https://llvm.org/PR50910

Differential Revision: https://reviews.llvm.org/D106462
The file was modifiedllvm/test/Transforms/SROA/slice-width.ll
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
Commit 593059b328cf297d456e08dce8a2e1f8964df0c7 by craig.topper
[RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC

fcvt.w(u) supports multiple rounding modes, but the ISD node
doesn't encode that. So name it to match the rounding mode it uses.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
Commit 7f5555776513f174729a686ed01270e23462aaf7 by spatel
[Analysis] improve function signature checking for snprintf

The check for size_t parameter 1 was already here for snprintf_chk,
but it wasn't applied to regular snprintf. This could lead to
mismatching and eventually crashing as shown in:
https://llvm.org/PR50885
The file was modifiedllvm/lib/Analysis/TargetLibraryInfo.cpp
The file was modifiedllvm/test/Transforms/InstCombine/simplify-libcalls.ll
Commit 697ea09d47a93d92e40990a38fccf9e246cc22e6 by ajcbik
[mlir][sparse] add sparse tensor type conversion operation

Introduces a conversion from one (sparse) tensor type to another
(sparse) tensor type. See the operation doc for details. Actual
codegen for all cases is still TBD.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D107205
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/invalid.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir
Commit 2a2847823f0d13188c43ebdd0baf42a95df750c7 by efriedma
[ConstantFold] Get rid of special cases for sizeof etc.

Target-dependent constant folding will fold these down to simple
constants (or at least, expressions that don't involve a GEP).  We don't
need heroics to try to optimize the form of the expression before that
happens.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51232 .

Differential Revision: https://reviews.llvm.org/D107116
The file was modifiedllvm/lib/IR/ConstantFold.cpp
The file was modifiedclang/test/OpenMP/for_reduction_codegen.cpp
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.c
The file was modifiedllvm/test/tools/llvm-as/slow-ptrtoint.ll
The file was modifiedclang/test/CodeGenCXX/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_codegen.cpp
The file was modifiedllvm/test/Transforms/LowerTypeTests/function-disjoint.ll
The file was modifiedllvm/test/Other/constant-fold-gep.ll
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_codegen.cpp
Commit 6eb2ffbaeb56c8b08ad17c823e1699b964e10b8b by efriedma
Fix a couple regression tests I missed updating in 2a284782
The file was modifiedmlir/test/Target/LLVMIR/openacc-llvm.mlir
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
Commit bdd55b2f1810eb5a2474a36229d08a9e5ca870fc by efriedma
Fix the default alignment of i1 vectors.

Currently, the default alignment is much larger than the actual size of
the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway.  If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).

Differential Revision: https://reviews.llvm.org/D88994
The file was modifiedllvm/test/Transforms/InstCombine/icmp-vec.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
The file was modifiedllvm/test/CodeGen/X86/avx512-select.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-pair-mma.c
The file was modifiedllvm/test/CodeGen/X86/load-local-v3i129.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
The file was modifiedllvm/lib/IR/DataLayout.cpp
The file was modifiedllvm/test/CodeGen/NVPTX/f16x2-instructions.ll
The file was modifiedllvm/test/CodeGen/X86/vector-sext.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modifiedllvm/test/CodeGen/X86/pr41619.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedllvm/test/CodeGen/AArch64/spillfill-sve.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-min-max.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was modifiedllvm/test/Transforms/InstCombine/abs-intrinsic.ll
The file was modifiedllvm/test/Transforms/SROA/vector-promotion-different-size.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
The file was modifiedllvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lower-kernargs.ll
The file was modifiedllvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
The file was modifiedllvm/test/CodeGen/NVPTX/param-load-store.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 8b33839f010fe780fdaf68160be7c45d07fdfcad by kai.wang
[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision: https://reviews.llvm.org/D107139
The file was modifiedllvm/test/CodeGen/RISCV/rvv/inline-asm.ll
The file was modifiedclang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit ee3aef93b73646ef98f0241498d807a4fb68b78c by kai.wang
[RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision: https://reviews.llvm.org/D106633
The file was modifiedllvm/docs/LangRef.rst
Commit 6ef6616e07f5be69557e744fc28459d6051cfa9c by jan.kratochvil
[nfc] [lldb] Removed unused DWARFDebugInfo::GetDIEForDIEOffset

Its last use was removed by D63428.
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
Commit 732b05555c71cfdbf135a100a06472c5efc4eefb by scui
[GlobalOpt] support ConstantExpr use of global address for OptimizeGlobalAddressOfMalloc

I'm working on extending the OptimizeGlobalAddressOfMalloc to handle some more general cases. This is to add support of the ConstantExpr use of the global variables. The function allUsesOfLoadedValueWillTrapIfNull is now iterative with the added CE use of GV. Also, the recursive function valueIsOnlyUsedLocallyOrStoredToOneGlobal is changed to iterative using a worklist with the GEP case added.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D106589
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
The file was addedllvm/test/Transforms/GlobalOpt/new-promote.ll
The file was modifiedllvm/lib/Transforms/Utils/GlobalStatus.cpp
Commit 0da367145cb32f45a192e6f758a7474297730fc4 by craig.topper
[RISCV] Add some tests for SimplifyCFG's switch to lookup table transform

These are some of the basic cases taken from X86.

We currently fail to use lookup tables on many of these cases
because SimplifyCFG requires a legal type to do the transform and
RISCV only has one legal integer type.
The file was addedllvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
The file was addedllvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
Commit 52f35c9f148f3d4a9727d02d75ba41e570e683ca by i
[ELF][test] Improve .symver & --version-script tests

And delete redundant tests.
The file was addedlld/test/ELF/version-script-undef.s
The file was modifiedlld/test/ELF/partition-synthetic-sections.s
The file was modifiedlld/test/ELF/verneed.s
The file was removedlld/test/ELF/undef-version-script.s
The file was removedlld/test/ELF/version-script-twice.s
The file was removedlld/test/ELF/version-script-glob.s
The file was modifiedlld/test/ELF/version-script-symver.s
The file was modifiedlld/test/ELF/version-symbol-undef.s
The file was removedlld/test/ELF/version-script-locals.s
The file was removedlld/test/ELF/version-script-hide-so-symbol.s
Commit a5a5e73353696191c3754cab4fe5e7a585af3bf5 by noreply
[docs] Update outdated doxygen download link
The file was modifiedllvm/docs/README.txt
Commit 7d855605830f4a524f02b09d6891b351ff716782 by ivan.butygin
[mlir] Add populateGpuToLLVMConversionPatterns function

Differential Revision: https://reviews.llvm.org/D107218
The file was modifiedmlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
The file was modifiedmlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
Commit 97335ad13fd4f231a75163a1e5c232aed5efe921 by markus.boeck02
[mlir] Change ABI breaking use of NDEBUG to LLVM_ENABLE_ABI_BREAKING_CHECKS

The `DataLayout` class currently contains the member `layoutStack` which is hidden behind a preprocessor region dependant on the NDEBUG macro. Code wise this makes a lot of sense, as the `layoutStack` is used for extra assertions that users will want when compiling a debug build.
It however has the uncomfortable consequence of leading to a different ABI in Debug and Release builds. This I think is a bit annoying for downstream projects and others as they may want to build against a stable Release of MLIR in Release mode, but be able to debug their own project depending on MLIR.

This patch changes the related uses of NDEBUG to LLVM_ENABLE_ABI_BREAKING_CHECKS. As the macro is computed at configure time of LLVM, it may not change based on compiler settings of a downstream projects like NDEBUG would.

Differential Revision: https://reviews.llvm.org/D107227
The file was modifiedmlir/include/mlir/Interfaces/DataLayoutInterfaces.h
The file was modifiedmlir/lib/Interfaces/DataLayoutInterfaces.cpp
Commit ea155b995c98f821471516f9f6ae62c32c4d23b2 by kazu
[Analysis] Remove unused declaration isGEPBaseAtNegativeOffset (NFC)

The corresponding function definition was removed on Mar 3, 2021 in
commit ea7d208b780657c236986d7dfd7ba577583fd99a.
The file was modifiedllvm/include/llvm/Analysis/BasicAliasAnalysis.h
Commit 56e7b6c3924d7ba8db70c38235a77ed8208795eb by krishna17060
[InstCombine] Precommit tests for D106872 (NFC)
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll
Commit 41d0b20cc90f2aea25b4306f6c8f6c258ca3d377 by davelee.com
[lldb] Avoid moving ThreadPlanSP from plans vector

Change `ThreadPlanStack::PopPlan` and `::DiscardPlan` to not do the following:

1. Move the last plan, leaving a moved `ThreadPlanSP` in the plans vector
2. Operate on the last plan
3. Pop the last plan off the plans vector

This leaves a period of time where the last element in the plans vector has been moved. I am not sure what, if any, guarantees there are when doing this, but it seems like it would/could leave a null `ThreadPlanSP` in the container. There are asserts in place to prevent empty/null `ThreadPlanSP` instances from being pushed on to the stack, and so this could break that invariant during multithreaded access to the thread plan stack.

An open question is whether this use of `std::move` was the result of a measure performance problem.

Differential Revision: https://reviews.llvm.org/D106171
The file was modifiedlldb/include/lldb/Target/ThreadPlanCallUserExpression.h
The file was modifiedlldb/source/Target/ThreadPlanStack.cpp
The file was modifiedlldb/include/lldb/Target/ThreadPlanStepOverBreakpoint.h
The file was modifiedlldb/source/Target/ThreadPlan.cpp
The file was modifiedlldb/include/lldb/Target/ThreadPlan.h
The file was modifiedlldb/source/Target/ThreadPlanCallUserExpression.cpp
The file was modifiedlldb/source/Target/ThreadPlanStepOverBreakpoint.cpp
The file was modifiedlldb/source/Target/ThreadPlanCallFunction.cpp
The file was modifiedlldb/include/lldb/Target/ThreadPlanCallFunction.h
Commit 25a288b009f7d30b5392ea36c29570cbdcf238c3 by martin
[clang-repl] Fix building with win32 dylibs

Use `clang_target_link_libraries` to avoid duplicate libraries when
the same symbol is provided both by a static library and a larger
dylib, fixing linking with win32 dylibs. This fixes errors like
these:

    ld.lld: error: duplicate symbol: llvm::createStringError(std::__1::error_code, char const*)
    >>> defined at libLLVMSupport.a(Error.cpp.obj)
    >>> defined at libLLVM-14git.dll

This matches how other clang tools declare their dependencies.

Differential Revision: https://reviews.llvm.org/D107231
The file was modifiedclang/tools/clang-repl/CMakeLists.txt
Commit 05b025edf4aecf19634e01b0974126e53a927a50 by martin
[LLD][MinGW] Accept joined format for --stack

Postgresql uses `--stack=` in its Makefile.

Downstream issue: https://github.com/msys2/MINGW-packages/pull/9167

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D107237
The file was modifiedlld/test/MinGW/driver.test
The file was modifiedlld/MinGW/Options.td
Commit 2b9b5bc0409ff460849baf1fe4d7edda99c8db83 by minyihh
[clang-tidy] Add new case type to check variables with Hungarian notation

Add IdentifierNamingCheck::CaseType, CT_HungarianNotation, supporting
naming check with Hungarian notation.

Differential Revision: https://reviews.llvm.org/D86671
The file was addedclang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-hungarian-notation.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-hungarian-notation-cfgfile.cpp
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyCheck.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/readability-identifier-naming.rst
The file was modifiedclang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h
The file was modifiedclang-tools-extra/clang-tidy/ClangTidyCheck.h
The file was modifiedclang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
Commit 0e2586779ca6606a3df085f253a31b89b8ad8508 by llvm-project
[Preprocessor] Ensure newline after #pragma introduced by -fms-extensions.

The -fms-extensions converts __pragma (and _Pragma) into a #pragma that
has to occur at the beginning of a line and end with a newline. This
patch ensures that the newline after the #pragma is added even if
Token::isAtStartOfLine() indicated that we should not start a newline.

Committing relying post-commit review since the change is small, some
downstream uses might be blocked without this fix, and to make clear the
decision of the new -fminimize-whitespace feature (fix on main, revert
on clang-13.x branch) suggested by @aaron.ballman in D104601.

Differential Revision: https://reviews.llvm.org/D107183
The file was modifiedclang/lib/Frontend/PrintPreprocessedOutput.cpp
The file was addedclang/test/Preprocessor/whitespace-ms-extensions.c
Commit 8f30db8794125db2a768fbb3b20b0b1511ea211c by omair.javaid
[LLDB] Skip random failing tests on Arm/AArch64 Linux bots

Following tests have been failing randomly on LLDB Arm and AArch64 Linux
builtbots:

TestMultilineNavigation.py
TestMultilineCompletion.py
TestIOHandlerCompletion.py
TestGuiBasic.py

I have increased allocated CPU resources to these bots but it has not
improved situation to an acceptable level. This patch marks them as
skipped on Arm/AArch64 for now.
The file was modifiedlldb/test/API/commands/expression/multiline-navigation/TestMultilineNavigation.py
The file was modifiedlldb/test/API/iohandler/completion/TestIOHandlerCompletion.py
The file was modifiedlldb/test/API/commands/gui/basic/TestGuiBasic.py
The file was modifiedlldb/test/API/commands/expression/multiline-completion/TestMultilineCompletion.py
Commit a94fbb25de5fef6f20027f5ec9466fec821ba92f by omair.javaid
Revert "Revert "[LLDB][GUI] Expand selected thread tree item by default""

This reverts commit fd18f0e84cca023df6cb19e88c07c0e2059f659b.

I reverted this change to see its effect on failing GUI tests on LLDB
Arm/AArch64 Linux buildbots. I could not find any evidence against this
particular change so reverting it back.

Differential Revision: https://reviews.llvm.org/D100243
The file was addedlldb/test/API/commands/gui/expand-threads-tree/Makefile
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
The file was addedlldb/test/API/commands/gui/expand-threads-tree/TestGuiExpandThreadsTree.py
The file was addedlldb/test/API/commands/gui/expand-threads-tree/main.c
Commit 97c6ef4ea678ef9a69e1feaf9d77a0880bca09ba by omair.javaid
[LLDB] Change pexpect timeout to 30 to 60

Test dependent on pexpect fail randomly with timeouts on Arm/AArch64 Linux
buildbots. I am setting pexpect timeout from 30 to 60.

I will revert this back if this doesnt improve random failures.
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbpexpect.py
The file was modifiedlldb/third_party/Python/module/pexpect-4.6/pexpect/spawnbase.py
Commit d268c200701777085ef5d19e4a0637b87c7a02ac by freddy.ye
[X86] Support auto-detect for tigerlake and alderlake

Differential Revision: https://reviews.llvm.org/D107245
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedcompiler-rt/lib/builtins/cpu_model.c
Commit a441de6d94dc9e1dd3c36d33aa693c51ac2c8759 by carl.ritson
[AMDGPU][GlobalISel] Add missing default mapping for BVH intrinsics

Application of default mapping to BVH intrinsics was missing.
Copy parts of SelectionDAG test to GlobalISel test as these would
have indicated this error.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D107211
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 07a5b7e5b13d231725a2109c0768547d1924683b by Lang Hames
[examples] Fix incomplete_type on ZLinux when compiling RemoteJITUtils.

When compiling on ZLinux, we got this error:

/llvm-project/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/ \
RemoteJITUtils.h:80:65:   required from here...
/usr/include/c++/7/bits/unique_ptr.h:76:22: error: invalid application of
'sizeof' to incomplete type 'llvm::orc::RemoteExecutorProcessControl'
  static_assert(sizeof(_Tp)>0,

This patch just removes nullptr from the initialization of
std::unique_ptr<RemoteExecutorProcessControl> to avoid the issue.

Patch by Tung D. Le (tung@jp.ibm.com). Thanks Tung!

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D107247
The file was modifiedllvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.h
Commit bd19ba9d6db63587d1653d57be9f0e5ff2edcc38 by asbirlea
[docs]Update meeeting frequency to match new cal entry
The file was modifiedllvm/docs/GettingInvolved.rst
Commit e0f2d4af031c93b46f0920620ab6a798113b4b6e by kbobyrev
[clangd] Fix the crash in getQualification

Happens when DestContext is LinkageSpecDecl and hense CurContext happens to be
both not TagDecl and NamespaceDecl.

Minimal reproducer: trigger define outline in

```
namespace ns {
extern "C" {
typedef int foo;
}
foo Fo^o(int id) { return id; }
}
```

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D107047
The file was modifiedclang-tools-extra/clangd/unittests/ASTTests.cpp
The file was modifiedclang-tools-extra/clangd/AST.cpp
Commit c5b63714b520a2b271809d5f1257e5b3737b12ac by mkazantsev
[GC][NFC] Make getGCStrategy by name available in IR

We might want to use info from GC strategy in middle end analysis.
The motivation for this is provided in D99135: we may want to ask
a GC if it's going to work with a given pointer (currently this code
makes naive check by the method name).

Differetial Revision: https://reviews.llvm.org/D100559
Reviewed By: reames
The file was modifiedllvm/lib/IR/GCStrategy.cpp
The file was modifiedllvm/include/llvm/IR/GCStrategy.h
The file was modifiedllvm/lib/CodeGen/GCMetadata.cpp
Commit 85455192e18959b0d5bc20e99c21e13de9c5695e by david.green
[ARM] Add trackLiveness to block-placement.mir. NFC

Also move the test to mve-wls-block-placement.mir, to better fit what it
tests.
The file was removedllvm/test/CodeGen/Thumb2/block-placement.mir
The file was addedllvm/test/CodeGen/Thumb2/mve-wls-block-placement.mir
Commit 00a756d3f6e9266960718c2730a6aea61178f359 by ivan.butygin
[mlir] Remove invalid DeallocOpLowering pattern insertion

It is inserted later under then condition.

Differential Revision: https://reviews.llvm.org/D107238
The file was modifiedmlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
Commit e517a2405f39a174e65e4105106ae39704f88e4d by david.spickett
Revert "[libcxx][CI] Work around Arm buildkite failures"

This reverts commit f8bef4734845226c079900de3c273c8ab1915b49.

Buildkite agent 3.32.0 includes a fix for the PATH issue.
https://github.com/buildkite/agent/releases/tag/v3.32.0

Differential Revision: https://reviews.llvm.org/D107172
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 192e111e760b442c366ba053fe0a696edc2ea35b by springerm
[mlir][linalg] Fix comments around ConstraintsSet

Differential Revision: https://reviews.llvm.org/D107018
The file was modifiedmlir/include/mlir/Dialect/Linalg/Analysis/ConstraintsSet.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
Commit 8a49e053caac1623b7f0d87b68d21fb6526cad43 by dvyukov
tsan: inline ProcessPendingSignals check

ProcessPendingSignals is called in all interceptors
and user atomic operations. Make the fast-path check
(no pending signals) inlinable.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107217
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
Commit 7c6cca4b6e75fb3feea5449325c9394ee87456c3 by dvyukov
tsan: minor IgnoreSet refactoring

1. Move kMaxSize declaration to private section.
2. Inline Reset, it's trivial and called semi-frequently.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107215
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_ignoreset.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_ignoreset.h
Commit 307b1fddd4d84b559b154ff7744ae68bf9c6f503 by weratt
[clang-tidy] Always open files using UTF-8 encoding

The encoding used for opening files depends on the OS and might be different
from UTF-8 (e.g. on Windows it can be CP-1252). The documentation files use
UTF-8 and might be incompatible with other encodings. For example, right now
`clang-tools-extra/docs/clang-tidy/checks/abseil-no-internal-dependencies.rst`
has non-ASCII quotes and running `add_new_check.py` fails on Windows, because
it tries to read the file with incompatible encoding.

Use `io.open` for compatibility with both Python 2 and Python 3.

Reviewed By: kbobyrev

Differential Revision: https://reviews.llvm.org/D106792
The file was modifiedclang-tools-extra/clang-tidy/rename_check.py
The file was modifiedclang-tools-extra/clang-tidy/add_new_check.py
Commit 7ed0120d84d2e143bce1b9bd5f426f0bc8d53102 by cullen.rhodes
[AArch64][AsmParser] NFC: Parser.Lex() -> Lex()

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D107146
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Commit 58cc5a4c9fe7580eeaa7dd856ca89aa73f3482c8 by zinenko
[OpenMPIRBuilder] Add a constructor to ReductionInfo to appease gcc5

Otherwise, it produces wrong code for brace initializers.
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
Commit 28293918409dd3a5aa1aefa3342e50e099814cab by david.green
[ARM] Revert WLSTP to DLSTP if the target block is out of range

If the block target for a WLSTP instruction is known to be out of range,
and cannot be fixed by the ARMBlockPlacementPass, we can relax it to a
DLSTP (and cmp/branch) to still allow the creation of tail predicated
loops. That is what this patch does, adding extra revert code to the
fallback path of ARMBlockPlacementPass.

Due to the code produced when reverting, this creates a DLSTP between a
Bcc and a Br. As a DLS isn't necessarily a terminator we need to split
the block to move the DLS/Br into.

Differential Revision: https://reviews.llvm.org/D104709
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-branch.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-wls-block-placement.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
The file was modifiedllvm/lib/Target/ARM/ARMBlockPlacement.cpp
Commit 23d4c4f3fb12e127a5f07a7082f33b02082bb3f5 by andrzej.warzynski
[flang][nfc] Fix variable names in `FrontendOptions` & `PreprocessorOptions`

As all member variables in `FrontendOptions` and `PreprocessorOptions`
are public, we should be naming them as `variable` rather than
`variable_` [1]. This patch fixes that.

Also, `FrontendOptions` & `PreprocessorOptions` are re-defined as a
structs rather than classes (all fields are meant to be public).

[1]
https://github.com/llvm/llvm-project/blob/main/flang/docs/C%2B%2Bstyle.md#naming

Differential Revision: https://reviews.llvm.org/D107062
The file was modifiedflang/include/flang/Frontend/CompilerInstance.h
The file was modifiedflang/include/flang/Frontend/PreprocessorOptions.h
The file was modifiedflang/lib/Frontend/FrontendActions.cpp
The file was modifiedflang/lib/Frontend/CompilerInstance.cpp
The file was modifiedflang/lib/Frontend/FrontendAction.cpp
The file was modifiedflang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedflang/unittests/Frontend/FrontendActionTest.cpp
The file was modifiedflang/docs/FlangDriver.md
The file was modifiedflang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
The file was modifiedflang/include/flang/Frontend/FrontendOptions.h
Commit f117ed542fd2c327924d7767268d75ce77559944 by rosie.sumpter
[LoopFlatten] Fix missed LoopFlatten opportunity

When the limit of the inner loop is a known integer, the InstCombine
pass now causes the transformation e.g. imcp ult i32 %inc, tripcount ->
icmp ult %j, tripcount-step (where %j is the inner loop induction
variable and %inc is add %j, step), which is now accounted for when
identifying the trip count of the loop. This is also an acceptable use
of %j (provided the step is 1) so is ignored as long as the compare
that it's used in is also the condition of the inner branch.

Differential Revision: https://reviews.llvm.org/D105802
The file was modifiedllvm/lib/Transforms/Scalar/LoopFlatten.cpp
The file was modifiedllvm/test/Transforms/LoopFlatten/loop-flatten.ll
The file was modifiedllvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
Commit 057905011660200466fe1ab25cca76717e382d0b by llvm-dev
Fix MSVC signed/unsigned comparison warning. NFCI.
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 7397dcb403c2214d76444b3f3b16bb4eeed42e58 by llvm-dev
[TTI] Add basic SK_InsertSubvector shuffle mask recognition

This patch adds an initial ShuffleVectorInst::isInsertSubvectorMask helper to recognize 2-op shuffles where the lowest elements of one of the sources are being inserted into the "in-place" other operand, this includes "concat_vectors" patterns as can be seen in the Arm shuffle cost changes. This also helped fix a x86 issue with irregular/length-changing SK_InsertSubvector costs - I'm hoping this will help with D107188

This doesn't currently attempt to work with 1-op shuffles that could either be a "widening" shuffle or a self-insertion.

The self-insertion case is tricky, but we currently always match this with the existing SK_PermuteSingleSrc logic.

The widening case will be addressed in a follow up patch that treats the cost as 0.

Masks with a high number of undef elts will still struggle to match optimal subvector widths - its currently bounded by minimum-width possible insertion, whilst some cases would benefit from wider (pow2?) subvectors.

Differential Revision: https://reviews.llvm.org/D107228
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/include/llvm/IR/Instructions.h
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was modifiedllvm/test/Analysis/CostModel/ARM/shuffle.ll
Commit 66b4aafa2ec73cc397d1844a4c782eabcfe9f2cf by fmayer
[hwasan] Detect use after scope within function.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105201
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-capture.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-nobug.cpp
The file was addedcompiler-rt/test/hwasan/TestCases/stack-uas.c
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-loop-removed.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-goto.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-inlined.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-temp.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-types.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-loop-bug.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-temp2.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-dtor-order.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-if.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-loop.cpp
The file was addedllvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
Commit 872a950033d3cacd8c489f8be68d7c25a11a8746 by llvm-dev
[CostModel] Treat 'widen subvector' patterns as zero cost

As discussed on D107228, widening a subvector by inserting the whole subvector into the bottom a larger undef vector should always be cheap enough that we can treat it as zero cost.

NOTE: If this proves to cause issues we have the option of introducing a "SK_WidenSubvector" shuffle kind enum that targets could override the zero cost, but that doesn't seem necessary atm.

Differential Revision: https://reviews.llvm.org/D107228
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Commit dc3fbe293f1a1c1068e2cd27151fb373798fdfb6 by petar.avramovic
GlobalISel: Fix infinite loop in legalization artifact combiner

ArtifactValueFinder keeps trying to combine g_unmerge_values in some cases.
Fix is to skip combine attempt for dead defs.

Differential Revision: https://reviews.llvm.org/D106879
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
Commit 675c9423736d4117e918f734c995dc3bb069c986 by carl.ritson
[AMDGPU] Disable NSA for BVH instructions when appropriate

Check maximum NSA size when selecting NSA or non-NSA BVH instructions.

Differential Revision: https://reviews.llvm.org/D103230
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
Commit 46a861af3d1c77f28b414e6d96890fc2d0cf8538 by sjoerd.meijer
[CostModel][AArch64] Add some shuffle concat tests. NFC.

Test ported over from test/Analysis/CostModel/ARM/shuffle.ll.
The file was modifiedllvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
Commit 9e3e97aa810acac7b8ecffa7d4a92f55966e5358 by dvyukov
tsan: refactor MetaMap::GetAndLock interface

Don't lock the sync object inside of MetaMap methods.
This has several advantages:
- the new interface does not confuse thread-safety analysis
   so we can remove a bunch of NO_THREAD_SAFETY_ANALYSIS attributes
- this allows use of scoped lock objects
- this allows more flexibility, e.g. locking some other mutex
   between searching and locking the sync object
Also prefix the methods with GetSync to be consistent with GetBlock method.
Also make interface wrappers inlinable, otherwise we either end up with
2 copies of the method, or with an additional call.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107256
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.h
The file was modifiedcompiler-rt/lib/tsan/tests/unit/tsan_sync_test.cpp
Commit 14c7507b9d5936074076eb19deecd163c1315f94 by dvyukov
tsan: add LIKELY/UNLIKELY to MetaMap::GetSync

MetaMap::GetSync shows up in profiles,
so add LIKELY/UNLIKELY annotations.

Depends on D107256.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107257
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.cpp
Commit 7bd81fe1831e909e762e2f1f5caaba154989d4a1 by dvyukov
tsan: don't save creation stack for some sync objects

Currently we save the creation stack for sync objects always.
But it's not needed to some sync objects, most notably atomics.
We simply don't use atomic creation stack anywhere.
Allow callers to control saving of the creation stack
and don't save it for atomics.

Depends on D107257.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107258
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
The file was modifiedcompiler-rt/lib/tsan/tests/unit/tsan_sync_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.cpp
Commit 5c2b48fdb0a6f8dd7fb3fc24bdd3c028a2e3a51a by dvyukov
tsan: add new vector clock

Add new fixed-size vector clock for the new tsan runtime.
For now it's unused.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107167
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_defs.h
The file was modifiedcompiler-rt/lib/tsan/tests/unit/CMakeLists.txt
The file was addedcompiler-rt/lib/tsan/rtl/tsan_vector_clock.h
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was addedcompiler-rt/lib/tsan/tests/unit/tsan_vector_clock_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was addedcompiler-rt/lib/tsan/rtl/tsan_vector_clock.cpp
Commit 7942e20fc8e68d5937b52d487a3ce9d1eb830772 by llvm-dev
[VectorCombine] Add PR30986 test case
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
Commit 59198d062f409387393ee3843b3c999b1dc9947e by gchatelet
[libc] Add a Google Benchmark target to support continuous monitoring of memory operation performance

The next step is to be able to benchmark several implementations at once and compare which one performs best on a particular machine.

Differential Revision: https://reviews.llvm.org/D107265
The file was modifiedlibc/benchmarks/CMakeLists.txt
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.cpp
The file was addedlibc/benchmarks/LibcMemoryGoogleBenchmarkMain.cpp
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.h
Commit 03372e72d30294fe67012cd5cc0f069ce25cce3e by dvyukov
tsan: remove unbalanced mutex unlock

The mutex is now unlocked by the scoped Lock object.

Differential Revision: https://reviews.llvm.org/D107266
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
Commit 7eeaa782c430dd47c7da04b79f2d3f87cde77b4e by arjunpitchanathan
[MLIR] FlatAffineConstraints: Fixed bug where some divisions were not being detected

This patch fixes a bug in the existing implementation of detectAsFloorDiv,
where floordivs with numerator with non-zero constant term and floordivs with
numerator only consisting of a constant term were not being detected.

Reviewed By: vinayaka-polymage

Differential Revision: https://reviews.llvm.org/D107214
The file was modifiedmlir/unittests/Analysis/AffineStructuresTest.cpp
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
Commit 9988ab3989a2e2e9cde3cc1ab4d7a44a87dee393 by Justas.Janickas
[clang][NFC] Typo fixes. Test commit.

Fixed spelling of word "whether"
The file was modifiedclang/lib/Sema/SemaChecking.cpp
Commit b01417d3c58d5438c8bdb0762da0e882f905ef7f by irina.dobrescu
[AArch64] Optimise min/max lowering in ISel

Differential Revision: https://reviews.llvm.org/D106561
The file was modifiedllvm/test/CodeGen/AArch64/min-max.ll
The file was modifiedllvm/test/CodeGen/AArch64/minmax.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AArch64/min-max.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit cd2387b56dc82e1df314a46e8b987db45defc189 by fmayer
[hwasan] Commit missed REQUIRES: stable-runtime.

Differential Revision: https://reviews.llvm.org/D107268
The file was modifiedcompiler-rt/test/hwasan/TestCases/use-after-scope-capture.cpp
Commit b13fc7311eabca27b3baea99b7be6edef0213406 by Justas.Janickas
[OpenCL] __cpp_threadsafe_static_init is by default undefined in OpenCL mode.

Definition of `__cpp_threadsafe_static_init` macro is controlled by
language option Opts.ThreadsafeStatics. This patch sets language
option to false by default in OpenCL mode, resulting in macro
`__cpp_threadsafe_static_init` being undefined. Default value can be
overridden using command line option -fthreadsafe-statics.

Change is supposed to address portability because not all OpenCL
vendors support thread safe implementation of static initialization.

Fixes llvm.org/PR48012

Differential Revision: https://reviews.llvm.org/D107163
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/threadsafe-statics.clcpp
Commit c423a586a7107becc7c81b144f38028a0ab57043 by david.green
[ARM] Remove setPreservesCFG from ARMBlockPlacement

As of 28293918409dd3a5a it no longer preserves the CFG, needing to
split blocks in order to add DLS instructions.
The file was modifiedllvm/lib/Target/ARM/ARMBlockPlacement.cpp
Commit 12dc13b73cf8c11da1bcc354c78bd6a9c92408e8 by hans
prfchwintrin.h: Make _m_prefetchw take a pointer to volatile (PR49124)

For some reason, Microsoft declares _m_prefetch to take a const void*,
but _m_prefetchw to take a /volatile/ const void*.

Do the same for compatibility.

Differential revision: https://reviews.llvm.org/D106790
The file was modifiedclang/lib/Headers/prfchwintrin.h
Commit f10d4cfc237bf778d659f645eaf5c4ecb094148b by llvm-dev
[VectorCombine] Fix PR30986 poison test case

Thanks @xbolva00!
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
Commit c4cd573b3247509da6d76222a87265f9efd6ad02 by marshall
Change code owner of libc++ from Marshall to Louis
The file was modifiedllvm/CODE_OWNERS.TXT
Commit 713a5d12cde58a5dff90cc3e2d1e67c2a78fe52f by Pushpinder.Singh
[OpenMP][AMDGCN] Initial math headers support

With this patch, OpenMP on AMDGCN will use the math functions
provided by ROCm ocml library. Linking device code to the ocml will be
done in the next patch.

Reviewed By: JonChesterfield, jdoerfert, scchan

Differential Revision: https://reviews.llvm.org/D104904
The file was modifiedclang/lib/Headers/openmp_wrappers/cmath
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Headers/openmp_wrappers/__clang_openmp_device_functions.h
The file was modifiedclang/test/Headers/openmp_device_math_isnan.cpp
The file was addedclang/test/Headers/amdgcn_openmp_device_math.c
The file was addedclang/test/Headers/Inputs/include/utility
The file was modifiedclang/lib/Headers/__clang_hip_cmath.h
The file was addedclang/test/Headers/Inputs/include/algorithm
The file was modifiedclang/test/Headers/Inputs/include/cstdlib
The file was modifiedclang/lib/Headers/__clang_hip_math.h
The file was modifiedclang/lib/Headers/openmp_wrappers/math.h
Commit 1f04d8ed2e1d0719998ad5071194cb055841afc8 by benny.kra
[tsan] Complete renaming kMaxSid to kThreadSlotCount

This was missing from 5c2b48fdb0a6
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_vector_clock.cpp
Commit d4a3ad70d51d6739984bd24b2ef83e5058abd7de by kazu
[ADT] Remove PointerUnionTypeSelector (NFC)

The last use was removed on May 17, 2019 in commit
9b92875bbdde7c1e01b9e739da66aa876022eadd.
The file was modifiedllvm/include/llvm/ADT/PointerUnion.h
Commit ea23f7fce5deb2b55406cb61a06b0394b0c8011f by sjoerd.meijer
[AArch64] Add shufflevector concat codegen tests. NFC.
The file was addedllvm/test/CodeGen/AArch64/concat-vector.ll
Commit 97bcafa28deb95ad32f83fe339d78454d899ca1b by vsavchenko
[analyzer] Add control flow arrows to the analyzer's HTML reports

This commit adds a very first version of this feature.
It is off by default and has to be turned on by checking the
corresponding box.  For this reason, HTML reports still keep
control notes (aka grey bubbles).

Further on, we plan on attaching arrows to events and having all arrows
not related to a currently selected event barely visible.  This will
help with reports where control flow goes back and forth (eg in loops).
Right now, it can get pretty crammed with all the arrows.

Differential Revision: https://reviews.llvm.org/D92639
The file was modifiedclang/lib/Rewrite/HTMLRewrite.cpp
The file was modifiedclang/include/clang/Analysis/PathDiagnostic.h
The file was modifiedclang/lib/StaticAnalyzer/Core/BugReporter.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
The file was addedclang/test/Analysis/html_diagnostics/control-arrows.cpp
Commit 9e02f58780ab8734e5d27a0138bd477d18ae64a1 by vsavchenko
[analyzer] Highlight arrows for currently selected event

In some cases, when the execution path of the diagnostic
goes back and forth, arrows can overlap and create a mess.
Dimming arrows that are not relevant at the moment, solves this issue.
They are still visible, but don't draw too much attention.

Differential Revision: https://reviews.llvm.org/D92928
The file was modifiedclang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
The file was modifiedclang/test/Analysis/html_diagnostics/control-arrows.cpp
The file was modifiedclang/lib/Rewrite/HTMLRewrite.cpp
Commit d6d0b6559e97a3d0b258814e870d3e19f3a7ffcc by Saleem Abdulrasool
unwind: repair register restoration for OR1K

Currently, OR1K architecture put the program counter at offset 0x128 of
the current `or1k_thread_state_t`. However, the PC is restored after
updating the thread pointer in `r3`, which causes the PC to be fetched
incorrectly.

This patch swaps the order of restoration of `r9` and `r3`, such that
the PC is restored to `r9` using the current thread state.

Patch by Oi Chee Cheung!

Reviewed By: whitequark, compnerd

Differential Revision: https://reviews.llvm.org/D107042
The file was modifiedlibunwind/src/UnwindRegistersRestore.S
Commit bab86463df0789c39888285494bf68c713f0c5f3 by pklausler
[flang] Fix IsSimplyContiguous() for the case of a pointer component

The result expression for the analysis of a Component is not (longer)
valid in the expression traversal framework used by IsSimplyContiguousHelper
now that it has a tri-state result.  Fix so that any result of
analyzing the component symbol is required to be true, not just
present.

Differential Revision: https://reviews.llvm.org/D106693
The file was modifiedflang/lib/Evaluate/check-expression.cpp
Commit 417e500668621e1275851ccf6e573a39482368b5 by tlively
[WebAssembly] Compute known bits for SIMD bitmask intrinsics

This optimizes out the mask when the result of a bitmask is interpreted as an i8
or i16 value. Resolves PR50507.

Differential Revision: https://reviews.llvm.org/D107103
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
The file was addedllvm/test/CodeGen/WebAssembly/simd-bitmask-mask.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Commit 8490a7d908a981761607b7a138c0b10506ef9756 by aeubanks
Add script to bisect over files in an rsp file

This is mostly intended to be used to find which file contains a miscompile.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D107184
The file was addedllvm/utils/rsp_bisect.py
The file was addedllvm/utils/rsp_bisect_test/test_script.py
The file was addedllvm/utils/rsp_bisect_test/test_script_inv.py
The file was addedllvm/utils/rsp_bisect_test/test.py
Commit f6c44cdd3773a74fe52127b78c494d07f909e74d by lebedev.ri
[NFC][InstCombine] Add tests for xor reductions on i1 elt type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
Commit 1e801439be26569c9ede6fd309a645b00adb656c by lebedev.ri
[InstCombine] `xor` reduction w/ i1 elt type is a parity check

For i1 element type, `xor` and `add` are interchangeable
(https://alive2.llvm.org/ce/z/e77hhQ), so we should treat it just like
an `add` reduction and consistently transform them both:
https://alive2.llvm.org/ce/z/MjCm5W (self)
https://alive2.llvm.org/ce/z/kgqF4M (skipped zext)
https://alive2.llvm.org/ce/z/pgy3HP (skipped sext)

Though, let's emit the IR that is similar to the one we produce for
`vector_reduce_add(<n x i1>)`.

See https://bugs.llvm.org/show_bug.cgi?id=51259
The file was modifiedllvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 07548b83247e5c266e209ac4cdc2ab7a3231155d by clattner
[PatternRewriter] Disable copy/assign operators.

We had a [bad bug](https://github.com/llvm/circt/commit/69655864ee38167016506e9dae2eb1eb43dc3ba5) over in CIRCT
caused by accidentally passing around PatternRewriter
by value.  There is no reason to support copy/assignment
of the pattern rewriter, so disable it.

Differential Revision: https://reviews.llvm.org/D107232
The file was modifiedmlir/include/mlir/IR/PatternMatch.h
Commit bb725c98037eb8ad2ca2033427103b3503d57b2f by flo
[VPlan] Use defined and ops VPValues to print VPInterleaveRecipe.

This patch updates VPInterleaveRecipe::print to print the actual defined
VPValues for load groups and the store VPValue operands for store
groups.

The IR references may become outdated while transforming the VPlan and
the defined and stored VPValues always are up-to-date.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D107223
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit ce1c59dea6d01e8ec3d4cb911438254283e4646c by pmatos
[WebAssembly] Add new pass to lower int/ptr conversions of reftypes

Add new pass LowerRefTypesIntPtrConv to generate trap
instruction for an inttoptr and ptrtoint of a reference type instead
of erroring, since calling these instructions on non-integral pointers
has been since allowed (see ac81cb7e6).

Differential Revision: https://reviews.llvm.org/D107102
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/WebAssembly/CMakeLists.txt
The file was modifiedllvm/lib/Target/WebAssembly/WebAssembly.h
The file was addedllvm/lib/Target/WebAssembly/WebAssemblyLowerRefTypesIntPtrConv.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-inttoptr.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-ptrtoint.ll
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Commit 5a865b0b1ee650bc4d9b96fea98a1daa8e5933b6 by ayermolo
[DWARF] Don't process .debug_info relocations for DWO Context

When we build with split dwarf in single mode the .o files that contain both "normal" debug sections and dwo sections, along with relocaiton sections for "normal" debug sections.
When we create DWARF context in DWARFObjInMemory we process relocations and store them in the map for .debug_info, etc section.
For DWO Context we also do it for non dwo dwarf sections. Which I believe is not necessary. This leads to a lot of memory being wasted. We observed 70GB extra memory being used.

I went with context sensitive approach, flag is passed in. I am not sure if it's always safe not to process relocations for regular debug sections if Obj contains .dwo sections.
If it is alternatvie might be just to scan, in constructor, sections and if there are .dwo sections not to process regular debug ones.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106624
The file was modifiedllvm/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was addedllvm/test/DebugInfo/X86/dwarfdump-rela-dwo.s
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
The file was modifiedllvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFContext.h
The file was modifiedllvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
Commit c4a65434d894ca6f8ba1dcf338824b369c67f01b by pklausler
[flang] Symbol representation for dummy SubprogramDetails

Dummy procedures can be defined as subprograms with explicit
interfaces, e.g.

  subroutine subr(dummy)
    interface
      subroutine dummy(x)
        real :: x
      end subroutine
    end interface
    ! ...
  end subroutine

but the symbol table had no means of marking such symbols as dummy
arguments, so predicates like IsDummy(dummy) would fail.  Add an
isDummy_ flag to SubprogramNameDetails, analogous to the corresponding
flag in EntityDetails, and set/test it as needed.

Differential Revision: https://reviews.llvm.org/D106697
The file was modifiedflang/lib/Semantics/check-declarations.cpp
The file was modifiedflang/lib/Evaluate/tools.cpp
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was modifiedflang/test/Semantics/call02.f90
The file was modifiedflang/lib/Evaluate/check-expression.cpp
The file was modifiedflang/lib/Semantics/symbol.cpp
The file was modifiedflang/include/flang/Semantics/symbol.h
Commit ebc4c4e3b060ebd92a45a590818515c4cecb279f by listmail
[unroll] Add clarifying comment

The option to not preserve LCSSA is in fact not tested at all in upstream.  I was tempted to just remove the code entirely, but realized I didn't need to for my actual goal.
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
Commit 635c5ba45baee5c6a8841fbac06f6868ddae5a6d by scott.linder
[AMDGPU][HIP] Switch default DWARF version to 5

Another attempt at changing this default, now that tooling has greater
support for DWARF 5.

Differential Revision: https://reviews.llvm.org/D107190
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.h
The file was modifiedclang/lib/Driver/ToolChains/HIP.h
The file was modifiedclang/test/Driver/amdgpu-toolchain.c
The file was modifiedclang/test/Driver/hip-toolchain-dwarf.hip
Commit 3555880f106d8075a38c71d34ce498b541740561 by thakis
[gn build] (manually) port 5c2b48fdb0a6
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/tsan/BUILD.gn
Commit 82dc463bb356200fd46b90d6d5a439c3c9b31c92 by thakis
[lldb] Get rid of HAVE_SIGACTION

The .cpp file uses SIGNAL_POLLING_UNSUPPORTED to guard the call
to sigaction, so use it in the .h file too. (LLVM also calls
sigaction without a guard on non-Windows.)

No behavior change.

Differential Revision: https://reviews.llvm.org/D107255
The file was modifiedlldb/include/lldb/Host/Config.h.cmake
The file was modifiedlldb/cmake/modules/LLDBGenerateConfig.cmake
The file was modifiedlldb/include/lldb/Host/MainLoop.h
Commit 245f2ee6471099b351812d2327886f7c3b6e2ed6 by pmatos
Revert "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes"

This reverts commit ce1c59dea6d01e8ec3d4cb911438254283e4646c.
The file was modifiedllvm/lib/Target/WebAssembly/WebAssembly.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/WebAssembly/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-inttoptr.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-ptrtoint.ll
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
The file was removedllvm/lib/Target/WebAssembly/WebAssemblyLowerRefTypesIntPtrConv.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Commit ad2e830fe2f791ef37faa2238caed0a73e0cc51d by andrzej.warzynski
[flang][nfc] Add a regression test for #50993

https://bugs.llvm.org/show_bug.cgi?id=50993 was effectively fixed in
https://reviews.llvm.org/D106727. This patch adds a regression
test specifically for the use case reported in 50993.

Differential Revision: https://reviews.llvm.org/D107260
The file was addedflang/test/Preprocessing/parse-preprocessed.F
Commit 0c3dafd9edeb4cf81a5b46cd9d245cc1ae8d0eaf by jonathanchesterfield
Add Johannes to CODE_OWNERS for openmp offloading

Agreed on llvm-dev in May 2021
The file was modifiedllvm/CODE_OWNERS.TXT
Commit 9016beaa243026de307079b42ab4a7e022c6b14c by listmail
[unrollruntime] Pull out a helper function for readability and eventual reuse [nfc]
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
Commit 8baea415706fba58d9e33e63d3b48262332f12dc by lebedev.ri
[NFC][InstCombine] Add tests for mul reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
Commit 469793efa7b518e3b5a5bd68ed5e39a9f9f4121f by lebedev.ri
[InstCombine] `vector_reduce_mul(?ext(<n x i1>))` --> `zext(vector_reduce_and(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/PDansB (self)
https://alive2.llvm.org/ce/z/55D-Xc (zext)
https://alive2.llvm.org/ce/z/LxG3-r (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit ea9706626ce3f83b8433849049cc3c64b6b7297c by jan.kratochvil
[test] [lldb] Use filename instead of index in test

In some environments this test could fail if start.S has its own DWARF
CompileUnit or similar are included before the DWARF CompileUnit for the
file.

This change makes the test independent of the index of the compile unit,
instead checking the filename.

Reviewed By: herhut, jankratochvil

Differential Revision: https://reviews.llvm.org/D107300
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/dwarf5-lazy-dwo.c
Commit e97524cba2825ed412cd57a95a82c12ab439e171 by nikita.ppv
[DFAJumpThreading] Mark DT as preserved in LegacyPM

It is marked as preserved in NewPM, but not LegacyPM.
The file was modifiedllvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
Commit 84602f98c6d2df38275d36fd0009406defe3b627 by nikita.ppv
[DFAJumpThreading] Remove unnecessary includes (NFC)

This file uses neither unordered_map nor unordered_set.
The file was modifiedllvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
Commit b537c5b4147b6966fda8d80ed291f6b1f3857b16 by ezhulenev
[mlir] Async: clone constants into async.execute functions and parallel compute functions

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D107007
The file was addedmlir/test/Dialect/Async/async-parallel-for-compute-fn.mlir
The file was modifiedmlir/lib/Dialect/Async/Transforms/PassDetail.h
The file was modifiedmlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir
The file was addedmlir/lib/Dialect/Async/Transforms/PassDetail.cpp
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
The file was modifiedmlir/lib/Dialect/Async/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
Commit 3f7aea1a376d2def716113874cd382010f63897f by nikita.ppv
[DFAJumpThreading] Use insert return value (NFC)

Rather than find + insert. Also use range based for loop.
The file was modifiedllvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
Commit 2ab18d57d77633b6071c639c223b178754b36b4d by hedingarcia
[libc] Add differential and performance targets for sqrtf

Comparing the runtime of the sqrt functions from LLVM libc with the system libc:
|function       |perf - LLVM libc          |perf - MSVCRT
|sqrtf - Windows|44.05 sec (44051715500 ns)| 417.84 sec (417843359900 ns) = 6.96 mins

|function       |perf - LLVM libc          |perf - glibc
|sqrtf - Linux  |30.48 sec (30479458632 ns)|43.72 sec (43716901527 ns)

By running the differential test:
|function       |diff
|sqrtf - Windows|0 differing results
|sqrtf - Linux  |0 differing results

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D107229
The file was modifiedlibc/test/src/math/differential_testing/CMakeLists.txt
The file was addedlibc/test/src/math/differential_testing/sqrtf_perf.cpp
The file was addedlibc/test/src/math/differential_testing/sqrtf_diff.cpp
Commit 380b8a603c6e8997819726b15a76b8f6c94aa21a by nikita.ppv
[DFAJumpThreading] Use SmallPtrSet for Visited (NFC)

This set is only used for contains checks, so there is no need to
use std::set.
The file was modifiedllvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
Commit 437e37dd553917ef890821d5045f898f065e4d47 by jan.kratochvil
[nfc] [lldb] Support moving support files instead of copy

Split from D100299.

Reviewed By: jankratochvil

Differential Revision: https://reviews.llvm.org/D107165
The file was modifiedlldb/source/Symbol/CompileUnit.cpp
The file was modifiedlldb/include/lldb/Symbol/CompileUnit.h
Commit f575f371822f6a07483b21701165492224a846bb by Alex Lorenz
[clang][darwin] Add support for the -mtargetos= option to the driver

The new -mtargetos= option is a replacement for the existing, OS-specific options
like -miphoneos-version-min=. This allows us to introduce support for new darwin OSes
easier as they won't require the use of a new option. The older options will be
deprecated and the use of the new option will be encouraged instead.

Differential Revision: https://reviews.llvm.org/D106316
The file was addedclang/test/Driver/mtargetos-darwin.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
Commit 76940577e4bf9c63a8a4ebd32b556bd7feb8cad3 by listmail
[unroll] Move multiple exit costing into consumer pass [NFC]

This aligns the multiple exit costing with all the other cost decisions.  Note that UnrollAndJam, which is the only other caller of the original home of this code, unconditionally bails out of multiple exit loops.
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
Commit 317d70ea91841dfe503fddfe94b4a03b829917c6 by llvm-dev
[SLP][X86] Add fmuladd test coverage
The file was addedllvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
Commit 7888cfe7ef4f6e584022fbb23128b8b621ea69e4 by lebedev.ri
[NFC][InstCombine] Add tests for umin reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
Commit 0c137980565701bae7565d0aca999d3fa711822e by lebedev.ri
[InstCombine] `vector_reduce_umin(?ext(<n x i1>))` --> `?ext(vector_reduce_and(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/XxUScW (self)
https://alive2.llvm.org/ce/z/3usTF- (zext)
https://alive2.llvm.org/ce/z/GVxwQz (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
Commit 9d179ee3313bf18858ecc8a6dfc6b0f680573cfd by lebedev.ri
[NFC][InstCombine] Add tests for umax reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
Commit b9b7162b8bdc97ba5b4219fe3447fadc48b4a107 by lebedev.ri
[InstCombine] `vector_reduce_umax(?ext(<n x i1>))` --> `?ext(vector_reduce_or(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/NbBaeT (self)
https://alive2.llvm.org/ce/z/iEaig4 (zext)
https://alive2.llvm.org/ce/z/meGb3y (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 739efad3f6e36282b7d3a4c76802424473249b41 by efriedma
[AArch64] Regenerate fp16 tests.
The file was modifiedllvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
Commit b58eda39eb1fcb7df942c8569d031a342fa1308d by nikita.ppv
[ValueTracking] Fix computeConstantRange to use "may" instead of "always" semantics for llvm.assume

ValueTracking should allow for value ranges that may satisfy
llvm.assume, instead of restricting the ranges only to values that
will always satisfy the condition.

Differential Revision: https://reviews.llvm.org/D107298
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit c7770574f9b1c7b8548bf0596ed2008aa5cc5ca4 by nikita.ppv
Revert "[unroll] Move multiple exit costing into consumer pass [NFC]"

This reverts commit 76940577e4bf9c63a8a4ebd32b556bd7feb8cad3.

This causes Transforms/LoopUnroll/ARM/multi-blocks.ll to fail.
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
Commit f6f724c02e8ac8b675e3eabeae6b910995eba41b by Vitaly Buka
[sanitizer] Fix __sanitizer_syscall_post_epoll_wait

Syscall return number of initialized events which
needs to be used for unposoning.

Differential Revision: https://reviews.llvm.org/D107207
The file was modifiedcompiler-rt/test/msan/Linux/syscalls.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
Commit ecc2c9ba4547b31e0b87b2086368fcb0a20532ac by Vitaly Buka
[sanitizer] Add callbacks for epoll_pwait2

Depends on D107207.

Differential Revision: https://reviews.llvm.org/D107209
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
The file was modifiedcompiler-rt/include/sanitizer/linux_syscall_hooks.h
The file was modifiedcompiler-rt/test/msan/Linux/syscalls.cpp
Commit 4551a4184700cce21d3e63b03ccedefab6dd205f by lebedev.ri
[NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
Commit f47b7b6d10c77cce77c9456f788bcc77b3a19ebb by lebedev.ri
[InstCombine] `vector_reduce_smin(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/noXtZ8 (self)
https://alive2.llvm.org/ce/z/JNrN6C (zext)
https://alive2.llvm.org/ce/z/58snuN (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit d7482a2bded334710816ea0fc9fbbb6ec09d673e by lebedev.ri
[NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
Commit 554fc9ad0a24f6689c61d080c9451edd2ddc90b1 by lebedev.ri
[InstCombine] `vector_reduce_smax(?ext(<n x i1>))` --> `?ext(vector_reduce_{and,or}(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/3oqir9 (self)
https://alive2.llvm.org/ce/z/6cuI5m (zext)
https://alive2.llvm.org/ce/z/4FL8rD (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit bd13c8e610cad6c60e2b35264bcff9a4e4934615 by Jessica Paquette
[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress

When a value is expected to be extended, we should emit an extended load rather
than a normal G_LOAD.

Add checklines to arm64-abi.ll which show that we now emit the correct loads.

For ease of comparison: https://godbolt.org/z/8WvY6EfdE

Differential Revision: https://reviews.llvm.org/D107313
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi.ll
Commit a22449336ed918ef5946d5f89c50df9404a2c062 by lebedev.ri
[NFC][InstCombine] Add tests for and reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
Commit cdb0dfdffaaf061ba1b4e5653e6179db152ed891 by lebedev.ri
[NFC][InstCombine] Add tests for or reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
Commit 4ba3326f17ddabc1f427508a927a987d812ac543 by lebedev.ri
[InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259)

This allows the expansion logic to actually trigger if the argument
was extended from i1 element type, like the rest of the reductions expect.

Alive2 agrees:
https://alive2.llvm.org/ce/z/wcfews (or zext)
https://alive2.llvm.org/ce/z/FCXNFx (or sext)
https://alive2.llvm.org/ce/z/f26zUY (and zext)
https://alive2.llvm.org/ce/z/jprViN (and sext)
The file was modifiedllvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
Commit 6f6e9a867f2ace8c8b99eb8008e17dd63116bcde by lebedev.ri
[BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when advising against unrolling due to a call in a loop

I'm not sure this is the best way to approach this,
but the situation is rather not very detectable unless we explicitly call it out when refusing to advise to unroll.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D107271
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/include/llvm/Transforms/Utils/UnrollLoop.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was addedllvm/test/Transforms/LoopUnroll/X86/call-remark.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
Commit 65e9d7efb090756e16bbb5ff929efbc795a8b0d4 by 31459023+hctim
Improve UBSan documentation

Add more checks, info on -fno-sanitize=..., and reference to 5/2021 UBSan Oracle blog.

Authored By: DianeMeirowitz
Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D106908
The file was modifiedclang/docs/UndefinedBehaviorSanitizer.rst
Commit 52c87e0437808ed7249aaf73f43eda77e3f91d4d by ajcbik
[mlir][sparse] use consistent type for COO object and sparse tensor storage

There was a slightly mismatch between the double COO and actual numerical
type in the final sparse tensor storage (due to external formats always
using double). This minor revision removes that inconsistency by using a
properly typed COO and casting during the "add" method instead. This also
prepares alternative ways of initializing the COO object.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D107310
The file was modifiedmlir/lib/ExecutionEngine/SparseUtils.cpp
Commit 3b0a9e7b392a916d961c5a8c09b570e4656267d5 by Vedant Kumar
[profile] Move assertIsZero to InstrProfilingUtil.c

... and rename it to 'warnIfNonZero' to better-reflect what it actually
does.

The goal is to minimize the amount of logic that's conditionally
compiled under '#if __APPLE__'.
The file was modifiedcompiler-rt/lib/profile/InstrProfilingUtil.h
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingUtil.c
Commit b40a2a533a9dfb8dd5afb1f3b7d277da1e19f235 by modimo
[clang] Add support for optional flag -fnew-infallible to restrict exception propagation

The declaration for the global new function in C++ is generated in the compiler front-end. When examining exception propagation, we found that this is the largest root throw site propagator requiring unwind code to be generated for callers up the stack. Allowing this to be handled immediately with termination stops upward propagation and leads to significantly less landing pads generated. This in turns leads to a performance and .text size win.

With `-fnew-infallible` this annotates the declaration with `throw()` and `__attribute__((returns_nonnull))`.  `throw()` allows the compiler to assume exceptions do not propagate out of new and eliminate it as a root throw site. Note that the definition of global new is user-replaceable so users should ensure that the one used follows these semantics.

Measuring internally, we're seeing at 0.5% CPU win in one of our large internal FB workload. Measuring on clang self-build (cd0a1226b50081e86eb75a89d01e8782423971a0) we get:

thinlto/

        "dwarfehprepare.NumCleanupLandingPadsRemaining": 153494,
        "dwarfehprepare.NumNoUnwind": 26309,
thinlto_newinfallible/

        "dwarfehprepare.NumCleanupLandingPadsRemaining": 143660,
        "dwarfehprepare.NumNoUnwind": 28744,

a 1-143660/153494 = 6.4% reduction in landing pads and a 28744/26309 = 9.3% increase in the number of nounwind functions.

Testing:
ninja check-all
new test case to make sure these attributes are added correctly to global new.

Reviewed By: urnathan

Differential Revision: https://reviews.llvm.org/D105225
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was addedclang/test/CodeGenCXX/new-infallible.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
Commit 1f62af63467e4834e1e386619b3eccab245489d4 by efriedma
[AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types.

This adds handling for two cases:

1. A scalable vector where the element type is promoted.
2. A scalable vector where the element count is odd (or more generally,
   not divisble by the element count of the part type).

(Some element types still don't work; for example, <vscale x 2 x i128>,
or <vscale x 2 x fp128>.)

Differential Revision: https://reviews.llvm.org/D105591
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
Commit 7ce98cf56e3ea9c8dd8d55f6f61b1bed9de4c70a by scui
[GlobalOpt] Fix the assert for stored once non-pointer to global address

This is to fix the assert @bjope reported due to the code change of https://reviews.llvm.org/D106589. The test case from @bjope is also included.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D107302
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
The file was addedllvm/test/Transforms/GlobalOpt/2021-08-02-CastStoreOnceP2I.ll
Commit 9205143f07009cc4801b979d4d467d6c3c02450b by Vitaly Buka
[NFC][tsan] clang-format two files
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
Commit 6da9241aabe12c07fb905e5b3d2e4e16ef7d4296 by wlei
[llvm-profgen] Refactor PerfReader to allow different types of perf scripts

In order to support different types of perf scripts, this change tried to refactor `PerfReader` by adding the base class `PerfReaderBase` and current HybridPerfReader is derived from it for CS profile generation. Common functions like, passMM2PEvents, extract_lbrs, extract_callstack, etc. can be reused.

Next step is to add LBR only reader(for non-CS profile) and aggregated perf scripts reader(do a pre-aggregation of scripts).

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D107014
The file was modifiedllvm/tools/llvm-profgen/llvm-profgen.cpp
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was modifiedllvm/tools/llvm-profgen/PerfReader.h
Commit 3a41ff4883fe8b9e34a4f30aa9eecaf2ecb2ef44 by springerm
[mlir][SCF] Peel scf.for loops for even step divison

Add ForLoopBoundSpecialization pass, which specializes scf.for loops into a "main loop" where `step` divides the iteration space evenly and into an scf.if that handles the last iteration.

This transformation is useful for vectorization and loop tiling. E.g., when vectorizing loads/stores, programs will spend most of their time in the main loop, in which only unmasked loads/stores are used. Only the in the last iteration (scf.if), slower masked loads/stores are used.

Subsequent commits will apply this transformation in the SparseDialect and in Linalg's loop tiling.

Differential Revision: https://reviews.llvm.org/D105804
The file was modifiedmlir/include/mlir/Dialect/SCF/Passes.h
The file was addedmlir/test/Dialect/SCF/for-loop-peeling.mlir
The file was modifiedmlir/include/mlir/Dialect/SCF/Transforms.h
The file was modifiedmlir/include/mlir/Dialect/SCF/Passes.td
The file was modifiedmlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit fef4708472b2924ee09f2b332d94fe3a99bd5717 by springerm
[mlir][affine] addLowerOrUpperBound: Disallow pos among boundOperands

Bounds such as `dim_{pos} <= c_1 * dim_x + ...` where `x == pos` are invalid. `addLowerOrUpperBound` previously added an incorrect inequality to the set. Such cases are now explicitly rejected.

Differential Revision: https://reviews.llvm.org/D107220
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
Commit 18d10fbe87b36cd922faeeb04d18078aea071c95 by springerm
[mlir][affine] addLowerOrUpperBound: Make map+operand composing optional

There are cases in which it is not desirable to fully compose the bound map with the operands when adding lower/upper bounds to a `FlatAffineConstraints`.

E.g., this is the case when bounds should be expressed in terms of the operands only (and not the operands' dependencies). This also makes `addLowerOrUpperBound` useable together with operands that are defined through semi-affine expressions.

Differential Revision: https://reviews.llvm.org/D107221
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was modifiedmlir/include/mlir/Analysis/AffineStructures.h
Commit f4e418ac1e02c516abb8cc5125e38073b159e56f by 932494295
[RuntimeDyldChecker] Support offset in decode_operand expr

In RISCV's relocations, some relocations are comprised of two relocation types. For example, R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I compose a PC relative relocation. In general the compiler will set a label in the position of R_RISCV_PCREL_HI20. So, to test the R_RISCV_PCREL_LO12_I relocation, we need decode instruction at position of the label points to R_RISCV_PCREL_HI20 plus 4 (the size of a riscv non-compress instruction).

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D105528
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modifiedllvm/test/ExecutionEngine/JITLink/RISCV/ELF_pc_indirect.s
Commit 0023caf952e5100637227753f071bf0877176771 by 932494295
[RuntimeDyldChecker] Delete comparision of integers of different signs
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
Commit ed804588341e933cfc7783eb8776a258ba1fb264 by powerman1st
[RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106865
The file was addedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Commit 7900ee0b61ae4f251d59832c424bd0b1d46194d5 by powerman1st
[RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need to be insert after it.

If a vsetvli instruction is not compatible with the next vector instruction,
and there is no other things that may update or use VL/VTYPE, we could merge
it with the next vsetvli instruction that should be insert for the vector
instruction.

This commit only merge VTYPE with the former vsetvli instruction which has
the same VL.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106857
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Commit 77ebfba68b9aa89e9ccbcdf8e285afa0661c8ca4 by Chirag.Khandelwal
[Flang][Openmp] Upgrade TASKGROUP construct to 5.0.

In OMP 5.0 specification clause-list with
* task_reduction
* allocate
were allowed on taskgroup construct.

Fix XFAIL - omp-taskloop01.f90.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D93373
The file was modifiedflang/lib/Semantics/resolve-directives.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_ast_print.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_ast_print.cpp
The file was modifiedflang/lib/Semantics/resolve-names.cpp
The file was addedflang/test/Semantics/omp-taskgroup01.f90
The file was modifiedclang/test/OpenMP/master_taskloop_simd_ast_print.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMP.td
Commit 3d63d1a390f8e7f04b6cea09f03dff5d34a3289b by uday
[MILR][NFC] Silence clang-tidy warning in AffineOps.cpp

Silence clang-tidy warning in AffineOps.cpp due to the inability to see
through the typeswitch. NFC.

Differential Revision: https://reviews.llvm.org/D106125
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
Commit 735da5f5ad74ad139d3287c897be2057203a6032 by Vitaly Buka
[NFC][sanitizer] Add static to internal functions
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit d3a0a65bf01dccadee38d726b6c4d9813c84a048 by pmatos
Reland: "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes"

Add new pass LowerRefTypesIntPtrConv to generate debugtrap
instruction for an inttoptr and ptrtoint of a reference type instead
of erroring, since calling these instructions on non-integral pointers
has been since allowed (see ac81cb7e6).

Differential Revision: https://reviews.llvm.org/D107102
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-inttoptr.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/externref-ptrtoint.ll
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
The file was addedllvm/lib/Target/WebAssembly/WebAssemblyLowerRefTypesIntPtrConv.cpp
The file was modifiedllvm/lib/Target/WebAssembly/CMakeLists.txt
The file was modifiedllvm/lib/Target/WebAssembly/WebAssembly.h
Commit 150395c2bcee8e9a4c876eada81515fc917ac3b6 by fmayer
[hwasan] report failing thread for invalid free.

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D107270
The file was modifiedcompiler-rt/lib/hwasan/hwasan_report.cpp
The file was modifiedcompiler-rt/test/hwasan/TestCases/double-free.c
Commit b7fb5b54a93099cf3d7ac64f4a95d9942bc2e6a7 by martin
[LLD] [MinGW] Support both "--opt value" and "--opt=value" for more options

This does the same fix as D107237 but for a couple more options,
converting all remaining cases of such options to accept both
forms, for consistency. This fixes building e.g. openldap, which
uses --image-base=<value>.

Differential Revision: https://reviews.llvm.org/D107253
The file was modifiedlld/test/MinGW/driver.test
The file was modifiedlld/MinGW/Options.td
Commit ce49fd024b43bd76b149f984b8f0d16e92b9bb06 by martin
[clang] [MinGW] Let the last of -mconsole/-mwindows have effect

Don't just check for the existence of one, but check which one was
specified last, if any.

This fixes https://llvm.org/PR51296.

Differential Revision: https://reviews.llvm.org/D107261
The file was modifiedclang/lib/Driver/ToolChains/MinGW.cpp
The file was modifiedclang/test/Driver/mingw.cpp
Commit 40202b13b23290a6e20900896838c2dbbfb281bd by jay.foad
[AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends

These instructions have an implicit use of vcc which counts towards the
constant bus limit. Pre gfx10 this means that the explicit operands
cannot be sgprs. Use the custom inserter hook to call legalizeOperands
to enforce that restriction.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51217

Differential Revision: https://reviews.llvm.org/D106868
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/uaddo.ll
Commit a02bbeeae7fcaa25c6bdb4c98e2ec8ab5e83cd6d by cullen.rhodes
[AArch64][AsmParser] NFC: Use helpers in matrix tile list parsing
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Commit 0156f91f3b0af0c2b3c14eecb6192dbb039fc2d2 by david.sherwood
[NFC] Rename enable-strict-reductions to force-ordered-reductions

I'm renaming the flag because a future patch will add a new
enableOrderedReductions() TTI interface and so the meaning of this
flag will change to be one of forcing the target to enable/disable
them. Also, since other places in LoopVectorize.cpp use the word
'Ordered' instead of 'strict' I changed the flag to match.

Differential Revision: https://reviews.llvm.org/D107264
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-vf1.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
Commit 831910c5c4941b7c58d4d50d9e20808c8e2c1c0b by dvyukov
tsan: new MemoryAccess interface

Currently we have MemoryAccess function that accepts
"bool kAccessIsWrite, bool kIsAtomic" and 4 wrappers:
MemoryRead/MemoryWrite/MemoryReadAtomic/MemoryWriteAtomic.

Such scheme with bool flags is not particularly scalable/extendable.
Because of that we did not have Read/Write wrappers for UnalignedMemoryAccess,
and "true, false" or "false, true" at call sites is not very readable.

Moreover, the new tsan runtime will introduce more flags
(e.g. move "freed" and "vptr access" to memory acccess flags).
We can't have 16 wrappers and each flag also takes whole
64-bit register for non-inlined calls.

Introduce AccessType enum that contains bit mask of
read/write, atomic/non-atomic, and later free/non-free,
vptr/non-vptr.
Such scheme is more scalable, more readble, more efficient
(don't consume multiple registers for these flags during calls)
and allows to cover unaligned and range variations of memory
access functions as well.

Also switch from size log to just size.
The new tsan runtime won't have the limitation of supporting
only 1/2/4/8 access sizes, so we don't need the logarithms.

Also add an inline thunk that converts the new interface to the old one.
For inlined calls it should not add any overhead because
all flags/size can be computed as compile time.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107276
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_external.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/tsan/go/tsan_go.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_fd.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
Commit 18c6ed2f0f293582570ad3f6419e10ff808ba98e by dvyukov
tsan: add AccessVptr

Add AccessVptr access type.
For now it's converted to the same thr->is_vptr_access,
but later it will be passed directly to ReportRace
and will enable efficient tail calling in MemoryAccess function
(currently __tsan_vptr_update/__tsan_vptr_read can't use
tail calls in MemoryAccess because of the trailing assignment
to thr->is_vptr_access).

Depends on D107276.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107282
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
Commit 69396896fb615067b04a3e0c220f93bc91a10eec by esme.yi
[llvm-readobj][XCOFF] Fix the error dumping for the first
item of StringTable.

Summary: For the string table in XCOFF, the first 4 bytes
contains the length of the string table, so we should
print the string entries from fifth bytes. This patch
also adds tests for llvm-readobj dumping the string
table.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D105522
The file was modifiedllvm/test/tools/yaml2obj/XCOFF/long-symbol-name.yaml
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.h
The file was modifiedllvm/tools/llvm-readobj/XCOFFDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp
The file was addedllvm/test/tools/llvm-readobj/XCOFF/string-table.yaml
The file was modifiedllvm/test/tools/yaml2obj/XCOFF/basic-doc64.yaml
The file was modifiedllvm/lib/Object/XCOFFObjectFile.cpp
Commit d77b476c1953bcb0a608b2d6a4f2dd9fe0b43967 by dvyukov
tsan: avoid extra call indirection in unaligned access functions

Currently unaligned access functions are defined in tsan_interface.cpp
and do a real call to MemoryAccess. This means we have a real call
and no read/write constant propagation.

Unaligned memory access can be quite hot for some programs
(observed on some compression algorithms with ~90% of unaligned accesses).

Move them to tsan_interface_inl.h to avoid the additional call
and enable constant propagation.
Also reorder the actual store and memory access handling for
__sanitizer_unaligned_store callbacks to enable tail calling
in MemoryAccess.

Depends on D107282.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107283
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface.cpp
Commit 4f4f2783056fd01182740251b2ce8a77b12684b3 by krasimir
[clang-format] don't break between function and function name in JS

The patch https://reviews.llvm.org/D105964 (https://github.com/llvm/llvm-project/commit/58494c856a15f5b0e886c7baf5d505ac6c05dfe5)
updated detection of function declaration names. It had the unfortunate
consequence that it started breaking between `function` and the function
name in some cases in JavaScript code.

This patch addresses this.

Reviewed By: MyDeveloperDay, owenpan

Differential Revision: https://reviews.llvm.org/D107267
The file was modifiedclang/unittests/Format/FormatTestJS.cpp
The file was modifiedclang/lib/Format/ContinuationIndenter.cpp
Commit 9b50844fd798b5a81afd4aeb44b053d622747a42 by vlad.vinogradov
[mlir] Fix delayed object interfaces registration

Store both interfaceID and objectID as key for interface registration callback.
Otherwise the implementation allows to register only one external model per one object in the single dialect.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D107274
The file was modifiedmlir/lib/IR/Dialect.cpp
The file was modifiedmlir/unittests/IR/InterfaceAttachmentTest.cpp
The file was modifiedmlir/include/mlir/IR/Dialect.h
Commit 0d8cd4e2d5d4abb804d40984522e0413c66a3cbd by Jason Molenda
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted

Add a comment when there is a shifted value,
    add x9, x0, #291, lsl #12 ; =1191936
but not when the immediate value is unshifted,
    subs x9, x0, #256 ; =256
when the comment adds nothing additional to the reader.

Differential Revision: https://reviews.llvm.org/D107196
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/AArch64/cgp-usubo.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-element.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec_uaddo.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/logical_shifted_reg.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-nvcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq.ll
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The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
The file was modifiedllvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll
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The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-copy.ll
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The file was modifiedllvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
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The file was modifiedllvm/test/CodeGen/AArch64/srem-lkk.ll
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The file was modifiedllvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
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The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_plus.ll
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The file was modifiedllvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s
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The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
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The file was modifiedllvm/test/CodeGen/AArch64/sdivpow2.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
The file was modifiedllvm/test/CodeGen/AArch64/signbit-shift.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-ld1r.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
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The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat.ll
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The file was modifiedllvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-thunk.ll
The file was modifiedllvm/test/CodeGen/AArch64/addsub.ll
The file was modifiedllvm/test/CodeGen/AArch64/ls64-inline-asm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/funnel-shift.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/sat-add.ll
The file was modifiedllvm/test/CodeGen/AArch64/signed-truncation-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-sdiv.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
The file was modifiedllvm/test/CodeGen/AArch64/align-down.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
The file was modifiedllvm/test/CodeGen/AArch64/neg-abs.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
The file was modifiedllvm/test/CodeGen/AArch64/shift-mod.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fp128.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/addsub-constant-folding.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-cbz.ll
The file was modifiedllvm/test/CodeGen/AArch64/vldn_shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-atomic-128.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch-nobase.ll
The file was modifiedllvm/test/CodeGen/AArch64/extract-bits.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
The file was modifiedllvm/test/CodeGen/AArch64/sub-of-not.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-memset-inline.ll
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
Commit f0008a4cf43588ff695c84dbfe3b1ae89640f85c by frgossen
[MLIR] Add `getI8Type` to `OpBuilder`

Differential Revision: https://reviews.llvm.org/D107332
The file was modifiedmlir/lib/IR/Builders.cpp
The file was modifiedmlir/include/mlir/IR/Builders.h
Commit cba6aab9715988b522c21b0e04a7d9b888a81394 by fraser
[RISCV] Support simple fractional steps in matching VID sequences

This patch extends the optimization of VID-sequence BUILD_VECTORs
introduced in D104921 to include simple fractional steps composed of a
separated integer numerator and denominator.

A notable limitation in this sequence detection is that only sequences
with steps N/1 or 1/D are found, meaning that the step between elements
and the frequency with which it changes is consistent across the whole
sequence. Fractional steps such as 2/3 won't be matched as those would
involve more complex tracking of state or some level of backtracking.

As is stands, however, this patch is sufficient to match common
interleave-type shuffle indices, for example matching `<0,0,1,1>` (or
commonly `<0,u,1,u>` or `<u,0,u,1>`) to an index sequence divided by 2.

While the optimization is relatively `undef`-tolerant, due to greedy
pattern-matching there even are some simple patterns which confuse the
sequence detection into identifying either a suboptimal sequence or no
sequence at all.

Currently only fractional-step sequences identified as having a
power-of-two denominator are actually lowered to RVV instructions. This
is to avoid introducing divisions into the generated code.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106533
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Commit 59989d68ba065b8dc1909d525dfd135d9e3c0206 by kiran.chandramohan
[MLIR][OpenMP] Add support for critical construct

This patch adds the critical construct to the OpenMP dialect. The
implementation models the definition in 2.17.1 of the OpenMP 5 standard.
A name and hint can be specified. The name is a global entity or has
external linkage, it is modelled as a FlatSymbolRefAttr. Hint is
modelled as an integer enum attribute.
Also lowering to LLVM IR using the OpenMP IRBuilder.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D107135
The file was modifiedmlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
The file was modifiedmlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
The file was modifiedmlir/test/Dialect/OpenMP/ops.mlir
The file was modifiedmlir/test/Target/LLVMIR/openmp-llvm.mlir
The file was modifiedmlir/test/Dialect/OpenMP/invalid.mlir
Commit 08128fe7059e20b3f97ae5abbdeff2e6f6c711ed by adamcz
[clang] Make member var invalid when static initializer is invalid.

Previously we would show an error, but keep the member, and also the
CXXRrecordDecl, valid. This could lead to crashes when attempting to
access the record layout or size.

Differential Revision: https://reviews.llvm.org/D105478
The file was addedclang/test/AST/ast-dump-undeduced-expr.cpp
The file was modifiedclang/test/SemaCXX/cxx11-crashes.cpp
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/test/SemaCXX/crash-auto-36064.cpp

Summary

  1. [LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots (details)
Commit 2ba285961959af1928e9d9535c869f3334a2030e by omair.javaid
[LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots

We have started seeing some sporadic test failures on LLDB Arm/AArch64
Linux buildbots. This patch reduces no of parallel tests to 4 so
to provide some bandwidth for the timing critical and load dependent
test cases.
The file was modifiedbuildbot/osuosl/master/config/builders.py