SuccessChanges

Summary

  1. [DOCS] Added example for G_EXTRACT and G_INSERT (details)
  2. [mlir] Use ReassociationIndices instead of affine maps in linalg.reshape. (details)
  3. [RISCV][VP] Lower VP ISD nodes to RVV instructions (details)
  4. [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR (details)
  5. [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR (details)
  6. [MLIR] Rename free function `verify` on OffsetSizeAndStrideOpInterface (details)
  7. [X86]Fix a crash trying to convert indices to proper type. (details)
  8. [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV (details)
  9. [AMDGPU] Autogenerate checks for a clustering test and add GFX10 (details)
  10. [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM (details)
  11. Revert "[Passes] Enable the relative lookup table converter pass on aarch64" (details)
  12. [X86][SSE] Move unpack(hop,hop) fold from foldShuffleOfHorizOp to combineTargetShuffle (details)
  13. Make dependency between certain analysis passes transitive (reapply) (details)
  14. [AArch64] Fix scalar imm variants of SIMD shift left instructions (details)
  15. [SystemZ][z/OS] Fix return values in AutoConversion functions (details)
Commit e4eec519370b7bf42f31d51f7730e5c91cb53d18 by shivam98.tkg
 [DOCS] Added example for G_EXTRACT and G_INSERT

Reviewed By: xgupta, gargaroff

Differential Revision: https://reviews.llvm.org/D101227
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
Commit 2865d114f953a0c05df2663f4569704c9fe35eb0 by pifon
[mlir] Use ReassociationIndices instead of affine maps in linalg.reshape.

Differential Revision: https://reviews.llvm.org/D101861
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-push-reshape.mlir
The file was modifiedmlir/test/Dialect/Linalg/llvm.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
Commit 6f17613bfb95583f96a35ed589b67f07c5b028ab by fraser
[RISCV][VP] Lower VP ISD nodes to RVV instructions

This patch supports all of the current set of VP integer binary
intrinsics by lowering them to to RVV instructions. It does so by using
the existing RISCVISD *_VL custom nodes as an intermediate layer. Both
scalable and fixed-length vectors are supported by using this method.

One notable change to the existing vector codegen strategy is that
scalable all-ones and all-zeros mask SPLAT_VECTORs are now lowered to
RISCVISD VMSET_VL and VMCLR_VL nodes to match their fixed-length
BUILD_VECTOR counterparts. This allows them to reuse the existing
"all-ones" VL patterns.

To reduce the size of the phabricator diff, some tests are intentionally
left out and will be added later if the patch is accepted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101826
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
Commit 3fbcf07a99eccc90b99afcd78d94bf31c01f7329 by fraser
[RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR

As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vand-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vor-vp.ll
Commit 491a3d135993d22589c1a154217fdb24510d35d1 by fraser
[RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR

As agreed in D101826, these are follow-up tests for the RISC-V VP
support. Tests for VP_ASHR were landed as part of D101826.
The file was addedllvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
Commit 62851ea7ea2ca59766daab878c5c68629734cb4d by uday
[MLIR] Rename free function `verify` on OffsetSizeAndStrideOpInterface

Using a free function verify(<Op>) is error prone. Rename it.

Differential Revision: https://reviews.llvm.org/D101886
The file was modifiedmlir/lib/Interfaces/ViewLikeInterface.cpp
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.h
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.td
Commit 13a51e017c09ce449ba2ec0024baf356d6dfcbad by a.bataev
[X86]Fix a crash trying to convert indices to proper type.

Need to perfortm a bitcast on IndicesVec rather than subvector extract
if the original size of the IndicesVec is the same as the size of the
  destination type.

Differential Revision: https://reviews.llvm.org/D101838
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/var-permute-128.ll
Commit 437468f31942433c55bd2ceefeaaa0e8924deb1b by fraser
[RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV

As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
The file was addedllvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
Commit f106fe5f23deb66092ab2a846a31d4c0931fa0a5 by jay.foad
[AMDGPU] Autogenerate checks for a clustering test and add GFX10
The file was modifiedllvm/test/CodeGen/AMDGPU/cluster_stores.ll
Commit 61a46375a25b817da8657378b3fbd707a5e54771 by fraser
[RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM

As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
The file was addedllvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
Commit 6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 by martin
Revert "[Passes] Enable the relative lookup table converter pass on aarch64"

This reverts commit 57b259a852a6383880f5d0875d848420bb3c2945.

The relative lookup table converter pass seems to cause problems
for chromium on Windows/ARM64, see https://crbug.com/1204788.
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit 85460a2f5b6309450b341d19d800a7d90786b941 by llvm-dev
[X86][SSE] Move unpack(hop,hop) fold from foldShuffleOfHorizOp to combineTargetShuffle

By moving this after more of the shuffle canonicalization we reduce the demanded vector elts, avoiding a few unnecessary copies/moves etc.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit 3ee826594a9ed4119dd1fdfdd3f5f9175991e688 by bjorn.a.pettersson
Make dependency between certain analysis passes transitive (reapply)

LazyBlockFrequenceInfoPass, LazyBranchProbabilityInfoPass and
LoopAccessLegacyAnalysis all cache pointers to their nestled required
analysis passes. One need to use addRequiredTransitive to describe
that the nestled passes can't be freed until those analysis passes
no longer are used themselves.

There is still a bit of a mess considering the getLazyBPIAnalysisUsage
and getLazyBFIAnalysisUsage functions. Those functions are used from
both Transform, CodeGen and Analysis passes. I figure it is OK to
use addRequiredTransitive also when being used from Transform and
CodeGen passes. On the other hand, I figure we must do it when
used from other Analysis passes. So using addRequiredTransitive should
be more correct here. An alternative solution would be to add a
bool option in those functions to let the user tell if it is a
analysis pass or not. Since those lazy passes will be obsolete when
new PM has conquered the world I figure we can leave it like this
right now.

Intention with the patch is to fix PR49950. It at least solves the
problem for the reproducer in PR49950. However, that reproducer
need five passes in a specific order, so there are lots of various
"solutions" that could avoid the crash without actually fixing the
root cause.

This is a reapply of commit 3655f0757f2b4b, that was reverted in
33ff3c20498ef5c2057 due to problems with assertions in the polly
lit tests. That problem is supposed to be solved by also adjusting
ScopPass to explicitly preserve LazyBlockFrequencyInfo and
LazyBranchProbabilityInfo (it already preserved
OptimizationRemarkEmitter which depends on those lazy passes).

Differential Revision: https://reviews.llvm.org/D100958
The file was modifiedllvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
The file was modifiedpolly/lib/Analysis/ScopPass.cpp
The file was addedllvm/test/Other/pr49950.ll
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was modifiedllvm/lib/Analysis/LazyBranchProbabilityInfo.cpp
Commit 1ee50b473168735752a2f80ae9b356cfa70a76d0 by andrew.savonichev
[AArch64] Fix scalar imm variants of SIMD shift left instructions

This issue was reported in PR50057: Cannot select:
t10: i64 = AArch64ISD::VSHL t2, Constant:i32<2>

Shift intrinsics (llvm.aarch64.neon.ushl.i64 and sshl) with a constant
shift operand are lowered into AArch64ISD::VSHL in tryCombineShiftImm.
VSHL has i64 and v1i64 patterns for a right shift, but only v1i64 for
a left shift.

This patch adds the missing i64 pattern for AArch64ISD::VSHL, and LIT
tests to cover scalar variants (i64 and v1i64) of all shift
intrinsics (only ushl and sshl cases fail without the patch, others
were just not covered).

Differential Revision: https://reviews.llvm.org/D101580
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vshift.ll
Commit 6a12875046fd8c3e9f67482803a9f0f7b39dcfa6 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix return values in AutoConversion functions

My previous patch https://reviews.llvm.org/rG1527a5e4b4834e65678f9c30f786a2f4c17932bf incorrectly set int return values instead of std::error_code. This patch correctly returns and std::error_code value.

Reviewed By: fanbo-meng, Jonathan.Crowther

Differential Revision: https://reviews.llvm.org/D101904
The file was modifiedllvm/lib/Support/AutoConvert.cpp