Changes

Summary

  1. [tests] Update Transforms/FunctionAttrs/nosync.ll (details)
  2. [mlir] Check generated IR of math_polynomial_approx.mlir (details)
  3. [flang] Provide access to constant character array data (details)
  4. [WebAssembly] Fix JS code mentions in LowerEmscriptenEHSjLj (details)
  5. [M68k][test] Initial migration of MC tests (details)
  6. [M68k][AsmParser] Support negative integer constants (details)
  7. [M68k][AsmParser] Fix invalid register name parsing logics (details)
  8. [dfsan] extend a test case to measure origin memory usage (details)
  9. [ARM] Simplification to ARMBlockPlacement Pass. (details)
  10. [AMDGPU] Revise handling of preexisting waitcnt (details)
  11. [InstCombine] Fully disable select to and/or i1 folding (details)
  12. [test] Delete redundant arm64-tls-relocs.s (details)
  13. [AArch64] Replace fixup_aarch64_tlsdesc_call with FirstLiteralRelocationKind + R_AARCH64_{,P32_}TLSDESC_CALL (details)
  14. [M68k][test][NFC] Scrubing some tests (details)
  15. [AMDGPU] Move insertion of function entry waitcnt later (details)
Commit 6adcdd26139c6afcc79073fe16e72e94394c607d by nhaehnle
[tests] Update Transforms/FunctionAttrs/nosync.ll

Commit generated by running update_test_checks.py, to reflect the fact
that we now add the `mustprogress` attribute.
The file was modifiedllvm/test/Transforms/FunctionAttrs/nosync.ll
Commit 3c952ab25fb8602d756d303ed498f890b922e0c6 by ezhulenev
[mlir] Check generated IR of math_polynomial_approx.mlir

Instead of just checking that we emit something.

Differential Revision: https://reviews.llvm.org/D101940
The file was modifiedmlir/test/Dialect/Math/polynomial-approximation.mlir
Commit 535cbe02a4543ca930e79c10b5d334580428e607 by pklausler
[flang] Provide access to constant character array data

Allow direct access to constant character array data (for creating a hash ID of a constant).

Differential Revision: https://reviews.llvm.org/D101208
The file was modifiedflang/include/flang/Evaluate/constant.h
Commit 7f06cae1c19da91013df2ece641ba7b4980f8c33 by aheejin
[WebAssembly] Fix JS code mentions in LowerEmscriptenEHSjLj

- Removes the mention of fastcomp, which is deprecated.
- Some functions in Emscripten have moved from JS glue code to
  compiler-rt/emscripten_setjmp.c and
  compiler-rt/emscripten_exception_builtins.c. This fixes comments about
  that.

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D101812
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit 34da083a8c6bb42def881c8959e04c1de1366d70 by minyihh
[M68k][test] Initial migration of MC tests

As the context depicted by bug 49865[1], we are migrating tests under
`test/CodeGen/M68k/Encoding`, which was originally used to test
instruction encoding using MIR file as input, into `test/MC/M68k`. We
are also adding test directives for AsmParser using the same set of
inputs.

Currently we are converting the original MIR test files into assembly
code as well as translating the original LIT "RUN" statement into one
that only uses built-in LLVM tools (i.e. Get rid of `extract-section`).

However, since AsmParser has not completely finished, many of these
original test cases fail. Thus, this patch only migrate test files
that are passed by the current implementation of AsmParser (and
MCCodeEmitter). The remaining tests (under test/CodeGen/M68k/Encoding)
will be ported alone with the patch that fixes the related issues.

[1]: https://bugs.llvm.org/show_bug.cgi?id=49865

Differential Revision: https://reviews.llvm.org/D101410
The file was addedllvm/test/MC/M68k/Relocations/data-abs.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Control/Classes/MxNOP.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRI.s
The file was addedllvm/test/MC/M68k/Control/Classes/MxNOP.s
The file was addedllvm/test/MC/M68k/Bits/Classes/MxBTST_RI.s
The file was addedllvm/test/MC/M68k/Relocations/data-gotpcrel.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Relocations/data-gotoff.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxDiMu.s
The file was addedllvm/test/MC/M68k/Bits/Classes/MxBTST_RR.s
The file was addedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRRF.s
The file was addedllvm/test/MC/M68k/Relocations/data-gotoff.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Relocations/data-abs.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxCMP_RR.s
The file was addedllvm/test/MC/M68k/ShiftRotate/Classes/MxSR_DD.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Data/Classes/MxMove_RI.mir
The file was addedllvm/test/MC/M68k/Relocations/data-pc-rel.s
The file was addedllvm/test/MC/M68k/Control/Classes/MxRTS.s
The file was addedllvm/test/MC/M68k/Arith/Classes/MxExt.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RR.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Relocations/data-pc-rel.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxCMP_RI.s
The file was removedllvm/test/CodeGen/M68k/Encoding/ShiftRotate/Classes/MxSR_DD.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_RR.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Control/Classes/MxJMP.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxNEG.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Control/Classes/MxRTS.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxNEG.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RI.mir
The file was addedllvm/test/MC/M68k/Relocations/text-plt.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxExt.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_EAd.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/ShiftRotate/Classes/MxSR_DI.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxDiMu.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Relocations/data-gotpcrel.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Relocations/text-plt.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRR_EAd.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_RI.mir
The file was addedllvm/test/MC/M68k/Control/Classes/MxJMP.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRRF.mir
The file was addedllvm/test/MC/M68k/Data/Classes/MxMove_RI.s
The file was addedllvm/test/MC/M68k/ShiftRotate/Classes/MxSR_DI.s
Commit abac6023bba555ee930762f08a01f33370308c68 by minyihh
[M68k][AsmParser] Support negative integer constants

Parsing negative integer constants as expressions.

Differential Revision: https://reviews.llvm.org/D101732
The file was addedllvm/test/MC/M68k/Data/Classes/MxMove_MI.s
The file was modifiedllvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_FMR.mir
The file was addedllvm/test/MC/M68k/Control/Classes/MxScc.s
The file was addedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_FMI.s
The file was addedllvm/test/MC/M68k/Data/Classes/MxLEA.s
The file was addedllvm/test/MC/M68k/Bits/Classes/MxBTST_MR.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Control/Classes/MxScc.mir
The file was addedllvm/test/MC/M68k/Bits/Classes/MxBTST_MI.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_FMI.mir
The file was addedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_FMR.s
The file was removedllvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_MR.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Data/Classes/MxMove_MI.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_MI.mir
The file was removedllvm/test/CodeGen/M68k/Encoding/Data/Classes/MxLEA.mir
Commit 5b3dd2a49035445dcfdb09fb7e890b79adf6ab6f by minyihh
[M68k][AsmParser] Fix invalid register name parsing logics

Adjust sanity check in register parsing function to allow register
name with more than 2 characters (e.g. ccr).

Differential Revision: https://reviews.llvm.org/D101733
The file was modifiedllvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
The file was removedllvm/test/CodeGen/M68k/Encoding/Data/Classes/MxMoveCCR.mir
The file was addedllvm/test/MC/M68k/Data/Classes/MxMoveCCR.s
Commit f3e3a1d79eee878bb2816ded1a007e71a4fca7e1 by jianzhouzh
 [dfsan] extend a test case to measure origin memory usage

This is to support D101204.

Reviewed By: gbalats

Differential Revision: https://reviews.llvm.org/D101877
The file was modifiedcompiler-rt/test/dfsan/release_shadow_space.c
Commit 9ba5238c28daf930df3dcb9bc90b5c8531ae1466 by malhar.jajoo
[ARM] Simplification to ARMBlockPlacement Pass.

It simplifies the logic by moving the predecessor  (preHeader or it's predecessor) above the target (or loopExit),
instead of moving the target to after the predecessor.

Since the loopExit is no longer being moved, directions of any branches within/to it are unaffected.

While the predecessor is being moved, the backwards movement simplifies some considerations,
and the only consideration now required is that a forward WLS to the predecessor should not become backwards.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D100094
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/lib/Target/ARM/ARMBlockPlacement.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/block-placement.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll
Commit f5199d7ae0edf47c41d7347aad18f893ad20f0b3 by Austin.Kerbow
[AMDGPU] Revise handling of preexisting waitcnt

Preexisting waitcnt may not update the scoreboard if the instruction
being examined needed to wait on fewer counters than what was encoded in
the old waitcnt instruction. Fixing this results in the elimination of
some redudnat waitcnt.

These changes also enable combining consecutive waitcnt into a single
S_WAITCNT or S_WAITCNT_VSCNT instruction.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D100281
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
The file was addedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit 8a156d1c2795189389fadbf33702384f522f2506 by aqjune
[InstCombine] Fully disable select to and/or i1 folding

This is a patch that disables the poison-unsafe select -> and/or i1 folding.

It has been blocking D72396 and also has been the source of a few miscompilations
described in llvm.org/pr49688 .
D99674 conditionally blocked this folding and successfully fixed the latter one.
The former one was still blocked, and this patch addresses it.

Note that a few test functions that has `_logical` suffix are now deoptimized.
These are created by @nikic to check the impact of disabling this optimization
by copying existing original functions and replacing and/or with select.

I can see that most of these are poison-unsafe; they can be revived by introducing
freeze instruction. I left comments at fcmp + select optimizations (or-fcmp.ll, and-fcmp.ll)
because I think they are good targets for freeze fix.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D101191
The file was modifiedllvm/test/Transforms/InstCombine/bit-checks.ll
The file was modifiedllvm/test/Transforms/InstCombine/dont-distribute-phi.ll
The file was modifiedllvm/test/Transforms/InstCombine/and.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
The file was modifiedllvm/test/Transforms/InstCombine/or-fcmp.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop.ll
The file was modifiedllvm/test/Transforms/PGOProfile/chr.ll
The file was modifiedllvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-and-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmp-min-max.ll
The file was modifiedllvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov-not.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-safe-impliedcond-transforms.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll
The file was modifiedllvm/test/Transforms/LoopSimplify/merge-exits.ll
The file was modifiedllvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
The file was modifiedllvm/test/Transforms/InstCombine/and2.ll
The file was modifiedllvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov.ll
The file was modifiedllvm/test/Transforms/InstCombine/signed-truncation-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/onehot_merge.ll
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
The file was modifiedllvm/test/Transforms/InstCombine/widenable-conditions.ll
The file was modifiedllvm/test/Transforms/InstCombine/demorgan.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-cmp-br.ll
The file was modifiedllvm/test/Transforms/InstCombine/zext-or-icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/umul-sign-check.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
The file was modifiedllvm/test/Transforms/InstCombine/logical-select.ll
The file was modifiedllvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov-not.ll
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
The file was modifiedllvm/test/Transforms/InstCombine/range-check.ll
The file was modifiedclang/test/CodeGenOpenCL/amdgpu-nullptr.cl
The file was modifiedllvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-bitext.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-fcmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
The file was modifiedllvm/test/Transforms/InstCombine/sign-test-and-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/prevent-cmp-merge.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-safe-transforms.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
The file was modifiedllvm/test/Transforms/InstCombine/assume.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-safe-bool-transforms.ll
Commit 5f395223200bbe32bc17c731b4063ac2b58e51d9 by i
[test] Delete redundant arm64-tls-relocs.s

It just replicates tls-relocs.s
The file was removedllvm/test/MC/AArch64/arm64-tls-relocs.s
Commit 1b11b5b01fd8887a9c471b10cd99f0a60f6b2e50 by i
[AArch64] Replace fixup_aarch64_tlsdesc_call with FirstLiteralRelocationKind + R_AARCH64_{,P32_}TLSDESC_CALL
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
The file was modifiedllvm/test/MC/AArch64/tls-relocs.s
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
Commit f6d7fc801b4a513a5d5e04762e0e4c71414ae5ef by minyihh
[M68k][test][NFC] Scrubing some tests

Remove unecessary labels and assembly directives. NFC.
The file was modifiedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_FMR.s
The file was modifiedllvm/test/MC/M68k/Control/Classes/MxScc.s
The file was modifiedllvm/test/MC/M68k/Data/Classes/MxLEA.s
The file was modifiedllvm/test/MC/M68k/Bits/Classes/MxBTST_MR.s
The file was modifiedllvm/test/MC/M68k/Arith/Classes/MxBiArOp_FMI.s
The file was modifiedllvm/test/MC/M68k/Data/Classes/MxMove_MI.s
The file was modifiedllvm/test/MC/M68k/Data/Classes/MxMoveCCR.s
The file was modifiedllvm/test/MC/M68k/Bits/Classes/MxBTST_MI.s
The file was modifiedllvm/test/MC/M68k/Arith/Classes/MxNEG.s
Commit 6617a5a5eaeec455a2c4e1df9589208bcd5e6678 by Austin.Kerbow
[AMDGPU] Move insertion of function entry waitcnt later

This allows tracking these as preexisting waitcnt.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D101380
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir