SuccessChanges

Summary

  1. [flang] Add tests for MIN for character arrays. NFC (details)
  2. [flang] Remove redundant reallocation (details)
  3. [AMDGPU] Serialize MFInfo::ScavengeFI (details)
  4. [gn build] Port 98e5ede60499 (details)
  5. [AsmParser][ARM] Make .thumb_func imply .thumb (details)
  6. [llvm][NFC] Remove deprecated TargetFrameLowering and InstrTypes alignment functions (details)
  7. [llvm][NFC] Remove remaining deprecated alignment functions from CodeGen (details)
  8. [llvm-dwarfdump] Help option output should be consistent with the command guide (details)
  9. [DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST (details)
  10. [NFC][X86][MCA] AMD Zen 3: add tests with eliminatible GPR moves (details)
  11. [X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle (details)
  12. [NFC][X86][MCA] AMD Zen 3: add tests with non-eliminatible MMX moves (details)
Commit 778487a221496e92795afab147c3a030c74ad356 by diana.picus
[flang] Add tests for MIN for character arrays. NFC

We used to test only scalar character types. This commit adds tests for
arrays with a few simple shapes.

Differential Revision: https://reviews.llvm.org/D101983
The file was modifiedflang/unittests/RuntimeGTest/CharacterTest.cpp
Commit 2ea36e94927ccbc1f8e915a4e5c932531e69f02d by diana.picus
[flang] Remove redundant reallocation

The MaxMinHelper used to implement MIN and MAX for character types would
reallocate the accumulator whenever the number of characters in it was
different from that in the other input. This is unnecessary if the
accumulator is already larger than the other input. This patch fixes the
issue and adds a unit test to make sure we don't reallocate if we don't
need to.

Differential Revision: https://reviews.llvm.org/D101984
The file was modifiedflang/unittests/RuntimeGTest/CharacterTest.cpp
The file was modifiedflang/runtime/character.cpp
Commit 98e5ede60499f255c2cd48b85dcda14af5b99c7d by sebastian.neubauer
[AMDGPU] Serialize MFInfo::ScavengeFI

Serialize ScavengeFI from SIMachineFunctionInfo into yaml.

ScavengeFI is not used outside of the PrologEpilogInserter,
so this shouldn't change anything.

Differential Revision: https://reviews.llvm.org/D101367
The file was addedllvm/lib/CodeGen/MIRYamlMapping.cpp
The file was addedllvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was addedllvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
The file was addedllvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
The file was addedllvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was addedllvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
The file was addedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
Commit 8894a4b5d70a2fee8c35e2e66597fec24bc15770 by llvmgnsyncbot
[gn build] Port 98e5ede60499
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit f87638338464e7ff9396e92e04e3f5702d479d39 by thatlemon
[AsmParser][ARM] Make .thumb_func imply .thumb

GNU as documentation states that a `.thumb_func` directive implies `.thumb`, teach the asm parser to switch mode whenever it's encountered. On the other hand the labeled form, exclusive to Apple's toolchain, doesn't switch mode at all.

Reviewed By: nickdesaulniers, peter.smith

Differential Revision: https://reviews.llvm.org/D101975
The file was modifiedlld/test/ELF/arm-ldrlit-err.s
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was addedllvm/test/MC/ARM/thumb_func-implies-thumb.s
Commit eb1b26ec1d1ac60b2207354fcd003cad40e12b76 by gchatelet
[llvm][NFC] Remove deprecated TargetFrameLowering and InstrTypes alignment functions

Differential Revision: https://reviews.llvm.org/D102056
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
Commit e805b7c2d63c1f8b74f228718a55536f54ddd1c0 by gchatelet
[llvm][NFC] Remove remaining deprecated alignment functions from CodeGen

Differential Revision: https://reviews.llvm.org/D102058
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
Commit f0762fc42f0f4ecf849bef42eed2bb4c0785ea67 by gbreynoo
[llvm-dwarfdump] Help option output should be consistent with the command guide

The dwarfdump command guide shows the short options used as aliases but
these are not found in the help text unless --show-hidden is used.
Investigating other tools some follow this pattern, others like
llvm-objdump show aliases with --help. This change fixes the help output
to be consistent with the command guide. This includes updating alias
descriptions in the help output to use "--".

As part of this change I updated cmdline.test, including some options
that were missing testing.

Differential Revision: https://reviews.llvm.org/D101646
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/test/tools/llvm-dwarfdump/cmdline.test
Commit 0791f968fee259e5c34523167bd58179b8b081c2 by stephen.tozer
[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST

This patch modifies updateDbgUsersToReg to properly handle
DBG_VALUE_LIST instructions, by replacing the hard-coded operand indices
(i.e. getOperand(0)) with the more general getDebugOperandsForReg(), and
updating the register for all matching operands.

Differential Revision: https://reviews.llvm.org/D101523
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was addedllvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
Commit 227678089cf6d8b15d51e58abfefd4f346e9c7f0 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests with eliminatible GPR moves
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
Commit 7059b28d5d276cab89815b762d10431329a7da2a by lebedev.ri
[X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

Refs:
AMD SOG 19h, 2.9.4 Zero Cycle Move
The processor is able to execute certain register to register
mov operations with zero cycle delay.

Agner,
22.13 Instructions with no latency
Register-to-register move instructions are resolved at
the register rename stage without using any execution units.
These instructions have zero latency. It is possible to do six such
register renamings per clock cycle, and it is even possible to
rename the same register multiple times in one clock cycle.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
Commit bda9ca3e44c1b67d1c4ed145bb7071c340fe8961 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests with non-eliminatible MMX moves

In Zen3, MMX moves are *not* eliminated,
i've verified this with llvm-exegesis.
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s