SuccessChanges

Summary

  1. AMDGPU: Correct const_index_stride for wave 32 for PAL ABI (details)
  2. [NFC] (test commit) Changed example invocation of C++ for OpenCL (details)
  3. [X86] Ensure we pass DebugLoc by const reference where possible. NFCI. (details)
  4. [SLP] Regenerate tests to reduce diff in D98714. NFCI. (details)
  5. Revert "AMDGPU: Correct const_index_stride for wave 32 for PAL ABI" (details)
  6. [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts (details)
  7. [DebugInfo] Fix crash when emitting an invalidated SDDbgValue (details)
  8. [NFC] Correctly assert the indents for printEnumValHelpStr. (details)
  9. [OpenCL] Fix optional image types. (details)
  10. [ARM] Transforming memset to Tail predicated Loop (details)
  11. Fix: [DebugInfo] Fix crash when emitting an invalidated SDDbgValue (details)
  12. AMDGPU: Correct const_index_stride for wave 32 for PAL ABI (details)
  13. [AMDGPU] Restrict immediate scratch offsets (details)
  14. Retire TargetRegisterInfo::getSpillAlignment (details)
  15. [DAG] Ensure all SD classes consistently return a const reference with getDebugLoc(). NFCI. (details)
  16. [CodeGen] Ensure UserValue::getDebugLoc() and UserLabel::getDebugLoc() consistently return a const reference NFCI. (details)
  17. Reapply "[DebugInfo] Drop DBG_VALUE_LISTs with an excessive number of debug operands" (details)
  18. [libc++] [test] Test that list::swap/move/move-assign does not invalidate iterators. (details)
  19. [libc++] [test] Simplify arithmetic in list.special/swap.pass.cpp. NFCI. (details)
  20. [libc++] [test] Test that unordered_*::swap/move/assign does not invalidate iterators. (details)
  21. [NFC][X86][MCA] Increase iteration count in reg move elimination tests (details)
  22. [NFC][X86] AMD Zen 3: move sched classes for renameables moves togeter (details)
  23. [X86] AMD Zen 3: throughput for renameable GPR moves is 6 (details)
  24. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable SSE XMM moves (details)
  25. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX XMM moves (details)
  26. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX YMM moves (details)
  27. [X86] AMD Zen 3: SSE XMM moves are zero-cycle (details)
  28. [X86] AMD Zen 3: AVX XMM moves are zero-cycle (details)
  29. [X86] AMD Zen 3: AVX YMM moves are zero-cycle (details)
  30. [X86] AMD Zen 3: throughput for renameable XMM/YMM moves is 6 (details)
  31. [NFC][X86][MCA] AMD Zen3 Decrease iteration count in reg-move-elimination tests (details)
  32. [PowerPC] Provide MMA builtins for compatibility (details)
  33. [mlir] Rename BufferAliasAnalysis to BufferViewFlowAnalysis (details)
  34. [mlir][linalg] Remove redundant indexOp builder. (details)
  35. [libomptarget] Add support for target memory allocators to cuda RTL (details)
  36. [AArch64] add test for missed vectorization; NFC (details)
  37. BasicAA: Recognize inttoptr as isEscapeSource (details)
  38. [mlir][spirv] add support lowering of extract_slice to scalar type (details)
  39. [mlir][vector] add pattern to cast away leading unit dim for elementwise op (details)
Commit 442de0c1adf36bfddb5fb66b442bba8999fa733b by david.stuttard
AMDGPU: Correct const_index_stride for wave 32 for PAL ABI

Since there is a single scratch resource descriptor for all shaders, if there is
a wave32 and a wave64 shader (for instance for VsFs pairs)
then the const_index_stride will be incorrect for wave32 shaders.

Differential Revision: https://reviews.llvm.org/D101830

Change-Id: Id8de5566b0d1a07a814e2e7db016df9d20bf6d2c
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
Commit f372ff17f74f99f5e1c021a9c919b33c4caf38d9 by olemarius.strohm
[NFC] (test commit) Changed example invocation of C++ for OpenCL
The file was modifiedclang/docs/OpenCLSupport.rst
Commit 8e42024f79997827cefe00d31cd3bc55d1551fec by llvm-dev
[X86] Ensure we pass DebugLoc by const reference where possible. NFCI.

Avoids a lot of unnecessary tracking increments/decrements of the underlying TrackingMDNodeRef
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2a3f60b5f5304f61cab3654a6afb67b79ca7df86 by llvm-dev
[SLP] Regenerate tests to reduce diff in D98714. NFCI.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
Commit 793b4b26039e461dc3142a3f667ba7c97b0ed920 by david.stuttard
Revert "AMDGPU: Correct const_index_stride for wave 32 for PAL ABI"

This reverts commit 442de0c1adf36bfddb5fb66b442bba8999fa733b.
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Commit 280aa3415e408cacc520274fdb948ec9fc63865a by llvm-dev
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts

Based off a discussion on D89281 - where the AARCH64 implementations were being replaced to use funnel shifts.

Any target that has efficient funnel shift lowering can handle the shift parts expansion using the same expansion, avoiding a lot of duplication.

I've generalized the X86 implementation and moved it to TargetLowering - so far I've found that AARCH64 and AMDGPU benefit, but many other targets (ARM, PowerPC + RISCV in particular) could easily use this with a few minor improvements to their funnel shift lowering (or the folding of their target ops that funnel shifts lower to).

NOTE: I'm trying to avoid adding full SHIFT_PARTS legalizer handling as I think it might actually be possible to remove these opcodes in the medium-term and use funnel shift / libcall expansion directly.

Differential Revision: https://reviews.llvm.org/D101987
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_uint.ll
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_sint.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sra.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-long-shift.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srl.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit ce0c1f3ced9bccb29c34b87de82c5cdffcbcd457 by stephen.tozer
[DebugInfo] Fix crash when emitting an invalidated SDDbgValue

This patch fixes a crash in the compiler that occurs when certain
invalidated SDDbgValues are emitted. The cause of this was that we would
attempt to check the liveness of the debug value's operands, which
triggers an assert if any of those operands are invalid. This patch
changes this check such that it only occurs if the SDDbgValue is valid;
if not, the check is irrelevant anyway, so can be safely ignored.

Differential Revision: https://reviews.llvm.org/D101540
The file was addedllvm/test/DebugInfo/Generic/invalidated-dbg-value-is-undef.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Commit d9f2960c932c9803e662098e33d899efa3c67f44 by joachim
[NFC] Correctly assert the indents for printEnumValHelpStr.

Only verify that there's no negative indent.
Noted by @chapuni in https://reviews.llvm.org/D93494.

Reviewed By: chapuni

Differential Revision: https://reviews.llvm.org/D102021
The file was modifiedllvm/lib/Support/CommandLine.cpp
Commit 76f1de10f43ec4d1eb6146c45ccd6f93df5aa3e1 by anastasia.stulova
[OpenCL] Fix optional image types.

This change allows the use of identifiers for image types
from `cl_khr_gl_msaa_sharing` freely in the kernel code if
the extension is not supported since they are not in the
list of the reserved identifiers.

This change also removed the need for pragma for the types
in the extensions since the spec does not require the pragma
uses.

Differential Revision: https://reviews.llvm.org/D100983
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/Basic/OpenCLImageTypes.def
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/test/SemaOpenCL/access-qualifier.cl
The file was modifiedclang/test/SemaOpenCL/invalid-image.cl
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit dfe3ffaa4a47ea93cc289b4496c093fbaf73adbc by malhar.jajoo
[ARM] Transforming memset to Tail predicated Loop

This patch converts llvm.memset intrinsic into Tail Predicated
Hardware loops for a target that supports the Arm M-profile
Vector Extension (MVE).

The llvm.memset is converted to a TP loop for both
constant and non-constant input sizes (of llvm.memset).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D100435
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/test/CodeGen/Thumb2/mve-tp-loop.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
The file was modifiedllvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-phireg.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 14818a86d044909d8eeb1f39f689e2785a09823b by stephen.tozer
Fix: [DebugInfo] Fix crash when emitting an invalidated SDDbgValue

This patch is a fix for revision ce0c1f3c, which caused test failures on
bots without x86 as a registered target. This patch moves the test added
in the prior patch to the x86 folder, so that it only runs on bots with
the correct target available.
The file was removedllvm/test/DebugInfo/Generic/invalidated-dbg-value-is-undef.ll
The file was addedllvm/test/DebugInfo/X86/invalidated-dbg-value-is-undef.ll
Commit 606d4e806192013ff7da33351f671d08b4524438 by david.stuttard
AMDGPU: Correct const_index_stride for wave 32 for PAL ABI

Retrying after revert and fix (removed implicit def flag from operand). Now
passes with expensive_checks enabled.

Since there is a single scratch resource descriptor for all shaders, if there is
a wave32 and a wave64 shader (for instance for VsFs pairs)
then the const_index_stride will be incorrect for wave32 shaders.

Differential Revision: https://reviews.llvm.org/D101830

Change-Id: Ie3b8b2921237968caca91527dd0c97b1b0cc0360
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Commit 13c0316239dc31a34262f2270d0952aa152a9a76 by sebastian.neubauer
[AMDGPU] Restrict immediate scratch offsets

gfx9 does not work with negative offsets, gfx10 works only with
aligned negative offsets, but not with unaligned negative offsets.

This is slightly more conservative than needed, gfx9 does support
negative offsets when a VGPR address is used and gfx10 supports
negative, unaligned offsets when an SGPR address is used, but we
do not make use of that with this patch.

Differential Revision: https://reviews.llvm.org/D101292
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
Commit 6248d1119040d5031b248633005998b94b8024d4 by benny.kra
Retire TargetRegisterInfo::getSpillAlignment

getSpillAlign does the same thing.
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Commit dd21c6b843b25d2d65daab561fe47b4157c32952 by llvm-dev
[DAG] Ensure all SD classes consistently return a const reference with getDebugLoc(). NFCI.

Avoids a lot of unnecessary tracking increments/decrements of the underlying TrackingMDNodeRef.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
Commit c9d4b4173b56c5a56d32d07be660f872b9746f87 by llvm-dev
[CodeGen] Ensure UserValue::getDebugLoc() and UserLabel::getDebugLoc() consistently return a const reference NFCI.

Avoids a lot of unnecessary tracking increments/decrements of the underlying TrackingMDNodeRef.
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
Commit 7bc1dd1191aba77da83f04415ee646cc3381729e by stephen.tozer
Reapply "[DebugInfo] Drop DBG_VALUE_LISTs with an excessive number of debug operands"

Reapply b623df3c, which was reverted while reverting a different patch
with a breaking change. There are no underlying issues with this patch,
so no changes have been made to the original patch.

This reverts commit b11e4c990771541e440861f017afea7b4ba162f4.
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
The file was addedllvm/test/DebugInfo/X86/live-debug-vars-loc-limit.ll
Commit 8935c8449b7b17049990d29443ed29dde315f281 by arthur.j.odwyer
[libc++] [test] Test that list::swap/move/move-assign does not invalidate iterators.

And remove the dedicated debug-iterator test; we want to test this in all modes.
We have a CI step for testing the whole test suite with `--debug_level=1` now.

Part of https://reviews.llvm.org/D102003
The file was modifiedlibcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
The file was removedlibcxx/test/libcxx/containers/sequences/list/list.cons/db_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/list/list.cons/assign_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/list/list.cons/move.pass.cpp
Commit a1f75bf091a20132dc44828a2a9a68d559f922f3 by arthur.j.odwyer
[libc++] [test] Simplify arithmetic in list.special/swap.pass.cpp. NFCI.

Part of https://reviews.llvm.org/D102003
The file was modifiedlibcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
Commit f42355e17c3f3d1d099d028a388796a64724ffdb by arthur.j.odwyer
[libc++] [test] Test that unordered_*::swap/move/assign does not invalidate iterators.

And remove the dedicated debug-iterator tests; we want to test this in all modes.
We have a CI step for testing the whole test suite with `--debug_level=1` now.

Part of https://reviews.llvm.org/D102003
The file was modifiedlibcxx/test/std/containers/unord/unord.map/unord.map.swap/swap_non_member.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multiset/unord.multiset.swap/swap_non_member.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multimap/unord.multimap.cnstr/assign_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/unord.set.cnstr/assign_move.pass.cpp
The file was removedlibcxx/test/libcxx/containers/unord/unord.set/db_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/unord.set.cnstr/move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multiset/unord.multiset.cnstr/assign_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multiset/unord.multiset.cnstr/move.pass.cpp
The file was removedlibcxx/test/libcxx/containers/unord/unord.map/db_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multimap/unord.multimap.cnstr/move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multimap/unord.multimap.swap/swap_non_member.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.map/unord.map.cnstr/move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.map/unord.map.cnstr/assign_move.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/unord.set.swap/swap_non_member.pass.cpp
The file was removedlibcxx/test/libcxx/containers/unord/unord.multimap/db_move.pass.cpp
The file was removedlibcxx/test/libcxx/containers/unord/unord.multiset/db_move.pass.cpp
Commit e6d688ec96706c1bbcb27419333828ec61752fab by lebedev.ri
[NFC][X86][MCA] Increase iteration count in reg move elimination tests

So the IPC actually stabilizes at 6.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s
Commit c3cd8ed0097b07e5454255ffe5899ded21ca0bff by lebedev.ri
[NFC][X86] AMD Zen 3: move sched classes for renameables moves togeter
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit d8c6202576771f0e1478b3abdd246600caf7d704 by lebedev.ri
[X86] AMD Zen 3: throughput for renameable GPR moves is 6

They are resolved at the register rename stage without
using any execution units.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit cbabe4f4d62a6bcee206e0673de559805a092420 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: Add tests for renameable SSE XMM moves
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s
Commit bcbfc22ff9b2f16d77489b0ce34e8d96e4f9ae5b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX XMM moves
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
Commit 0d961fbd525cb7df3e981d6469b81cbf8f5e5883 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX YMM moves
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
Commit 9db4203883f57f34e7e88fd6deb761ef8a9f7d5a by lebedev.ri
[X86] AMD Zen 3: SSE XMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

Refs:
AMD SOG 19h, 2.9.4 Zero Cycle Move
The processor is able to execute certain register to register
mov operations with zero cycle delay.

Agner,
22.13 Instructions with no latency
Register-to-register move instructions are resolved at
the register rename stage without using any execution units.
These instructions have zero latency. It is possible to do six such
register renamings per clock cycle, and it is even possible to
rename the same register multiple times in one clock cycle.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit ee020b930d1299acf42b759dd15a44d2020ef963 by lebedev.ri
[X86] AMD Zen 3: AVX XMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
Commit 715c0d0bd412141e0404d5bfcad4dddac3bfc0d0 by lebedev.ri
[X86] AMD Zen 3: AVX YMM moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 758c173309edbd6ac3958eb08dc01b6524badff8 by lebedev.ri
[X86] AMD Zen 3: throughput for renameable XMM/YMM moves is 6

They are resolved at the register rename stage without
using any execution units.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/resources-avx1.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s
Commit 34de155f7e335e9e69276356565dcc31ed7d8535 by lebedev.ri
[NFC][X86][MCA] AMD Zen3 Decrease iteration count in reg-move-elimination tests

Drop it just enough so it still produces the right IPC.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-xmm.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-avx-ymm.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-sse-xmm.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s
Commit 25bbff632d018d178272a61c0732203d53d3a2e3 by saghir
[PowerPC] Provide MMA builtins for compatibility

Vector pair intrinsics and builtins were renamed in
https://reviews.llvm.org/D91974 to replace the _mma_ prefix by _vsx_.
However, some projects used the _mma_ version, so this patch adds
these intrinsics to provide compatibility.

Fixes Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=50159

Reviewed By: nemanjai, amyk

Differential Revision: https://reviews.llvm.org/D100482
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/CodeGen/builtins-ppc-pair-mma.c
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit faab8c140ab2480d978ccc3ea11cbc3b279736b6 by tpopp
[mlir] Rename BufferAliasAnalysis to BufferViewFlowAnalysis

This it to make more clear the difference between this and
an AliasAnalysis.

For example, given a sequence of subviews that create values
A -> B -> C -> d:
BufferViewFlowAnalysis::resolve(B) => {B, C, D}
AliasAnalysis::resolve(B) => {A, B, C, D}

Differential Revision: https://reviews.llvm.org/D100838
The file was modifiedmlir/include/mlir/Transforms/BufferUtils.h
The file was removedmlir/include/mlir/Analysis/BufferAliasAnalysis.h
The file was removedmlir/lib/Analysis/BufferAliasAnalysis.cpp
The file was modifiedmlir/lib/Analysis/CMakeLists.txt
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
The file was modifiedmlir/lib/Transforms/BufferOptimizations.cpp
The file was addedmlir/include/mlir/Analysis/BufferViewFlowAnalysis.h
The file was addedmlir/lib/Analysis/BufferViewFlowAnalysis.cpp
The file was modifiedmlir/include/mlir/Transforms/Bufferize.h
Commit f31531a30b124042d8523b7d50053ade82659c5b by gysit
[mlir][linalg] Remove redundant indexOp builder.

Remove the builder signature taking a signed dimension identifier.

Reviewed By: ergawy

Differential Revision: https://reviews.llvm.org/D102055
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
Commit a15f8589f4e81973b096a5ccc7b5b687c3284ebe by huberjn
[libomptarget] Add support for target memory allocators to cuda RTL

Summary:
The allocator interface added in D97883 allows the RTL to allocate shared and
host-pinned memory from the cuda plugin. This patch adds support for these to
the runtime.

Reviewed By: grokos

Differential Revision: https://reviews.llvm.org/D102000
The file was modifiedopenmp/libomptarget/plugins/cuda/src/rtl.cpp
The file was addedopenmp/libomptarget/test/api/omp_device_managed_memory.c
The file was addedopenmp/libomptarget/test/api/omp_host_pinned_memory.c
The file was modifiedopenmp/libomptarget/plugins/common/MemoryManager/MemoryManager.h
Commit 0a6f11aabdd3f116b603694a0d4f9abbba62ade4 by spatel
[AArch64] add test for missed vectorization; NFC

This is a reduction of the example in:
https://llvm.org/PR50256
The file was addedllvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
Commit bc302bfbef84bd778a9e5e0a1b5851c6a55c1d9c by jotrem
BasicAA: Recognize inttoptr as isEscapeSource

Pointers escape when converted to integers, so a pointer produced by
converting an integer to a pointer must not be a local non-escaping
object.

Reviewed By: nikic, nlopes, aqjune

Differential Revision: https://reviews.llvm.org/D101541
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was addedllvm/test/Analysis/BasicAA/noalias-inttoptr.ll
Commit 565ee6afc707d5744d0ec90936f0c0564c1acf69 by thomasraoux
[mlir][spirv] add support lowering of extract_slice to scalar type

Differential Revision: https://reviews.llvm.org/D102041
The file was modifiedmlir/test/Conversion/VectorToSPIRV/simple.mlir
The file was modifiedmlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
Commit a970e69d6b62d60c4c222e2a4be0a73999c97651 by thomasraoux
[mlir][vector] add pattern to cast away leading unit dim for elementwise op

Differential Revision: https://reviews.llvm.org/D102034
The file was modifiedmlir/test/Dialect/Vector/vector-transforms.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp