SuccessChanges

Summary

  1. NFC: Move TypeList implementation up the file (details)
  2. Make `hasTypeLoc` matcher support more node types. (details)
  3. [GlobalISel] Don't form zero/sign extending loads for atomics. (details)
  4. [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. (details)
  5. [mlir][vector] Fix warning (details)
Commit 0ad494838b8576de14144776490faa710fa2a099 by steveire
NFC: Move TypeList implementation up the file

This will make it possible for more code to use it.
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
Commit 1f65f42dd37ab6a950d3ec110e3efca0ace1b615 by steveire
Make `hasTypeLoc` matcher support more node types.

Differential Revision: https://reviews.llvm.org/D101572
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/docs/LibASTMatchersReference.html
Commit 808bc11d9e1aa01edaf7ec4e56be3aee5ed42a83 by Amara Emerson
[GlobalISel] Don't form zero/sign extending loads for atomics.

For importing patterns, we only support matching G_LOAD, not G_ZEXTLOAD or
G_SEXTLOAD.

Differential Revision: https://reviews.llvm.org/D101932
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit 5b158093e2469dec16a070019c6432d26bf7be9b by Amara Emerson
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.

We never bothered to have a separate set of combines for -O0 in the prelegalizer
before. This results in some minor performance hits for a mode where performance
isn't a concern (although not regressing code size significantly is still preferable).

This also removes the CSE option since we don't need it for -O0.

Through experiments, I've arrived at a set of combines that gets the most code
size improvement at -O0, while reducing the amount of time spent in the combiner
by around 35% give or take.

Differential Revision: https://reviews.llvm.org/D102038
The file was modifiedllvm/lib/Target/AArch64/AArch64.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
The file was removedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
The file was modifiedllvm/lib/Target/AArch64/CMakeLists.txt
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
The file was addedllvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
Commit 6aaf06f92988c6e2b91f90ab7ed3a6d21981480a by thomasraoux
[mlir][vector] Fix warning

Previous change caused another warning in some build configuration:
"default label in switch which covers all enumeration values"
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp