AbortedChanges

Summary

  1. [VP] Improve the VP intrinsic unittests (details)
  2. [CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols (details)
  3. [LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC. (details)
  4. [MLIR] Switch llvm.noalias to a unit attribute (details)
  5. [AMDGPU] Add some GFX10.3 testing. NFC. (details)
  6. [RegAllocFast] properly handle STATEPOINT instruction. (details)
  7. [PowerPC][Bug] Fix Bug in Stack Frame Update Code (details)
  8. [LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling. (details)
  9. [libomptarget][nfc] Drop stringify in macro (details)
  10. [OpenCL] Allow use of double type without extension pragma. (details)
  11. [AMDGPU] Move code sinking before structurizer (details)
  12. [SLP] restrict matching of load combine candidates (details)
  13. [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again (details)
  14. CodeGen: Fix null dereference before null check (details)
Commit b159987054e12ad9f5b5e373249cbdba90047b84 by simon.moll
[VP] Improve the VP intrinsic unittests

Test that all VP intrinsics are tested.
Test intrinsic id -> opcode -> intrinsic id round tripping.
Test property scopes in the include/llvm/IR/VPIntrinsics.def file.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D93534
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
Commit b2f21b145aecbf5bc1af63b79de395897fc2e6f4 by wingo
[CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols

As we have been missing support for WebAssembly globals on the IR level,
the lowering of WASM_SYMBOL_TYPE_GLOBAL to IR was incomplete.  This
commit fleshes out the lowering support, lowering references to and
definitions of addrspace(1) values to correctly typed
WASM_SYMBOL_TYPE_GLOBAL symbols.

Depends on D101608.

Differential Revision: https://reviews.llvm.org/D101913
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/global-get.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global-set.ll
Commit 518b7f913526b5d002751edfa88869d10f5412fc by martin
[LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC.

As this isn't handled as a regular relocation, the normal handling of
maybeReportRelocationToDiscarded in Chunks.cpp doesn't apply here.

This would have caught the issue fixed by
82de4e075339f5ad8d68cfe31eb45b771d4750ae.

Differential Revision: https://reviews.llvm.org/D102115
The file was modifiedlld/COFF/DLL.cpp
Commit 1c777ab459d7ee181d7aba62af8bc35a572a2290 by uday
[MLIR] Switch llvm.noalias to a unit attribute

Switch llvm.noalias attribute from a boolean attribute to a unit
attribute.

Differential Revision: https://reviews.llvm.org/D102225
The file was modifiedmlir/test/Target/LLVMIR/llvmir-invalid.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/func.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
Commit 3b873831c439021da736fdc7c2c54bd0da2869ea by jay.foad
[AMDGPU] Add some GFX10.3 testing. NFC.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/readcyclecounter.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/readcyclecounter.ll
Commit df47368d406aa4b9aaa7dd49026a0eff9763e6ca by dantrushin
[RegAllocFast] properly handle STATEPOINT instruction.

STATEPOINT is a fancy and complex pseudo instruction which
has both tied defs and regmask operand.

Basic FastRA algorithm is as follows:

1. Mark registers used by defs as free
2. If instruction has regmask operand displace clobbered registers
   according to regmask.
3. Assign registers for use operands.

In case of tied defs step 1 is replaced with allocation of registers
for them. But regmask is still processed, which may displace already
allocated registers. As a result, tied use and def will get assigned
to different registers.

This patch makes FastRA to process instruction's RegMask (if any) when
checking for physical registers interference.
That way tied operands won't get registers clobbered by regmask.

Reviewed By: arsenm, skatkov
Differential Revision: https://reviews.llvm.org/D99284
The file was addedllvm/test/CodeGen/X86/statepoint-fastregalloc.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit c79bc5942d0efd4740c7a6d36ad951c59ef3bc0e by stefanp
[PowerPC][Bug] Fix Bug in Stack Frame Update Code

The stack frame update code does not take into consideration spilling
to registers for callee saved registers. The option -ppc-enable-pe-vector-spills
turns on spilling to registers for callee saved registers and may expose a bug
in the code that moves a stack frame pointer update instruction.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101366
The file was addedllvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit 3f03877f5a838973d0d22f6b45c112228319f4da by martin
[LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling.

Differential Revision: https://reviews.llvm.org/D101903
The file was modifiedlldb/CMakeLists.txt
Commit dedca78d486e6532ad0d01f670c409c7339e6387 by jonathanchesterfield
[libomptarget][nfc] Drop stringify in macro

[libomptarget][nfc] Drop stringify in macro
A step towards deleting the macros entirely.

Differential Revision: https://reviews.llvm.org/D102228
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
Commit 13ea238b1e1db96ef5fd409e869d9a8ebeef1332 by anastasia.stulova
[OpenCL] Allow use of double type without extension pragma.

Simply use of extensions by allowing the use of supported
double types without the pragma. Since earlier standards
instructed that the pragma is used explicitly a new warning
is introduced in pedantic mode to indicate that use of
type without extension pragma enable can be non-portable.

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior
of the compiler less strict by accepting code without extra
pragma statements.

Differential Revision: https://reviews.llvm.org/D100980
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaOpenCL/extensions.cl
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/test/Misc/warning-flags.c
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit 09fe84abb4ee71f707c3ec8e960a42d8292f6211 by Piotr Sobczak
[AMDGPU] Move code sinking before structurizer

Moving code sinking pass before structurizer creates more sinking
opportunities.

The extra flow edges introduced by the structurizer can have adverse
effects on sinking, because the sinking pass prefers moving instructions
to blocks with unique predecessors and the structurizer destroys that
property in some cases.

A notable example is moving high-latency image instructions across kills.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D101115
The file was addedllvm/test/CodeGen/AMDGPU/sink-image-sample.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multilevel-break.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
Commit 49950cb1f6f699cbb9d8f141c0c043d4795c3417 by spatel
[SLP] restrict matching of load combine candidates

The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.

Differential Revision: https://reviews.llvm.org/D102074
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit c02476f3158f2908ef0a6f628210b5380bd33695 by lebedev.ri
[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again

Instead of handling power-of-two sized vector chunks,
try handling the large vector in a stream mode,
decreasing the operational vector size
once it no longer works for the elements left to process.

Notably, this improves costs for overaligned loads - loading padding is fine.
This more directly tracks when we need to insert/extract the YMM/XMM subvector,
some costs fluctuate because of that.

Reviewed By: RKSimon, ABataev

Differential Revision: https://reviews.llvm.org/D100684
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/load_store.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit bce3cca4889a9e4ab7b9652b0c44bb49ca8f3bad by Matthew.Arsenault
CodeGen: Fix null dereference before null check
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp