UnstableChanges

Summary

  1. [mlir] Move move capture in SparseElementsAttr::getValues (details)
  2. [NFC][LSAN] Limit the number of concurrent threads is the test (details)
  3. [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (details)
  4. [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract (details)
  5. [OpenMP] Changes to enable MSVC ARM64 build of libomp (details)
  6. [RISCV] Regenerate stepvector.ll. NFC (details)
  7. [hwasan] Stress test for thread creation. (details)
  8. [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 (details)
Commit 731206f3684af5979e3a794970db83f9a34b4541 by riddleriver
[mlir] Move move capture in SparseElementsAttr::getValues

This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
Commit 2a73b7bd8cf7620fc0e478ac838b07ee6649dd8a by Vitaly Buka
[NFC][LSAN] Limit the number of concurrent threads is the test

Test still fails with D88184 reverted.

The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D102218
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 69069509b2d3cb0e0bcf6e38e0ab05c432adc763 by Amara Emerson
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
Commit ffbffaf6b6b0fc06abb7b43ec8de8bc61d941bc7 by albionapc
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.

Differential: https://reviews.llvm.org/D100604
The file was addedllvm/test/CodeGen/PowerPC/vec-extract-itofp.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
Commit 4fb0aaf03381473ec8af727edb4b5d59b64b0d60 by Andrey.Churbanov
[OpenMP] Changes to enable MSVC ARM64 build of libomp

This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.

Differential Revision: https://reviews.llvm.org/D101173
The file was modifiedopenmp/runtime/src/dllexports
The file was modifiedopenmp/runtime/src/kmp_atomic.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_os.h
The file was modifiedopenmp/runtime/src/z_Windows_NT-586_util.cpp
The file was modifiedopenmp/runtime/src/kmp_platform.h
The file was modifiedopenmp/runtime/src/CMakeLists.txt
Commit d092dd56aed8af64425446544ca7c9a0616d86ce by craig.topper
[RISCV] Regenerate stepvector.ll. NFC

It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
Commit a7757f6c22e45e84e56da79af67fe29dd1c224f5 by eugenis
[hwasan] Stress test for thread creation.

This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.

The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.

Differential Revision: https://reviews.llvm.org/D101936
The file was addedcompiler-rt/test/hwasan/TestCases/Linux/create-thread-stress.cpp
Commit 4433f4601e8a8e36ddd9bb6f6ed394bda353b828 by Austin.Kerbow
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2

The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102252
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td