FailedChanges

Summary

  1. [libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages (details)
  2. [mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard... (details)
  3. [clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule (details)
  4. Revert "[scudo] Enable arm32 arch" (details)
  5. [mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize... (details)
  6. [clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers (details)
  7. [x86] add test for pcmpeq with 0; NFC (details)
  8. [x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ (details)
  9. [AMDGPU] Remove assert (details)
  10. [mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern... (details)
  11. [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. (details)
  12. [InstCombine] ~(C + X) --> ~C - X (PR50308) (details)
  13. [AMDGPU] Improve Codegen for build_vector (details)
  14. [llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly (details)
  15. [Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64 (details)
  16. [NFC] Use variable GEP index in vec_demanded_elts tests (details)
  17. [clang][AVR] Redefine some types to be compatible with avr-gcc (details)
  18. [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr (details)
Commit 96100f15082679b2c75c7744b8eb4fc87fcf71f5 by kbessonova
[libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages

Differential Revision: https://reviews.llvm.org/D102195
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/deque
The file was modifiedlibcxx/include/list
The file was modifiedlibcxx/include/__hash_table
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/include/vector
Commit 0fb364a97e74abd3d3700b8f18bbfed787fbfdbb by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102236
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
The file was modifiedmlir/include/mlir/Conversion/LinalgToStandard/LinalgToStandard.h
Commit 163325086c35b3984c5e6f7a2adb6022003fcd84 by n.james93
[clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule

The `IgnoreArray` flag was not used before while running the rule. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=47288 | b/47288 ]]

Reviewed By: njames93

Differential Revision: https://reviews.llvm.org/D101239
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-pro-type-member-init.ignorearrays.cpp
Commit 7d0a81ca38e427de9b7fb0961ec643b757028131 by david.spickett
Revert "[scudo] Enable arm32 arch"

This reverts commit b1a77e465e37fc400c16f9fda2a637f11c698bb9.

Which has a failing test on our armv7 bots:
https://lab.llvm.org/buildbot/#/builders/59/builds/1812
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit c6b96ae06f70bd0ecd28995ffc45d87edd89a84d by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102308
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
Commit 4c59ab34f7bda74296e42ef7ea8d83828cb45558 by n.james93
[clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers

There should be a follow up to this for changing the traversal mode, but some of the tests don't like that.

Reviewed By: steveire

Differential Revision: https://reviews.llvm.org/D101614
The file was modifiedclang-tools-extra/clang-tidy/bugprone/SizeofExpressionCheck.cpp
Commit 24d06fff55510780eba1a267d844ee26a17d6888 by spatel
[x86] add test for pcmpeq with 0; NFC
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
Commit f58e0513dd95944b81ce7a6e7b49ba656de7d75f by spatel
[x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ

This is motivated by the example in https://llvm.org/PR50055 ,
but it doesn't do anything for that bug currently because we
don't actually have a zero-extended setcc there.

Proof for the generic transform (inverse of what we would
try to do in combining):
https://alive2.llvm.org/ce/z/aBL-Mg

Differential Revision: https://reviews.llvm.org/D102275
The file was modifiedllvm/test/CodeGen/X86/vsel-cmp-load.ll
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
Commit a4db7025a9762c568c7bc9fdd3c64f4a60e31cfc by Piotr Sobczak
[AMDGPU] Remove assert

Remove assert introduced in D101177, following post-commit feedback.
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit 06bb9cf30d11247540d5b3f2a714f3aa640353e6 by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102245
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns.mlir
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
Commit a383d325f6c6c8d9bb52d1da221d9a144dfc475c by jay.foad
[TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.

In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.

Differential Revision: https://reviews.llvm.org/D102318
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
Commit 554b1bced325a8d860ad00bd59020d66d01c95f8 by lebedev.ri
[InstCombine] ~(C + X) --> ~C - X (PR50308)

We can not rely on (C+X)-->(X+C) already happening,
because we might not have visited that `add` yet.
The added testcase would get stuck in an endless combine loop.
The file was modifiedllvm/test/Transforms/InstCombine/not-add.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 46adccc5cc1095f57b65fb2a17a4a023ccc77eb9 by jay.foad
[AMDGPU] Improve Codegen for build_vector

Improve the code generation of build_vector.
Use the v_pack_b32_f16 instruction instead of
v_and_b32 + v_lshl_or_b32

Differential Revision: https://reviews.llvm.org/D98081

Patch by Julien Pag├Ęs!
The file was modifiedllvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fexp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
The file was addedllvm/test/CodeGen/AMDGPU/v_pack.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
Commit 5a439015393e616b2faed9a9fbb1d7036b28e786 by gkm
[llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly

`__mh_(execute|dylib|dylinker|bundle|preload|object)_header` are special symbols whose values hold the VMA of the Mach header to support introspection. They are attached to the first section in `__TEXT`, even though their addresses are outside `__TEXT`, and they do not refer to code.

It is normally harmless, but when the first section of `__TEXT` has no other symbols, `__mh_*_header` is considered by the disassembler when determing function boundaries. Since `__mh_*_header` refers to an address outside `__TEXT`, the boundary determination fails and disassembly quits.

Since `__TEXT,__text` normally has symbols, this bug is obscured. Experiments placing `__stubs` and `__stub_helper` first exposed the bug, since neither has symbols.

Differential Revision: https://reviews.llvm.org/D101786
The file was addedllvm/test/tools/llvm-objdump/MachO/no-text-symbols-disassembly.test
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 4b98199ce8fb94d0de46e04b4d7b3a699691d2e1 by martin
[Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64

The bug (PR50227, affecting COFF) that caused the revert in
6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 has been fixed in
382c505d9cfca8adaec47aea2da7bbcbc00fc05c now, so it should be safe
to reenable the pass for that target (and ELF).

In PR50227 it's also mentioned that the same pass seems to cause
problems on aarch64 on darwin, so leaving it disabled there for now.
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit 61630814b1d0415953fd4d1a58427836487f356c by david.sherwood
[NFC] Use variable GEP index in vec_demanded_elts tests

I've changed a test in each of these files:

  Transforms/InstCombine/vec_demanded_elts.ll
  Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll

to use a variable GEP index instead of a constant value so that
we're testing the more general case.
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Commit 892c56eabe250acaeb761eaddf783f47d95f7f4d by powerman1st
[clang][AVR] Redefine some types to be compatible with avr-gcc

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D100701
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/lib/Basic/Targets/AVR.cpp
The file was modifiedclang/test/CodeGen/builtins.cpp
Commit 3fa6510f6ea0101c70592487074957bb1cde576c by peter.waller
[CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr

When a ptest is used to set flags from the output of rdffr, the ptest
can be eliminated, using a flags-setting rdffrs instead.

Additionally, check that nothing consumes flags between rdffr and ptest;
this case appears to have been missed previously.

* There is no unpredicated RDFFRS instruction.
* If substituting RDFFR_PP, require that the mask argument of the
  PTEST matches that of the RDFFR_PP.
* Move some precondition code up inside optimizePTestInstr, so that it
  covers the new code paths for RDFFR which return earlier.
  * Only consider RDFFR, PTEST in same basic block.
  * Check for other flag setting instructions between the two, abort if
    found.
  * Drop an old TODO comment about removing dead PTEST instructions.

RDFFR_P to follow in later patch.

Differential Revision: https://reviews.llvm.org/D101357
The file was addedllvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp