FailedChanges

Summary

  1. [DAGCombiner] Add test exposing bug in DAG combine. (details)
  2. [DAGCombiner] Fix DAG combine store elimination, different address space. (details)
  3. Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics" (details)
  4. [ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements() (details)
  5. [CUDA][HIP] Fix device template variables (details)
  6. [llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility. (details)
  7. [OpenCL] Remove pragma requirement from Arm dot extension. (details)
  8. [mlir][openacc] Conversion of data operand to LLVM IR dialect (details)
  9. [TargetLowering] Improve legalization of scalable vector types (details)
  10. [X86][AVX] Add v4i64 shift-by-32 tests (details)
  11. [X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI. (details)
  12. Fix grammar in README.md (details)
  13. [AMDGPU] Disable the SIFormMemoryClauses pass at -O1 (details)
  14. [PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td (details)
  15. [MLIR] Factor pass timing out into a dedicated timing manager (details)
  16. [docs] Fix documentation for bugprone-dangling-handle (details)
  17. [SystemZ][z/OS] Fix warning caused by umask returning a signed integer type (details)
  18. [libomptarget][amdgpu][nfc] Expand errorcheck macros (details)
  19. [lld-macho] Implement branch-range-extension thunks (details)
  20. [AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting. (details)
  21. [mlir][sparse] keep runtime support library signature consistent (details)
  22. [X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621) (details)
  23. Update static bound checker for Linalg to cover decreasing cases (details)
  24. [CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions (details)
  25. [X86] Fix -Wunused-lambda-capture (details)
  26. [NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl (details)
  27. [NFC][clang][Codegen] Split ThunkInfo into it's own header (details)
  28. [mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin) (details)
Commit 4b00ffa767fc8a71c2eaf544cb6397f6db34eb6a by hgreving
[DAGCombiner] Add test exposing bug in DAG combine.

Adds a test in X86, exposing a bug in DAG combine eliminating stores that
are the same value but no the same address space.

Differential Revision: https://reviews.llvm.org/D102243
The file was addedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
Commit 762ac725bf9775536dda5b3dda13574f14a8c2b9 by hgreving
[DAGCombiner] Fix DAG combine store elimination, different address space.

Fixes a bug in the DAG combiner that eliminates the stores because it missed
to inspect the address space of the pointers.

%v = load %ptr_as1
// no chain side effect
store %v, %ptr_as2

As well as

store %v, %ptr_as1
store %v, %ptr_as2

Fixes a test for above in X86.

Differential Revision: https://reviews.llvm.org/D102096
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
Commit 8d37411e48202b490c62ee3548df4b90f5974e12 by stefanp
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"

This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
Breaks PowerPC Big Endian buildbots.
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
Commit 44e0e91db01abb9de1868f5acf3ff4f2648b8fc0 by craig.topper
[ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements()

getVectorNumElements() returns a value for scalable vectors
without any warning so it is effectively getVectorMinNumElements().
By renaming it and making getVectorNumElements() forward to
it, we can insert a check for scalable vectors into getVectorNumElements()
similar to EVT. I didn't do that in this patch because there are still more
fixes needed, but I was able to temporarily do it and passed the RISCV
lit tests with these changes.

The changes to isPow2VectorType and getPow2VectorType are copied from EVT.

The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table.
We're now considering SameNumElts to require the scalable property to match which
removes some unneeded type checks.

This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8

Reviewed By: frasercrmck, sdesmalen

Differential Revision: https://reviews.llvm.org/D102262
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Commit 98575708da9544ccab8939fece9c3d638a32f09f by Yaxun.Liu
[CUDA][HIP] Fix device template variables

Currently clang does not emit device template variables
instantiated only in host functions, however, nvcc is
able to do that:

https://godbolt.org/z/fneEfferY

This patch fixes this issue by refactoring and extending
the existing mechanism for emitting static device
var ODR-used by host only. Basically clang records
device variables ODR-used by host code and force
them to be emitted in device compilation. The existing
mechanism makes sure these device variables ODR-used
by host code are added to llvm.compiler-used, therefore
they are guaranteed not to be deleted.

It also fixes non-ODR-use of static device variable by host code
causing static device variable to be emitted and registered,
which should not.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D102237
The file was modifiedclang/test/CodeGenCUDA/device-stub.cu
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGenCUDA/static-device-var-rdc.cu
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/test/CodeGenCUDA/static-device-var-no-rdc.cu
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/CodeGenCUDA/host-used-device-var.cu
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 1336c5ae2fea48bcb54a5050a01b59333fd502aa by rupprecht
[llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility.

Much like other LLVM binary utilities, `llvm-cov` has a symlink compatibility feature where it runs in `gcov` compatibility mode if the binary name ends in `gcov`. This is identical to invoking `llvm-cov gcov ...`.

Differential Revision: https://reviews.llvm.org/D102299
The file was addedllvm/test/tools/llvm-cov/tool-name.test
Commit 58d18dde5cca3417e3d52670775c95d2f6fe9d05 by anastasia.stulova
[OpenCL] Remove pragma requirement from Arm dot extension.

This removed the pointless need for extension pragma since
it doesn't disable anything properly and it doesn't need to
enable anything that is not possible to disable.

The change doesn't break existing kernels since it allows to
compile more cases i.e. without pragma statements but the
pragma continues to be accepted.

Differential Revision: https://reviews.llvm.org/D100985
The file was modifiedclang/lib/Headers/opencl-c.h
The file was modifiedclang/test/SemaOpenCL/arm-integer-dot-product.cl
The file was modifiedclang/test/CodeGenOpenCL/arm-integer-dot-product.cl
Commit 6110b667b0537104ee139a5c6efc726f902db4de by clementval
[mlir][openacc] Conversion of data operand to LLVM IR dialect

Add a conversion pass to convert higher-level type before translation.
This conversion extract meangingful information and pack it into a struct that
the translation (D101504) will be able to understand.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D102170
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was addedmlir/include/mlir/Conversion/OpenACCToLLVM/ConvertOpenACCToLLVM.h
The file was addedmlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp
The file was addedmlir/lib/Conversion/OpenACCToLLVM/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was addedmlir/test/Conversion/OpenACCToLLVM/convert-standalone-data-to-llvmir.mlir
Commit c5ec00e62b0e7b91eb07e25441c7ed38227f5bf3 by fraser
[TargetLowering] Improve legalization of scalable vector types

This patch extends the vector type-conversion and legalization capabilities of
scalable vector types.

Firstly, `vscale x 1` types now behave more like the corresponding `vscale x
2+` types. This enables the integer promotion legalization of extended scalable
types, such as the promotion of `<vscale x 1 x i5>` to `<vscale x 1 x i8>`.

These `vscale x 1` types are also now better handled by
`getVectorTypeBreakdown`, where what looks like older handling for 1-element
fixed-length vector types was spuriously updated to include scalable types.

Widening of scalable types is now better supported, by using `INSERT_SUBVECTOR`
to insert the smaller scalable vector "value" type into the wider scalable
vector "part" type. This allows AArch64 to pass and return `vscale x 1` types
by value by widening.

There are still cases where we are unable to legalize `vscale x 1` types, such
as where expansion would require splitting the vector in two.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D102073
The file was addedllvm/test/CodeGen/AArch64/sve-widen-scalable-vectortype.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
Commit 778562ada39f5353b735c4ac204eddedb072a94b by llvm-dev
[X86][AVX] Add v4i64 shift-by-32 tests

AVX1 could perform this as a v8f32 shuffle instead of splitting - based off PR46621
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-256.ll
Commit 7bff9bdd34d53a660f80eb1cdc9da885fd2702e1 by llvm-dev
[X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI.

Pull out repeated code to create a concat_vectors of the same operand from all subvecs.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 47a11a97d0c28e6b1235907780c998f141497e0a by paul.robinson
Fix grammar in README.md
The file was modifiedREADME.md
Commit 5885f1a4cb0bec91ea106e4f300c860c8d061d56 by baptiste.saleil
[AMDGPU] Disable the SIFormMemoryClauses pass at -O1

This patch disables the SIFormMemoryClauses pass at -O1. This pass has a
significant impact on compilation time, so we only want it to be enabled
starting from -O2.

Differential Revision: https://reviews.llvm.org/D101939
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit cf4610d27bbb5c3a744374440e2fdf77caa12040 by wei.huang
[PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
Commit 33f908c42881fa02963f0c64f8be5088717664cc by fabian
[MLIR] Factor pass timing out into a dedicated timing manager

This factors out the pass timing code into a separate `TimingManager`
that can be plugged into the `PassManager` from the outside. Users are
able to provide their own implementation of this manager, and use it to
time additional code paths outside of the pass manager. Also allows for
multiple `PassManager`s to run and contribute to a single timing report.

More specifically, moves most of the existing infrastructure in
`Pass/PassTiming.cpp` into a new `Support/Timing.cpp` file and adds a
public interface in `Support/Timing.h`. The `PassTiming` instrumentation
becomes a wrapper around the new timing infrastructure which adapts the
instrumentation callbacks to the new timers.

Reviewed By: rriddle, lattner

Differential Revision: https://reviews.llvm.org/D100647
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was addedmlir/include/mlir/Support/Timing.h
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was modifiedmlir/lib/Support/MlirOptMain.cpp
The file was modifiedmlir/include/mlir/Pass/Pass.h
The file was modifiedmlir/lib/Pass/PassTiming.cpp
The file was addedmlir/lib/Support/Timing.cpp
The file was modifiedmlir/test/Pass/pass-timing.mlir
The file was modifiedmlir/lib/Pass/PassManagerOptions.cpp
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/test/Pass/pipeline-parsing.mlir
The file was modifiedmlir/docs/PassManagement.md
Commit 5389a05836e74e3acab6dbda7e80ea43e3bc6304 by malcolm.parsons
[docs] Fix documentation for bugprone-dangling-handle

string_view isn't experimental anymore.
This check has always handled both forms.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D102313
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/bugprone-dangling-handle.rst
Commit cbed6e5b2ff026e4d64de8f6ee19bc902b6e0e23 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix warning caused by umask returning a signed integer type

On z/OS, umask() returns an int because mode_t is type int, however it is being compared to an unsigned int. This patch fixes the following warning we see when compiling Path.cpp.

```
comparison of integers of different signs: 'const int' and 'const unsigned int'
```

Reviewed By: muiez

Differential Revision: https://reviews.llvm.org/D102326
The file was modifiedllvm/unittests/Support/Path.cpp
Commit 9934571eab9c6b3be22c4c8857bd3f4280b77843 by jonathanchesterfield
[libomptarget][amdgpu][nfc] Expand errorcheck macros

[libomptarget][amdgpu][nfc] Expand errorcheck macros

These macros expand to continue, which is confusing, or exit,
which is incompatible with continuing execution on offloading fail.

Expanding the macros in place makes the code look untidy but the
control flow obvious and amenable to improving. In particular, exit
becomes easier to eliminate.

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D102230
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
Commit 93c8559baf551a7a30ab17654569ac5ac92986f4 by gkm
[lld-macho] Implement branch-range-extension thunks

Extend the range of calls beyond an architecture's limited branch range by first calling a thunk, which loads the far address into a scratch register (x16 on ARM64) and branches through it.

Other ports (COFF, ELF) use multiple passes with successively-refined guesses regarding the expansion of text-space imposed by thunk-space overhead. This MachO algorithm places thunks during MergedOutputSection::finalize() in a single pass using exact thunk-space overheads. Thunks are kept in a separate vector to avoid the overhead of inserting into the `inputs` vector of `MergedOutputSection`.

FIXME:
* arm64-stubs.s test is broken
* add thunk tests
* Handle thunks to DylibSymbol in MergedOutputSection::finalize()

Differential Revision: https://reviews.llvm.org/D100818
The file was modifiedlld/MachO/Symbols.cpp
The file was modifiedlld/MachO/InputSection.h
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/InputSection.cpp
The file was modifiedlld/MachO/SyntheticSections.h
The file was addedlld/test/MachO/tools/generate-thunkable-program.py
The file was modifiedlld/MachO/Arch/ARM64.cpp
The file was addedlld/test/MachO/arm64-thunks.s
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/MergedOutputSection.cpp
The file was modifiedlld/MachO/Target.h
The file was modifiedlld/MachO/MergedOutputSection.h
The file was modifiedlld/MachO/Symbols.h
Commit dc8d16c03f4fcdc0dbfc2925621f6d0064bca31c by Amara Emerson
[AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting.

This caused performance regressions vs SDAG on SingleSource/Benchmarks/Adobe-C++
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit ca5d0a7310bfb21730ac6dd735e06502e7e45099 by ajcbik
[mlir][sparse] keep runtime support library signature consistent

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102285
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
Commit fb1d61b7257ccd5ba0c96bcea78d6516384ce5b6 by llvm-dev
[X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621)

On AVX1 targets we can handle v4i64 logical shifts by 32 bits as a pair of v8f32 shuffles with zero.

I was hoping to put this in LowerScalarImmediateShift, but performing that early causes regressions where other instructions were respliting the subvectors.
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
Commit 5480ea6c84633b7a5548cfe48fc09c6b57cecfb9 by hanchung
Update static bound checker for Linalg to cover decreasing cases

The current static checker for linalg does not work on the decreasing
index cases well. So, this is to Update the current static bound checker
for linalg to cover decreasing index cases.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D102302
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
Commit 3bf1acab5b454ad7fb2074b34663108b53620695 by i
[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions

llvm-dev message: https://lists.llvm.org/pipermail/llvm-dev/2021-May/150465.html

In an ELF shared object, a default visibility defined symbol is preemptible by default.
This creates some missed optimization opportunities. -fno-semantic-interposition can optimize -fPIC:

* in Clang: avoid GOT/PLT cost for variable access/function calls to external linkage definition in the same TU
* in GCC: enable interprocedural optimizations (including inlining) and avoid PLT

See https://gist.github.com/MaskRay/2d4dfcfc897341163f734afb59f689c6 for more information.

-Bsymbolic-functions is more aggressive than -fvisibility-inlines-hidden (present since 2012) as it applies
to all function definitions.  It can

* avoid PLT for cross-TU function calls && reduce dynamic symbol lookup
* reduce dynamic symbol lookup for taking function addresses and optimize out GOT/TOC on x86-64/ppc64

With both options, the libLLVM.so and libclang-cpp.so performance should
be closer to PIE binary linking against `libLLVM*.a` and `libclang*.a`

(In a -DLLVM_TARGETS_TO_BUILD=X86 build, the number of JUMP_SLOT decreases from 12716 to 1628, and the number of GLOB_DAT decreases from 1918 to 1313
The built clang with `-DLLVM_LINK_LLVM_DYLIB=on -DCLANG_LINK_CLANG_DYLIB=on` is significantly faster.
See the Linux kernel build result https://bugs.archlinux.org/task/70697
)

Some implication:

Interposing a subset of functions is no longer supported.
(This is fragile anyway and cannot really be supported. For Mach-O we don't use
`ld -interpose`, so interposition is not supported on Mach-O at all.)

Compiling a program which takes the address of any LLVM function with
`{gcc,clang} -fno-pic` and expects the address to equal to the address taken
from libLLVM.so or libclang-cpp.so is unsupported. I am fairly confident that
llvm-project shouldn't have different behaviors depending on such pointer
equality (as we've been using -fvisibility-inlines-hidden which applies to
inline functions for a long time), but if we accidentally do, users should be
aware that they should not make assumption on pointer equality in `-fno-pic`
mode.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D102090
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit 0fe6649bc5b1824e87e418b2b18f61c1ed1025ce by i
[X86] Fix -Wunused-lambda-capture
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2d84195d60b0cb5ea43b18ab8f6770a84bf32da4 by lebedev.ri
[NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl

It does the same thing.
Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
Commit 81f56a2eb3797eb5be61d65a8f7d7e19456e67d1 by lebedev.ri
[NFC][clang][Codegen] Split ThunkInfo into it's own header

Otherwise we'll have issues with forward definition of GlobalDecl.

Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was addedclang/include/clang/Basic/Thunk.h
The file was modifiedclang/include/clang/AST/VTableBuilder.h
The file was modifiedclang/include/clang/Basic/ABI.h
Commit 113b807017847f7d9e79db724f09968b51459cf0 by clementval
[mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin)

This patch begins to translate acc.enter_data operation to call to tgt runtime call.
It currently only translate create/copyin operands of memref type. This acts as a basis to add support
for FIR types in the Flang/OpenACC support. It follows more or less a similar path than clang
with `omp target enter data map` directives.
This patch is taking a different approach than D100678 and perform a translation to LLVM IR
and make use of the OpenMPIRBuilder instead of doing a conversion to the LLVMIR dialect.

OpenACC support in Flang will rely on the current OpenMP runtime where 1:1 lowering can be
applied. Some extension will be added where features are not available yet.

Big part of this code will be shared for other standalone data operations in the OpenACC
dialect such as acc.exit_data and acc.update.

It is likely that parts of the lowering can also be shared later with the ops for
standalone data directives in the OpenMP dialect when they are introduced.

This is an initial translation and it probably needs more work.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D101504
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
The file was addedmlir/test/Target/LLVMIR/openacc-llvm.mlir
The file was modifiedmlir/lib/Target/LLVMIR/CMakeLists.txt
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/All.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h