Changes

Summary

  1. [PowerPC] Removed `-DLLVM_ENABLE_PROJECTS=flang` from PowerPC flang buildbot (details)
Commit 4adb6aa495ee9484d7f2e15c93e7685bdc603cc7 by albionapc
[PowerPC] Removed `-DLLVM_ENABLE_PROJECTS=flang` from PowerPC flang buildbot

With `FLANG_NEW_DRIVER` default to on now, it is necessary to remove this
option for the bot to be able to build again.

Differential Revision: https://reviews.llvm.org/D102626
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [ARM][NEON] Combine base address updates for vst1x intrinsics (details)
  2. Remove scalable vector assert from InnerLoopVectorizer::setDebugLocFromInst (details)
  3. Revert "[X86] Limit X86InterleavedAccessGroup to handle the same type case only" (details)
  4. [mlir][Vector] NFC - Drop vector EDSC usage (details)
  5. [llvm][AArch64][SVE] Model FFR-using intrinsics with inaccessiblemem (details)
  6. Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" (details)
  7. [lldb][NFC] Remove sample test boilerplate from TestBreakOnCPP11Initializers (details)
  8. [lldb] Encode `bool` as unsigned int (details)
  9. [mir][Python][linalg] Support OpDSL extensions in C++. (details)
  10. [X86][Atom] Fix vector integer shift by immediate resource/throughputs (details)
  11. [X86][AVX] createVariablePermute - generalize the PR50356 fix for smaller indices vector as well (details)
  12. [nfc] [lldb] 1/2: Fix DW_AT_ranges DW_FORM_sec_offset not using DW_AT_rnglists_base (used by GCC) (details)
  13. [lldb] 2/2: Fix DW_AT_ranges DW_FORM_sec_offset not using DW_AT_rnglists_base (used by GCC) (details)
  14. Revert rG528bc10e95d5f9d6a338f9bab5e91d7265d1cf05 : "[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB" (details)
  15. Reapply "[X86] Limit X86InterleavedAccessGroup to handle the same type case only" (details)
  16. [clang][patch] Add support for option -fextend-arguments={32,64}: widen integer arguments to int64 in unprototyped function calls (details)
  17. [lldb] Enable TestCppBitfields on Windows (details)
  18. [AsmParser][SystemZ][z/OS] Introducing HLASM Parser support to AsmParser - Part 1 (details)
  19. [VP] make getFunctionalOpcode return an Optional (details)
  20. Fix lld macho standalone build by including llvm/Config/llvm-config.h instead of llvm/Config/config.h (details)
  21. [mlir][SCF] NFC - Drop SCF EDSC usage (details)
  22. Revert "Do actual DCE in LoopUnroll (try 3)" (details)
Commit d59a2a32b942ffb0decef5370eec98b8eba99c11 by kbessonova
[ARM][NEON] Combine base address updates for vst1x intrinsics

Differential Revision: https://reviews.llvm.org/D102256
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/ARM/arm-vst1.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrNEON.td
Commit 7e95a563c89dc158217e2032b716e5be77677846 by david.sherwood
Remove scalable vector assert from InnerLoopVectorizer::setDebugLocFromInst

In InnerLoopVectorizer::setDebugLocFromInst we were previously
asserting that the VF is not scalable. This is because we want to
use the number of elements to create a duplication factor for the
debug profiling data. However, for scalable vectors we only know the
minimum number of elements. I've simply removed the assert for now
and added a FIXME saying that we assume vscale is always 1. When
vscale is not 1 it just means that the profiling data isn't as
accurate, but shouldn't cause any functional problems.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 66513e2f20d9885374d0df43a89fc768523d6354 by pengfei.wang
Revert "[X86] Limit X86InterleavedAccessGroup to handle the same type case only"

This reverts commit ca23a38e373142a18ab56700ba4f3b947bfe9db0.

Revert due to EXPENSIVE_CHECKS fail.
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit 6825bfe23e3829c81574e7d5d41887ca2dae4bef by nicolas.vasilache
[mlir][Vector] NFC - Drop vector EDSC usage

Drop the vector dialect EDSC subdirectory and update all uses.
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was removedmlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was removedmlir/test/EDSC/builder-api-test.cpp
The file was modifiedmlir/lib/Dialect/Vector/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was removedmlir/test/EDSC/lit.local.cfg
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was removedmlir/test/EDSC/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
The file was removedmlir/include/mlir/Dialect/Vector/EDSC/Builders.h
The file was removedmlir/lib/Dialect/Vector/EDSC/Builders.cpp
The file was modifiedmlir/test/CMakeLists.txt
Commit fd4ef793ea54e5730838998863fea5484fcba541 by peter.waller
[llvm][AArch64][SVE] Model FFR-using intrinsics with inaccessiblemem

Intriniscs reading or writing the FFR register need to model the fact
there is additional state being read/wrtten.

Model this state as inaccessible memory.

* setffr => write inaccessiblememonly
* rdffr => read inaccessiblememonly
* ldff* => read arg memory, write inaccessiblemem
* ldnf => read arg memory, write inaccessiblemem
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
Commit 52a779762688dee1a6042dc41f35e1f7a7048b85 by thakis
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known"

This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304.
Breaks tests, see comments on https://reviews.llvm.org/D102542
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
Commit ff954865137cdd11165340e2c9537cfd1b3f805d by Raphael Isemann
[lldb][NFC] Remove sample test boilerplate from TestBreakOnCPP11Initializers
The file was modifiedlldb/test/API/lang/cpp/break-on-initializers/TestBreakOnCPP11Initializers.py
The file was modifiedlldb/test/API/lang/cpp/break-on-initializers/main.cpp
Commit 0bab7b26f4d9dc4cb8f6c2877ad4a2c388c41c65 by weratt
[lldb] Encode `bool` as unsigned int

`bool` is considered to be unsigned according to `std::is_unsigned<bool>::value` (and `Type::GetTypeInfo`). Encoding it as signed int works fine for normal variables and fields, but breaks when reading the values of boolean bitfields. If the field is declared as `bool b : 1` and has a value of `0b1`, the call to `SBValue::GetValueAsSigned()` will return `-1`.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D102685
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/test/API/lang/cpp/bitfields/TestCppBitfields.py
The file was modifiedlldb/test/API/lang/cpp/bitfields/main.cpp
Commit 9a2769db801d4c45edb939223abfb3e1a639732f by gysit
[mir][Python][linalg] Support OpDSL extensions in C++.

The patch extends the yaml code generation to support the following new OpDSL constructs:
- captures
- constants
- iteration index accesses
- predefined types
These changes have been introduced by revision
https://reviews.llvm.org/D101364.

Differential Revision: https://reviews.llvm.org/D102075
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/config.py
The file was modifiedmlir/test/CMakeLists.txt
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/scalar_expr.py
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/assignments.py
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was addedmlir/test/python/dialects/linalg/opdsl/arguments.py
The file was addedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-yaml-gen.yaml
The file was modifiedmlir/test/python/dialects/linalg/opsrun.py
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/emit_structured_generic.py
The file was modifiedmlir/test/Dialect/Linalg/generalize-named-polymorphic-ops.mlir
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/emitter.py
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
Commit b14f9a1ebd7bb5ce9190990c07304befd6eff2ca by llvm-dev
[X86][Atom] Fix vector integer shift by immediate resource/throughputs

Match whats documented in the Intel AOM (and Agner/instlatx64 agree) - these are all Port0 only.

Now that we can use in-order models in llvm-mca, the atom model is a good "worst case scenario" analysis for x86.
The file was modifiedllvm/test/tools/llvm-mca/X86/Atom/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Atom/resources-mmx.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleAtom.td
Commit ab4e04a0f31ae187f67991980e707ff70bbc6285 by llvm-dev
[X86][AVX] createVariablePermute - generalize the PR50356 fix for smaller indices vector as well

Generalize the fix from rGd0902a8665b1 by ensuring we widen/narrow the indices subvector first and then perform the ZERO_EXTEND_VECTOR_INREG (if necessary), which should allow us to perform the variable permutes with source/destination/indices vectors of any widths.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/var-permute-256.ll
Commit 9dd861a4f53968c732531de5d4488ace20d6d075 by jan.kratochvil
[nfc] [lldb] 1/2: Fix DW_AT_ranges DW_FORM_sec_offset not using DW_AT_rnglists_base (used by GCC)

Refactor code only for D98289.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D99653
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
Commit d1310817194aad488c86f4fb627c33090600a4a9 by jan.kratochvil
[lldb] 2/2: Fix DW_AT_ranges DW_FORM_sec_offset not using DW_AT_rnglists_base (used by GCC)

DW_AT_ranges can use DW_FORM_sec_offset (instead of DW_FORM_rnglistx).
In such case DW_AT_rnglists_base does not need to be present.
DWARF-5 spec:
        "If the offset_entry_count is zero, then DW_FORM_rnglistx cannot
        be used to access a range list; DW_FORM_sec_offset must be used
        instead. If the offset_entry_count is non-zero, then
        DW_FORM_rnglistx may be used to access a range list;"

This fix is for TestTypeCompletion.py category `dwarf` using GCC with DWARF-5.

The fix just provides GetRnglist() lazy getter for `m_rnglist_table`.
The testcase is easier to review by:
        diff -u lldb/test/Shell/SymbolFile/DWARF/DW_AT_low_pc-addrx.s \
          lldb/test/Shell/SymbolFile/DWARF/DW_AT_range-DW_FORM_sec_offset.s

Differential Revision: https://reviews.llvm.org/D98289
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was addedlldb/test/Shell/SymbolFile/DWARF/DW_AT_range-DW_FORM_sec_offset.s
Commit 707fc2e2f227ec7b367273d0906b953bbae41392 by llvm-dev
Revert rG528bc10e95d5f9d6a338f9bab5e91d7265d1cf05 : "[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB"

Reports on D101970 indicate this is causing failures on multi-stage compiles.
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
The file was modifiedllvm/test/CodeGen/X86/lea-opt2.ll
The file was modifiedllvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/lib/Target/X86/X86FixupLEAs.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
Commit 9d09d20448e48c78035c40982646b7b26fee88c3 by pengfei.wang
Reapply "[X86] Limit X86InterleavedAccessGroup to handle the same type case only"

The current implementation assumes the destination type of shuffle is the same as the decomposed ones. Add the check to avoid crush when the condition is not satisfied.

This fixes PR37616.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D102751
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp
Commit d30dfa86760ced9ac57f676340b34f2247898102 by melanie.blower
[clang][patch] Add support for option -fextend-arguments={32,64}: widen integer arguments to int64 in unprototyped function calls

Reviewed By: Aaron Ballman

Differential Revision: https://reviews.llvm.org/D101640
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was addedclang/test/CodeGen/extend-arg-64.c
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedclang/test/Driver/fextend-args.c
Commit 6c83d4a60b7d243f0674f4381ec72b7c8ec4f2be by weratt
[lldb] Enable TestCppBitfields on Windows

The test works correctly on Windows, the linked bug has been resolved.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D102769
The file was modifiedlldb/test/API/lang/cpp/bitfields/TestCppBitfields.py
Commit f076da66b9d3c721611de36e43ac1da1607d1abf by anirudh_prasad
[AsmParser][SystemZ][z/OS] Introducing HLASM Parser support to AsmParser - Part 1

- This patch (is one in a series of patches) which introduces HLASM Parser support (for the first parameter of inline asm statements) to LLVM ([[ https://lists.llvm.org/pipermail/llvm-dev/2021-January/147686.html | main RFC here ]])
- This patch in particular introduces HLASM Parser support for Z machine instructions.
- The approach taken here was to subclass `AsmParser`, and make various functions and variables as "protected" wherever appropriate.
- The `HLASMAsmParser` class overrides the `parseStatement` function. Two new private functions `parseAsHLASMLabel` and `parseAsMachineInstruction` are introduced as well.

The general syntax is laid out as follows (more information available in [[ https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf | HLASM V1R6 Language Reference Manual ]] - Chapter 2 - Instruction Statement Format):

```
<TokA><spaces.*><TokB><spaces.*><TokC><spaces.*><TokD>
```

1. TokA is referred to as the Name Entry. This token is optional
2. TokB is referred to as the Operation Entry. This token is mandatory.
3. TokC is referred to as the Operand Entry. This token is mandatory
4. TokD is referred to as the Remarks Entry. This token is optional

- If TokA is provided, then we either parse TokA as a possible comment or as a label (Name Entry), Tok B as the Operation Entry and so on.
- If TokA is not provided (i.e. we have one or more spaces and then the first token), then we will parse the first token (i.e TokB) as a possible Z machine instruction, TokC as the operands to the Z machine instruction and TokD as a possible Remark field
- TokC (Operand Entry), no spaces are allowed between OperandEntries. If a space occurs it is classified as an error.
- TokD if provided is taken as is, and emitted as a comment.

The following additional approach was examined, but not taken:

- Adding custom private only functions to base AsmParser class, and only invoking them for z/OS. While this would eliminate the need for another child class, these private functions would be of non-use to every other target. Similarly, adding any pure virtual functions to the base MCAsmParser class and overriding them in AsmParser would also have the same disadvantage.

Testing:

- This patch doesn't have tests added with it, for the sole reason that MCStreamer Support and Object File support hasn't been added for the z/OS target (yet). Hence, it's not possible generate code outright for the z/OS target. They are in the process of being committed / process of being worked on.

- Any comments / feedback on how to combat this "lack of testing" due to other missing required features is appreciated.

Reviewed By: Kai, uweigand

Differential Revision: https://reviews.llvm.org/D98276
The file was modifiedllvm/include/llvm/MC/MCAsmInfo.h
The file was modifiedllvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Commit 66963bf3819df4f47bd874a946af058f0c1c4ec0 by simon.moll
[VP] make getFunctionalOpcode return an Optional

The operation of some VP intrinsics do/will not map to regular
instruction opcodes.  Returning 'None' seems more intuitive here than
'Instruction::Call'.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102778
The file was modifiedllvm/lib/IR/IntrinsicInst.cpp
The file was modifiedllvm/lib/CodeGen/ExpandVectorPredication.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicInst.h
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
Commit 9383e9c1e627b49cc1c80c2e6117132734a2fba8 by thakis
Fix lld macho standalone build by including llvm/Config/llvm-config.h instead of llvm/Config/config.h

lld/MachO/Driver.cpp and lld/MachO/SyntheticSections.cpp include
llvm/Config/config.h which doesn't exist when building standalone lld.

This patch replaces llvm/Config/config.h include with llvm/Config/llvm-config.h
just like it is in lld/ELF/Driver.cpp and HAVE_LIBXAR with LLVM_HAVE_LIXAR and
moves LLVM_HAVE_LIBXAR from config.h to llvm-config.h

Also it adds LLVM_HAVE_LIBXAR to LLVMConfig.cmake and links liblldMachO2.so
with XAR_LIB if LLVM_HAVE_LIBXAR is set.

Differential Revision: https://reviews.llvm.org/D102084
The file was modifiedlld/CMakeLists.txt
The file was modifiedlld/test/lit.site.cfg.py.in
The file was modifiedllvm/cmake/modules/LLVMConfig.cmake.in
The file was modifiedlld/test/CMakeLists.txt
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedllvm/tools/llvm-objdump/CMakeLists.txt
The file was modifiedlld/MachO/CMakeLists.txt
The file was modifiedlld/tools/lld/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn
The file was modifiedllvm/test/lit.site.cfg.py.in
The file was modifiedllvm/include/llvm/Config/config.h.cmake
The file was modifiedllvm/cmake/config-ix.cmake
The file was modifiedllvm/include/llvm/Config/llvm-config.h.cmake
The file was modifiedllvm/test/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedlld/MachO/Driver.cpp
Commit 84a880e1e23ebc2ca60e6e1f9e8d0d8db3f9a036 by nicolas.vasilache
[mlir][SCF] NFC - Drop SCF EDSC usage

Drop the SCF dialect EDSC subdirectory and update all uses.

Differential Revision: https://reviews.llvm.org/D102780
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was removedmlir/include/mlir/Dialect/SCF/EDSC/Builders.h
The file was modifiedmlir/include/mlir/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was removedmlir/include/mlir/Dialect/SCF/EDSC/Intrinsics.h
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
The file was modifiedmlir/lib/Dialect/SCF/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Intrinsics.h
The file was removedmlir/lib/Dialect/SCF/EDSC/Builders.cpp
The file was modifiedmlir/include/mlir/Dialect/MemRef/EDSC/Intrinsics.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Builders.h
The file was modifiedmlir/test/Dialect/Linalg/affine.mlir
The file was modifiedmlir/lib/Dialect/Linalg/EDSC/Builders.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
Commit 517857421d2ffcebc20da2c68862f7a2ddebaa51 by akhuang
Revert "Do actual DCE in LoopUnroll (try 3)"

This reverts commit b6320eeb8622f05e4a5d4c7f5420523357490fca
as it causes clang to assert; see
https://reviews.llvm.org/rGb6320eeb8622f05e4a5d4c7f5420523357490fca.
The file was modifiedllvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/AArch64/full-unroll-trip-count-upper-bound.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/pr45939-peel-count-and-complete-unroll.ll
The file was removedllvm/test/Transforms/LoopUnroll/dce.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/scevunroll.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll

Summary

  1. [PowerPC] Removed `-DLLVM_ENABLE_PROJECTS=flang` from PowerPC flang buildbot (details)
Commit 4adb6aa495ee9484d7f2e15c93e7685bdc603cc7 by albionapc
[PowerPC] Removed `-DLLVM_ENABLE_PROJECTS=flang` from PowerPC flang buildbot

With `FLANG_NEW_DRIVER` default to on now, it is necessary to remove this
option for the bot to be able to build again.

Differential Revision: https://reviews.llvm.org/D102626
The file was modifiedbuildbot/osuosl/master/config/builders.py