AbortedChanges

Summary

  1. [mlir][docs] Fix links to index and integer types (details)
  2. [CostModel][X86] Improve fneg costs (details)
  3. [X86] Inline variable to avoid unused warning in Release builds. NFCI. (details)
  4. Revert "[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass" (details)
  5. [NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator (details)
  6. [CostModel][X86] Improve f64/v2f64/v4f64 FMUL costs on AVX1 targets to account for slower btver2 (details)
  7. [ORC] Use GTEST_SKIP in ORC C-API unit test. (details)
  8. [ORC-RT] Add missing headers to CMakeLists.txt. (details)
Commit b3127c94dddf6abb03dcf6abac272dbb52827c52 by marius.brehler
[mlir][docs] Fix links to index and integer types

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102922
The file was modifiedmlir/docs/Tutorials/Toy/Ch-7.md
The file was modifiedmlir/docs/Tutorials/DefiningAttributesAndTypes.md
The file was modifiedmlir/docs/Dialects/SPIR-V.md
The file was modifiedmlir/docs/Dialects/Affine.md
Commit 2fca5558660e227d7e35923ddb229a47a8ea1f69 by llvm-dev
[CostModel][X86] Improve fneg costs

These are always lowered as xor ops, so are always cheap
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fp.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/fneg-cost.ll
Commit ea438b489828f717db9bb5433863854c1f61c7d7 by benny.kra
[X86] Inline variable to avoid unused warning in Release builds. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
Commit fd53cb414813444cf232903acfe7a9ddc72b5f21 by konndennsa
Revert "[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass"

This reverts commit cea7a3fe3d1fc91a00cb54cee3ac6f361343417e.
To investigate sanitizer-x86_64-linux-fast failure.
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/innerloop.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
Commit 355114a7532d9beb53bce792effd81d6064aa85b by Tony.Tye
[NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator

Add link to documentation for "AMD Instinct MI100 Instruction Set
Architecture" to AMDGPUUsage.rst.

Reviewed By: kzhuravl, rampitec, dp

Differential Revision: https://reviews.llvm.org/D102859
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit fe6c11c5710e95eedbb16c2aac58a5d992e55434 by llvm-dev
[CostModel][X86] Improve f64/v2f64/v4f64 FMUL costs on AVX1 targets to account for slower btver2

BTVER2 has a weaker f64 multiplier that other AVX1-era targets, so we need to bump the worst case cost slightly - llvm-mca reports the new vectorization in simplebb is beneficial on btver2, bdver2 and sandybridge AVX1 targets
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fp.ll
Commit 95612afc1d69ff470943b10210bb902fa14fc4e8 by Lang Hames
[ORC] Use GTEST_SKIP in ORC C-API unit test.

Now that gtest has been updated to 1.10 which supports GTEST_SKIP, we can use
that over return;

Patch by Mats Larsen. Thanks Mats!

Reviewed By: lhames, ikudrin

Differential Revision: https://reviews.llvm.org/D102710
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
Commit 16b284e99e4bca8d1e571310f545f10512dc979b by Lang Hames
[ORC-RT] Add missing headers to CMakeLists.txt.
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt