AbortedChanges

Summary

  1. [analyzer] Correctly propagate ConstructionContextLayer thru ParenExpr (details)
  2. [VectorCombine] Scalarize vector load/extract. (details)
  3. [Debug-Info]update section name to match AIX behaviour; nfc (details)
  4. [AMDGPU][Libomptarget] Remove global KernelNameMap (details)
  5. [CostModel][X86] Improve accuracy of vXi64 MUL costs on AVX2/AVX512 targets (details)
  6. Revert "[VectorCombine] Scalarize vector load/extract." (details)
  7. flang: include limits (details)
  8. [LoopIdiom] 'logical right shift until zero': the value must be loop-invariant (details)
  9. [NFCI][LoopIdiom] 'left-shift until bittest': assert that BaseX is loop-invariant (details)
  10. [debuginfo-tests] Stop using installed LLDB and remove redundancy (details)
  11. [RISCV] Prevent store combining from infinitely looping (details)
  12. [MLIR] Drop old cmake var names (details)
  13. [ARM] Fix inline memcpy trip count sequence (details)
  14. [ARM] Ensure WLS preheader blocks have branches during memcpy lowering (details)
  15. Recommit "[VectorCombine] Scalarize vector load/extract." (details)
  16. [ARM] Allow findLoopPreheader to return headers with multiple loop successors (details)
  17. [OpenCL] Add clang extension for bit-fields. (details)
  18. [AArch64][SVE] Improve codegen for fixed length vector concat (details)
  19. [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND (details)
  20. [OpenCL] Fix test by adding SPIR triple (details)
  21. [VPlan] Add mayReadOrWriteMemory & friends. (details)
  22. [VectorCombine] Fix load extract scalarization tests with assumes. (details)
Commit 058f384ae94ae0ac94441043804e4a25d338d483 by balazs.benics
[analyzer] Correctly propagate ConstructionContextLayer thru ParenExpr

Previously, information about `ConstructionContextLayer` was not
propagated thru causing the expression like:

  Var c = (createVar());

To produce unrelated temporary for the `createVar()` result and conjure
a new symbol for the value of `c` in C++17 mode.

Reviewed By: steakhal

Patch By: tomasz-kaminski-sonarsource!

Differential Revision: https://reviews.llvm.org/D102835
The file was modifiedclang/lib/Analysis/CFG.cpp
The file was modifiedclang/test/Analysis/Inputs/expected-plists/NewDelete-path-notes.cpp.plist
The file was modifiedclang/test/Analysis/NewDelete-path-notes.cpp
The file was modifiedclang/test/Analysis/NewDeleteLeaks-PR19102.cpp
The file was modifiedclang/test/Analysis/NewDelete-checker-test.cpp
Commit 86497785d540e59eaca24bed4219ddec183cbc9b by flo
[VectorCombine] Scalarize vector load/extract.

This patch adds a new combine that tries to scalarize chains of
`extractelement (load %ptr), %idx` to `load (gep %ptr, %idx)`. This is
profitable when extracting only a few elements out of a large vector.

At the moment, `store (extractelement (load %ptr), %idx), %ptr`
operations on large vectors result in huge code in the backend.

This can easily be triggered by using the matrix extension, e.g.
https://clang.godbolt.org/z/qsccPdPf4

This should complement D98240.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D100273
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
Commit 486d6d2b8ef7bd7313d99b5cbfa487c52d75169b by czhengsz
[Debug-Info]update section name to match AIX behaviour; nfc
The file was modifiedllvm/test/DebugInfo/Generic/array.ll
The file was modifiedllvm/test/DebugInfo/Generic/2010-06-29-InlinedFnLocalVar.ll
Commit 486110eb413446dfa835d880bfd1c0d6bbe9f120 by Pushpinder.Singh
[AMDGPU][Libomptarget] Remove global KernelNameMap

KernelNameMap contains entries like "key.kd" => key which clearly
could be replaced by simple logic of removing suffix from the key.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D102691
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
Commit 243e58868176102484c3ff1a338342633ede7361 by llvm-dev
[CostModel][X86] Improve accuracy of vXi64 MUL costs on AVX2/AVX512 targets

By llvm-mca analysis, Haswell/Broadwell has the worst v4i64 recip-throughput cost of the AVX2 targets at 6 (vs the currently used cost of 8). Similarly SkylakeServer (our only AVX512 target model) implements PMULLQ with an average cost of 1.5 (rounded up to 2.0), and the PMULUDQ-sequence (without AVX512DQ) as a cost of 6.
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-overflow.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-mul.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fix.ll
Commit 94d54155e2f38b56171811757044a3e6f643c14b by flo
Revert "[VectorCombine] Scalarize vector load/extract."

This reverts commit 86497785d540e59eaca24bed4219ddec183cbc9b.

One of the tests causes an ASAN failure.
https://lab.llvm.org/buildbot/#/builders/5/builds/7927/steps/12/logs/stdio
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
Commit 0f140ce33d64b2a8f4f0866debf5fdd36e49b3ad by schuett
flang: include limits
The file was modifiedflang/runtime/unit.cpp
Commit aa3dac95edbfb892b6236341b431b222f7bd0926 by lebedev.ri
[LoopIdiom] 'logical right shift until zero': the value must be loop-invariant

As per the reproducer provided by Mikael Holmén in post-commit review.
The file was modifiedllvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Commit 32bee42719ad8f0d8e15b55dd5b2a7563a817e34 by lebedev.ri
[NFCI][LoopIdiom] 'left-shift until bittest': assert that BaseX is loop-invariant

Given that BaseX is an incoming value when coming from the preheader,
it *should* be loop-invariant, but let's just document this assumption.
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Commit 5c4a5daf293c1c924caa3c6faed4487682d70045 by james.henderson
[debuginfo-tests] Stop using installed LLDB and remove redundancy

The removed code just replicated what use_llvm_tool does, plus looked
for an installed LLDB on the PATH to use. In a monorepo world, it seems
likely that if people want to run the tests that require LLDB, they
should enable and build LLDB itself. If users really want to use the
installed LLDB executable, they can specify the path to the executable
as an environment variable "LLDB".

See the discussion in https://reviews.llvm.org/D95339#2638619 for
more details.

Reviewed by: jmorse, aprantl

Differential Revision: https://reviews.llvm.org/D102680
The file was modifieddebuginfo-tests/lit.cfg.py
Commit 7a211ed110a72ad453305aba250da50c965c2f8e by fraser
[RISCV] Prevent store combining from infinitely looping

RVV code generation does not successfully custom-lower BUILD_VECTOR in all
cases. When it resorts to default expansion it may, on occasion, be expanded to
scalar stores through the stack. Unfortunately these stores may then be picked
up by the post-legalization DAGCombiner which merges them again. The merged
store uses a BUILD_VECTOR which is then expanded, and so on.

This patch addresses the issue by overriding the `mergeStoresAfterLegalization`
hook. A lack of granularity in this method (being passed the scalar type) means
we opt out in almost all cases when RVV fixed-length vector support is enabled.
The only exception to this rule are mask vectors, which are always either
custom-lowered or are expanded to a load from a constant pool.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D102913
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 587408c199e8125bb454a44b7a7b20e015f4d317 by uday
[MLIR] Drop old cmake var names

Drop old cmake variable names that were kept around so that zorg
buildbot could be migrated, which has now happened (D102977). D102976
had fixed the inconsistent names.

Differential Revision: https://reviews.llvm.org/D102997
The file was modifiedmlir/CMakeLists.txt
Commit 6cc78b9245bcc0e7a52723e2c298d290284e779b by david.green
[ARM] Fix inline memcpy trip count sequence

The trip count for a memcpy/memset will be n/16 rounded up to the
nearest integer. So (n+15)>>4. The old code was including a BIC too, to
clear one of the bits, which does not seem correct. This remove the
extra BIC.

Note that ideally this would never actually be generated, as in the
creation of a tail predicated loop we will DCE that setup code, letting
the WLSTP perform the trip count calculation. So this doesn't usually
come up in testing (and apparently the ARMLowOverheadLoops pass does not
do any sort of validation on the tripcount). Only if the generation of
the WLTP fails will it use the incorrect BIC instructions.

Differential Revision: https://reviews.llvm.org/D102629
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-phireg.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
Commit 53c42f7700e824d6ec394614653abd8b33d5da34 by david.green
[ARM] Ensure WLS preheader blocks have branches during memcpy lowering

This makes sure that the blocks created for lowering memcpy to loops end
up with branches, even if they fall through to the successor. Otherwise
IfCvt is getting confused with unanalyzable branches and creating
invalid block layouts.

The extra branches should be removed as the tail predicated loop is
finalized in almost all cases.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-memtp-branch.ll
Commit 4e8c28b6fbec95b47c435810ab5fc3b43c2935db by flo
Recommit "[VectorCombine] Scalarize vector load/extract."

This reverts commit 94d54155e2f38b56171811757044a3e6f643c14b.

This fixes a sanitizer failure by moving scalarizeLoadExtract(I)
before foldSingleElementStore(I), which may remove instructions.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
Commit 543406a69b339e875c39c75f3935e27fedefc0a7 by david.green
[ARM] Allow findLoopPreheader to return headers with multiple loop successors

The findLoopPreheader function will currently not find a preheader if it
branches to multiple different loop headers. This patch adds an option
to relax that, allowing ARMLowOverheadLoops to process more loops
successfully. This helps with WhileLoopStart setup instructions that can
branch/fallthrough to the low overhead loop and to branch to a separate
loop from the same preheader (but I don't believe it is possible for
both loops to be low overhead loops).

Differential Revision: https://reviews.llvm.org/D102747
The file was modifiedllvm/lib/CodeGen/MachineLoopInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineLoopInfo.h
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-branch.ll
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit 237c6924bd46ec0e33da71f9616caf9bf9965b23 by anastasia.stulova
[OpenCL] Add clang extension for bit-fields.

Allow use of bit-fields as a clang extension
in OpenCL. The extension can be enabled using
pragma directives.

This fixes PR45339!

Differential Revision: https://reviews.llvm.org/D101843
The file was modifiedclang/test/Misc/r600.languageOptsOpenCL.cl
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Basic/Targets/NVPTX.h
The file was modifiedclang/test/Misc/amdgcn.languageOptsOpenCL.cl
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/lib/Basic/Targets/AMDGPU.h
The file was modifiedclang/test/SemaOpenCL/unsupported.cl
The file was modifiedclang/include/clang/Basic/OpenCLExtensions.def
The file was modifiedclang/test/Misc/nvptx.languageOptsOpenCL.cl
Commit 4bc14be259672257d5c05c58a0ba604002698e93 by bradley.smith
[AArch64][SVE] Improve codegen for fixed length vector concat

Differential Revision: https://reviews.llvm.org/D102498
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit e40513252a2598c2a88366e9466de53edc5a5a51 by bradley.smith
[AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND

Depends on D102498

Differential Revision: https://reviews.llvm.org/D102607
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit 626e9641a2f5fde638b86d4e043f82fc58b908f8 by anastasia.stulova
[OpenCL] Fix test by adding SPIR triple
The file was modifiedclang/test/SemaOpenCL/unsupported.cl
Commit e9d97d7d9d904bc075565197b560e8424ac6a0dc by flo
[VPlan] Add mayReadOrWriteMemory & friends.

This patch adds initial implementation of mayReadOrWriteMemory,
mayReadFromMemory and mayWriteToMemory to VPRecipeBase.

Used by D100258.
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit d251d6f8128bbc38378a69e7fec405f0935a89de by flo
[VectorCombine] Fix load extract scalarization tests with assumes.

The input IR for @load_extract_idx_var_i64_known_valid_by_assume
and @load_extract_idx_var_i64_not_known_valid_by_assume_after_load
has been swapped.

This patch fixes the test so that @load_extract_idx_var_i64_known_valid_by_assume
has the assume before the load and the other test has it after.
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll