SuccessChanges

Summary

  1. [RISCV] Add a test case showing incorrect call-conv lowering (details)
  2. [HIP] Check compatibility of -fgpu-sanitize with offload arch (details)
  3. [mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops. (details)
  4. [SPE] Disable strict-fp for SPE by default (details)
  5. [LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass (details)
  6. [mlir] Async reference counting for block successors with divergent reference counted liveness (details)
  7. [Clang] Enable __has_feature(coverage_sanitizer) (details)
  8. [mlir] Add error state and error propagation to async runtime values (details)
  9. [X86] Pre-commit tests for D103192. NFC (details)
  10. [X86] Fold (shift undef, X)->0 for vector shifts by immediate. (details)
  11. [mlir] Async: Add error propagation support to async groups (details)
  12. [mlir][NFC] Don't outline kernel in MMA integration tests (details)
  13. [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. (details)
  14. [CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets (details)
  15. [NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes (details)
  16. Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11" (details)
  17. [NFC][scudo] Rename internal function (details)
  18. MC: mark `dump` with `LLVM_DUMP_METHOD` (details)
  19. [mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr (details)
  20. [mlir] Update cmake variable post D102976 (details)
  21. [NFC][scudo] Check zeros on smaller allocations (details)
  22. [libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup (details)
  23. [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. (details)
  24. [lldb][intel-pt] Remove old plugin (details)
  25. [mlir:Async] Convert assertions to async errors only inside async functions (details)
  26. [analyzer] RetainCountChecker: Disable reference counting for OSMetaClass. (details)
Commit 6f4794feb60a9deb939873118a7182a8ea87732e by fraser
[RISCV] Add a test case showing incorrect call-conv lowering

@HsiangKai helped find a bug in the lowering of indirect split
scalable-vector types in our calling convention. An imminent patch will
fix this.
The file was addedllvm/test/CodeGen/RISCV/rvv/calling-conv.ll
Commit 6d2c0950205f50f926ba5e362e845faff22582b7 by Yaxun.Liu
[HIP] Check compatibility of -fgpu-sanitize with offload arch

-fgpu-sanitize is incompatible with offload arch containing xnack-.

This patch checks that.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D102975
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/test/Driver/hip-sanitize-options.hip
The file was modifiedclang/lib/Driver/ToolChains/HIP.h
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.cpp
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.h
Commit b44007bec2470db0d9f100c6a9216d8e05cef608 by thomasraoux
[mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops.

In order to allow large matmul operations using the MMA ops we need to chain
operations this is not possible unless "DOp" and "COp" type have matching
layout so remove the "DOp" layout and force accumulator and result type to
match.
Added a test for the case where the MMA value is accumulated.

Differential Revision: https://reviews.llvm.org/D103023
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUDialect.h
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
Commit 5c18d1136665f74b15c0df599f56ac3e2e947fb8 by qiucofan
[SPE] Disable strict-fp for SPE by default

As discussed in PR50385, strict-fp on PowerPC SPE has not been handled
well. This patch disables it by default for SPE.

Reviewed By: nemanjai, vit9696, jhibbits

Differential Revision: https://reviews.llvm.org/D103235
The file was modifiedclang/test/CodeGen/builtins-ppc-fpconstrained.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
Commit 21653600034084e8335374ddc1eb8d362158d9a8 by konndennsa
[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass

This patch changes LoopUnrollAndJamPass from FunctionPass to LoopNest pass.
The next patch will utilize LoopNest to effectively handle loop nests.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D99149
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/innerloop.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopPassManager.h
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
Commit c412979cde54ec3b5d9f3b83f2b8b5b4b353ed65 by ezhulenev
[mlir] Async reference counting for block successors with divergent reference counted liveness

Support reference counted values implicitly passed (live) only to some of the successors.

Example: if branched to ^bb2 token will leak, unless `drop_ref` operation is properly created

```
^entry:
  %token = async.runtime.create : !async.token
   cond_br %cond, ^bb1, ^bb2
^bb1:
  async.runtime.await %token
  async.runtime.drop_ref %token
  br ^bb2
^bb2:
  return
```

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103102
The file was modifiedmlir/test/Dialect/Async/async-runtime-ref-counting.mlir
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
Commit 4fbc66cd6d90d8d5169c43fcc1b1e26e8a98d3a9 by elver
[Clang] Enable __has_feature(coverage_sanitizer)

Like other sanitizers, enable __has_feature(coverage_sanitizer) if clang
has enabled at least one SanitizerCoverage instrumentation type.

Because coverage instrumentation selection is not handled via normal
-fsanitize= (and thus not in SanitizeSet), passing this information
through to LangOptions required propagating the already parsed
-fsanitize-coverage= options from CodeGenOptions through to LangOptions
in FixupInvocation().

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D103159
The file was modifiedclang/docs/SanitizerCoverage.rst
The file was addedclang/test/Lexer/has_feature_coverage_sanitizer.cpp
The file was modifiedclang/include/clang/Basic/Features.def
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
Commit 39957aa4243cb9aec3a7114c0ecf710ecce96b72 by ezhulenev
[mlir] Add error state and error propagation to async runtime values

Depends On D103102

Not yet implemented:
1. Error handling after synchronous await
2. Error handling for async groups

Will be addressed in the followup PRs

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103109
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncOps.td
The file was modifiedmlir/lib/ExecutionEngine/AsyncRuntime.cpp
The file was modifiedmlir/test/Conversion/AsyncToLLVM/convert-runtime-to-llvm.mlir
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
The file was addedmlir/test/mlir-cpu-runner/async-error.mlir
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/include/mlir/ExecutionEngine/AsyncRuntime.h
The file was modifiedmlir/test/Dialect/Async/runtime.mlir
Commit b5f8ac26829385d98f730c2a76c5f9a6306df2f8 by craig.topper
[X86] Pre-commit tests for D103192. NFC
The file was modifiedllvm/test/CodeGen/X86/vec_shift5.ll
Commit a105d3024efec365961e940c489c4ed5198736d2 by craig.topper
[X86] Fold (shift undef, X)->0 for vector shifts by immediate.

We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.

I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.

Differential Revision: https://reviews.llvm.org/D103192
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_shift5.ll
Commit d8c84d2a4efc87b756d9d3df42b80d6f8762f62a by ezhulenev
[mlir] Async: Add error propagation support to async groups

Depends On D103109

If any of the tokens/values added to the `!async.group` switches to the error state, than the group itself switches to the error state.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103203
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncOps.td
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/AsyncRuntime.h
The file was modifiedmlir/test/Dialect/Async/runtime.mlir
The file was modifiedmlir/test/mlir-cpu-runner/async-error.mlir
The file was modifiedmlir/lib/ExecutionEngine/AsyncRuntime.cpp
Commit 750799b7bc3faeda0d4a14e556ce788e0452152e by thomasraoux
[mlir][NFC] Don't outline kernel in MMA integration tests

This matches better how other gpu integration tests are done.

Differential Revision: https://reviews.llvm.org/D103099
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
Commit 527cd013144d3fb3b578640721530fa2d2da4da9 by craig.topper
[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.

There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
Commit 90d25808c4207d22eec27f2677b7e658308dd2f9 by llvm-dev
[CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets

Determined from llvm-mca analysis (btver2 vs bdver2 vs sandybridge), the split+extends+concat sequence on AVX1 capable targets are cheaper than the #ops that the cost was previously based on.
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/cast.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-mul.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-overflow.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/extend.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fix.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
Commit bafbec8535690d625f1ed770db77f762a825ac0b by lebedev.ri
[NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-conversions.ll
The file was modifiedllvm/test/CodeGen/X86/combine-srl.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-math.ll
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/oddshuffles.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sra.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
Commit b6399e85d80d2bea522e4bce1c8c3744e45673e2 by Louis Dionne
Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11"

That fix was actually incorrect and caused tests to start failing.
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/check_round_trip.h
Commit eb69763ad8ea18ef1b0d739847da0be4ab099d51 by Vitaly Buka
[NFC][scudo] Rename internal function
The file was modifiedcompiler-rt/lib/scudo/standalone/linux.cpp
Commit 4cc5a971010efd48c60820b17c8de8ed086aa45f by Saleem Abdulrasool
MC: mark `dump` with `LLVM_DUMP_METHOD`

Mark the `ELFRelocationEntry::dump` method as `LLVM_DUMP_METHOD` to
annotate it properly as used to prevent the function being dead stripped
away.  This allows use of `dump` in the debugger.  This is purely to
improve the developer experience.
The file was modifiedllvm/include/llvm/MC/MCELFObjectWriter.h
Commit 9136b7d075d26a04db9dfed43c37e4c05cd3ccff by ezhulenev
[mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr

Differential Revision: https://reviews.llvm.org/D103270
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
Commit 5618a5a0594403bc8a22b60e06abd7f9d1e57afc by jpienaar
[mlir] Update cmake variable post D102976
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
Commit c261edb277020471b7670a8b2f826efc73c5d941 by Vitaly Buka
[NFC][scudo] Check zeros on smaller allocations

1Tb counting was the slowest test under the QEMU with MTE.
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/common_test.cpp
Commit 8d7d7f340ea0202cedddc786b484048da4bbc767 by Louis Dionne
[libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup

The test would previously disable itself using `#if TEST_STD_VER` instead
of using UNSUPPORTED markup.
The file was modifiedlibcxx/test/std/utilities/memory/storage.iterator/raw_storage_iterator.base.pass.cpp
Commit d7ae2438b9bd062159fa9bfa8e4db2b8a0d66e38 by craig.topper
[RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop.

This is another case we need to look through a phi to prove.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit 32bacb74107e45cdcedaf3bb2be11bd6e3015390 by walter erquinigo
[lldb][intel-pt] Remove old plugin

Now that LLDB proper has built-in support for intel-pt traces, we can remove the old plugin written by Intel. It has less features and it's hard to work with.

As a test, I ran "ninja lldbIntelFeatures" and it worked.

Differential Revision: https://reviews.llvm.org/D102866
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.cpp
The file was removedlldb/tools/intel-features/intel-pt/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/Decoder.h
The file was modifiedlldb/tools/intel-features/cli-wrapper.cpp
The file was removedlldb/tools/intel-features/scripts/python-typemaps.txt
The file was removedlldb/tools/intel-features/scripts/lldb-intel-features.swig
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.h
The file was modifiedlldb/tools/intel-features/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/Decoder.cpp
The file was removedlldb/tools/intel-features/intel-pt/README_CLI.txt
The file was modifiedlldb/tools/intel-features/README.txt
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.cpp
The file was removedlldb/tools/intel-features/intel-pt/README_TOOL.txt
The file was removedlldb/tools/intel-features/intel-pt/interface/PTDecoder.i
The file was removedlldb/tools/intel-features/scripts/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.h
Commit 8f23fac4da254e8cd2a3160a4fa029613a284ebe by ezhulenev
[mlir:Async] Convert assertions to async errors only inside async functions

Differential Revision: https://reviews.llvm.org/D103278
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
Commit 50f17e9d313960ddc956c20e4f90cfbfed91ecb1 by Artem Dergachev
[analyzer] RetainCountChecker: Disable reference counting for OSMetaClass.

It is a reference-counted class but it uses different methods for that
and the checker doesn't understand them yet.

Differential Revision: https://reviews.llvm.org/D103081
The file was modifiedclang/test/Analysis/os_object_base.h
The file was modifiedclang/test/Analysis/osobject-retain-release.cpp
The file was modifiedclang/lib/Analysis/RetainSummaryManager.cpp