SuccessChanges

Summary

  1. Support stripping indirectly referenced DILocations from !llvm.loop metadata (details)
  2. [NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR (details)
  3. [x86] add tests for extend of vector compare; NFC (details)
  4. Replace 'magic static' with a member variable for SCYL kernel names (details)
  5. [libc++] NFC: Make it easier for vendors to extend the run-buildbot script (details)
  6. [clang] [MinGW] Don't mark emutls variables as DSO local (details)
  7. [libcxx] [test] Convert an XFAIL LIBCXX-WINDOWS-FIXME into UNSUPPORTED with explanation (details)
  8. [mlir] Add support for querying the ModRef behavior from the AliasAnalysis class (details)
  9. [RISCV] Fix typo, use addImm instead of addReg. (details)
  10. [PDB] Enable parallel ghash type merging by default (details)
  11. [PowerPC] Added multiple PowerPC builtins (details)
  12. [MCA] Refactor the InOrderIssueStage stage. NFCI (details)
  13. [mlir-lsp-server] Add support for processing split files (details)
  14. [sanitizer] Android ELF TLS is supported from Q (API 29) (details)
  15. [mlir][capi] fix build issue with "all passes" registration (details)
  16. [NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes (details)
  17. [SanCov] Properly set ABI parameter attributes (details)
  18. [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli. (details)
Commit f3869a5c32b78bc70e5051efbc2594f772b0176e by Adrian Prantl
Support stripping indirectly referenced DILocations from !llvm.loop metadata

in stripDebugInfo().  This patch fixes an oversight in
https://reviews.llvm.org/D96181 and also takes into account loop
metadata pointing to other MDNodes that point into the debug info.

rdar://78487175

Differential Revision: https://reviews.llvm.org/D103220
The file was modifiedllvm/lib/IR/DebugInfo.cpp
The file was addedllvm/test/Verifier/llvm.loop-cu-strip-indirect.ll
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/include/llvm/IR/DebugInfo.h
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
Commit 9712b16763602370f8f66775da6f3766c139ebab by lebedev.ri
[NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR

Now that i've reimplemented the testcase generator
to produce actual IR (https://godbolt.org/z/s7PM8E6v9),
it turns out that this was the only discrepancy
from what the LV would produce.
The file was modifiedllvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
Commit 0d5219feb9b26f299823b43c3c478e98cb3a0915 by spatel
[x86] add tests for extend of vector compare; NFC
The file was addedllvm/test/CodeGen/X86/sext-vsetcc.ll
Commit cb66bf2c6d20da01ab57cb78ec5e5c0978b873be by erich.keane
Replace 'magic static' with a member variable for SCYL kernel names

I discovered when merging the __builtin_sycl_unique_stable_name into my
downstream that it is actually possible for the cc1 invocation to have
more than 1 Sema instance, if you pass it multiple input files, each
gets its own Sema instance and thus ASTContext instance.  The result was
that the call to Filter the SYCL kernels was using an
ItaniumMangleContext stored via a 'magic static', so it had an invalid
reference to ASTContext when processing the 2nd failure.

The failure is unfortunately flakey/transient, but the test that fails
was added anyway.

The magic-static was switched to a unique_ptr member variable in
ASTContext that is initialized when needed.
The file was addedclang/test/SemaSYCL/unique-stable-name-multiple-target-crash.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
Commit aad878f11279305b55e43d7225a36dc0035ecc86 by Louis Dionne
[libc++] NFC: Make it easier for vendors to extend the run-buildbot script
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 0e4cf807aeaf54a10e02176498a7df13ac722b37 by martin
[clang] [MinGW] Don't mark emutls variables as DSO local

These actually can be automatically imported from another DLL. (This
works properly as long as the actual implementation of emutls is
linked dynamically from e.g. libgcc; if the implementation comes from
compiler-rt or a statically linked libgcc, it doesn't work as intended.)

This fixes PR50146 and https://github.com/msys2/MINGW-packages/issues/8706
(fixing calling std::call_once in a dynamically linked libstdc++);
since f73183958482602c4588b0f4a1c3a096e7542947 the dso_local attribute
on the TLS variable affected the actual generated code for accessing
the emutls variable.

The dso_local attribute on the emutls variable made those accesses to
use 32 bit relative addressing in code, which requires runtime pseudo
relocations in the text section, and breaks entirely if the actual
other variable ends up loaded too far away in the virtual address
space.

Differential Revision: https://reviews.llvm.org/D102970
The file was modifiedclang/test/CodeGen/dso-local-executable.c
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit b3ceffdf35e5018958891215000b010ac614dbcc by martin
[libcxx] [test] Convert an XFAIL LIBCXX-WINDOWS-FIXME into UNSUPPORTED with explanation

Differential Revision: https://reviews.llvm.org/D103149
The file was modifiedlibcxx/test/libcxx/debug/extern-templates.sh.cpp
Commit d47dd11071322ad7be6ec7e35a89d0d8f26534b9 by riddleriver
[mlir] Add support for querying the ModRef behavior from the AliasAnalysis class

This allows for checking if a given operation may modify/reference/or both a given value. Right now this API is limited to Value based memory locations, but we should expand this to include attribute based values at some point. This is left for future work because the rest of the AliasAnalysis API also has this restriction.

Differential Revision: https://reviews.llvm.org/D101673
The file was modifiedmlir/include/mlir/Analysis/AliasAnalysis.h
The file was modifiedmlir/lib/Analysis/AliasAnalysis/LocalAliasAnalysis.cpp
The file was modifiedmlir/test/lib/Analysis/TestAliasAnalysis.cpp
The file was modifiedmlir/lib/Analysis/AliasAnalysis.cpp
The file was modifiedmlir/include/mlir/Analysis/AliasAnalysis/LocalAliasAnalysis.h
The file was addedmlir/test/Analysis/test-alias-analysis-modref.mlir
Commit 020df692d801c4fa9a67eb32e923927e33f9e4b5 by craig.topper
[RISCV] Fix typo, use addImm instead of addReg.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
Commit 109aac92128ca958afe5141a59347c8a0733ea3e by rnk
[PDB] Enable parallel ghash type merging by default

Ghashing is probably going to be faster in most cases, even without
precomputed ghashes in object files.

Here is my table of results linking clang.pdb:

-------------------------------
| threads | GHASH   | NOGHASH |
-------------------------------
|  j1     | 51.031s | 25.141s |
|  j2     | 31.079s | 22.109s |
|  j4     | 18.609s | 23.156s |
|  j8     | 11.938s | 21.984s |
| j28     |  8.375s | 18.391s |
-------------------------------

This shows that ghashing is faster if at least four cores are available.
This may make the linker slower if most cores are busy in the middle of
a build, but in that case, the linker probably isn't on the critical
path of the build. Incremental build performance is arguably more
important than highly contended batch build link performance.

The -time output indicates that ghash computation is the dominant
factor:

    Input File Reading:             924 ms (  1.8%)
    GC:                             689 ms (  1.3%)
    ICF:                            527 ms (  1.0%)
    Code Layout:                    414 ms (  0.8%)
    Commit Output File:              24 ms (  0.0%)
    PDB Emission (Cumulative):    49938 ms ( 94.8%)
      Add Objects:                46783 ms ( 88.8%)
        Global Type Hashing:      38983 ms ( 74.0%)
        GHash Type Merging:        5640 ms ( 10.7%)
        Symbol Merging:            2154 ms (  4.1%)
      Publics Stream Layout:        188 ms (  0.4%)
      TPI Stream Layout:             18 ms (  0.0%)
      Commit to Disk:              2818 ms (  5.4%)
  --------------------------------------------------
  Total Link Time:                52669 ms (100.0%)

We can speed that up with a faster content hash (not SHA1).

Differential Revision: https://reviews.llvm.org/D102888
The file was modifiedlld/test/COFF/pdb-type-server-simple.test
The file was modifiedlld/COFF/Driver.cpp
Commit 62b5df7fe2b3fda1772befeda15598fbef96a614 by stefanp
[PowerPC] Added multiple PowerPC builtins

This is the first in a series of patches to provide builtins for
compatibility with the XL compiler. Most of the builtins already had
intrinsics and only needed to be implemented in the front end.
Intrinsics were created for the three iospace builtins, eieio, and icbt.
Pseudo instructions were created for eieio and iospace_eieio to
ensure that nops were inserted before the eieio instruction.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D102443
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-sync.c
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/test/CodeGen/PowerPC/eieio.ll
Commit 50770d8de56068312bd0e1baa63e86912ce2b631 by andrea.dibiagio
[MCA] Refactor the InOrderIssueStage stage. NFCI

Moved the logic that checks for RAW hazards from the InOrderIssueStage to the
RegisterFile.

Changed how the InOrderIssueStage keeps track of backend stalls. Stall events
are now generated from method notifyStallEvent().

No functional change intended.
The file was modifiedllvm/lib/MCA/Stages/ExecuteStage.cpp
The file was modifiedllvm/include/llvm/MCA/Stages/InOrderIssueStage.h
The file was modifiedllvm/lib/MCA/HardwareUnits/RegisterFile.cpp
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
The file was modifiedllvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
The file was modifiedllvm/lib/MCA/Stages/InOrderIssueStage.cpp
The file was modifiedllvm/include/llvm/MCA/Stages/InstructionTables.h
The file was modifiedllvm/include/llvm/MCA/Stages/ExecuteStage.h
The file was modifiedllvm/include/llvm/MCA/HWEventListener.h
Commit 8cbbc5d00b6a13ccef2b61d151aa56e9f851839c by riddleriver
[mlir-lsp-server] Add support for processing split files

MLIR tools very commonly use `// -----` to split a file into distinct sub documents, that are processed separately. This revision adds support to mlir-lsp-server for splitting MLIR files based on this sigil, and processing them separately.

Differential Revision: https://reviews.llvm.org/D102660
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
The file was addedmlir/test/mlir-lsp-server/definition-split-file.test
Commit b834d6309455e340d6f5dcb8b8de885da5cf25a0 by rprichard
[sanitizer] Android ELF TLS is supported from Q (API 29)

Reviewed By: oontvoo, MaskRay

Differential Revision: https://reviews.llvm.org/D103214
The file was modifiedcompiler-rt/CMakeLists.txt
The file was modifiedcompiler-rt/test/lit.common.cfg.py
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/use_tls_test.cpp
Commit ef1cc4e7aebea584c9e63837fc83f4f755cb7af3 by ajcbik
[mlir][capi] fix build issue with "all passes" registration

Some builds exposed missing dependences on trafo/conv passes.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D103283
The file was modifiedmlir/lib/CAPI/Registration/CMakeLists.txt
Commit ee544b8d868d5845798c37200a4b2bd9de889a96 by lebedev.ri
[NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-128.ll
The file was modifiedllvm/test/CodeGen/X86/buildvec-extract.ll
The file was modifiedllvm/test/CodeGen/X86/insertelement-zero.ll
Commit 2d2a9020785c6e02afebc876aa2778fa64c5cafd by aeubanks
[SanCov] Properly set ABI parameter attributes

Arguments need to have the proper ABI parameter attributes set.

Followup to D101806.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D103288
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/div-tracing.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/const-cmp-tracing.ll
Commit 0fa5aac292b8e1bafb00b55233c78466b06bc323 by craig.topper
[RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli.

If an instruction's AVL operand is a PHI node in the same block,
we may be able to peek through the PHI to find vsetvli instructions
that produce the AVL in other basic blocks. If we can prove those
vsetvli instructions have the same VTYPE and were the last vsetvli
in their respective blocks, then we don't need to insert a vsetvli
for this pseudo instruction.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103277
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp