SuccessChanges

Summary

  1. [gn build] manually port 982e3c05108b6 (check-lld needs dsymutil) (details)
  2. [AArch64][RISCV] Make sure isel correctly honors failure orderings. (details)
  3. [clang-format] [docs] Regenerate style options documentation. (details)
  4. [dsymutil tests] Try to make eh_frames.test run on other platforms (details)
  5. [NFC] Remove confusing info about MainLoop VF/UF from debug message (details)
  6. [RISCV] Pre-commit test cases for D103211. NFC (details)
  7. [LoopUnroll] Clean up exit folding (NFC) (details)
  8. [LoopUnroll] Add store to unreachable latch test (NFC) (details)
  9. [RISCV] Add separate MxList tablegen classes for widening/narrowing and sext.zext.vf2/4/8. NFC (details)
  10. [LoopUnroll] Use changeToUnreachable() (NFC) (details)
  11. [lld-macho][test] Simplify --allow-empty with count 0 (details)
  12. [CGAtomic] Delete outdated code comparing success/failure ordering for cmpxchg. (details)
  13. [Verifier] Significantly speed up IsolatedFromAbove checking. NFC. (details)
  14. [clang-format] New BreakInheritanceList style AfterComma (details)
  15. [AArch64][GlobalISel] Fix a crash during selection of a G_ZEXT(s8 = G_LOAD) (details)
  16. [Internalize] Simplify comdat renaming with noduplicates after D103043 (details)
  17. [lld/mac] Don't crash on -order_file with assembly inputs on arm64 (details)
  18. [RISCV] Enable interleaved vectorization for RVV (details)
  19. [InstrProfiling][test] Fix stale tests (details)
  20. [InstrProfiling][test] Fix stale linkage.ll (details)
  21. [AtomicExpandPass][AArch64] Promote xchg with floating-point types to integer ones (details)
  22. [LoopUnroll] Make DomTree explicitly required (NFC) (details)
  23. Revert "[libc++] NFC: Move unwrap_iter to its own header" (details)
  24. [gn build] Port b13edf6e907b (details)
  25. [SystemZ] Set getExtendForAtomicOps to ISD::ANY_EXTEND (details)
  26. [analyzer]  Use Optional as a return type of StoreManager::castRegion (details)
  27. [InstCombine] reduce code duplication; NFC (details)
  28. [InstCombine] fold zext of masked bit set/clear (details)
  29. [RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases (details)
  30. [Support] Fix getMainExecutable on FreeBSD when called via an absolute path (details)
  31. Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" (details)
Commit 1a0e5d561ceb0af7a9ad356b0663dabac09d110f by thakis
[gn build] manually port 982e3c05108b6 (check-lld needs dsymutil)
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn
Commit 0b3b0a727ad6bac089a57e3625dd9dbf4e6f5bde by efriedma
[AArch64][RISCV] Make sure isel correctly honors failure orderings.

If a cmpxchg specifies acquire or seq_cst on failure, make sure we
generate code consistent with that ordering even if the success ordering
is not acquire/seq_cst.

At one point, it was ambiguous whether this sort of construct was valid,
but the C++ standad and LLVM now accept arbitrary combinations of
success/failure orderings.

This doesn't address the corresponding issue in AtomicExpand. (This was
reported as https://bugs.llvm.org/show_bug.cgi?id=33332 .)

Fixes https://bugs.llvm.org/show_bug.cgi?id=50512.

Differential Revision: https://reviews.llvm.org/D103284
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/test/CodeGen/AArch64/atomic-ops-lse.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
Commit 8702c6da162b6db962c8155195d79f1e002bc481 by marek.kurdej+llvm.org
[clang-format] [docs] Regenerate style options documentation.

Forgotten in commits fce8c10b, 9363aa90, 8d93d7ff.
The file was modifiedclang/docs/ClangFormatStyleOptions.rst
Commit 65527a8082ac947aa47cc2ff84b555da7dad48e1 by thakis
[dsymutil tests] Try to make eh_frames.test run on other platforms

We now have llvm-otool :)
The file was modifiedllvm/test/tools/dsymutil/X86/eh_frame.test
Commit 06eaffa8582134bfa47a1263f8b65fe17076d8c3 by bmahjour
[NFC] Remove confusing info about MainLoop VF/UF from debug message
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit a41309966a862be3817d05e4ae9ece60a7d8de86 by craig.topper
[RISCV] Pre-commit test cases for D103211. NFC
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
Commit f765445a691187c69a8a7c14991acb4589314e93 by nikita.ppv
[LoopUnroll] Clean up exit folding (NFC)

This does some non-functional cleanup of exit folding during
unrolling. The two main changes are:

* First rewrite latch->header edges, which is unrelated to exit
   folding.
* Combine folding for latch and non-latch exits. After the
   previous change, the only difference in their logic is that
   for non-latch exits we currently only fold "known non-exit"
   cases, but not "known exit" cases.

I think this helps a lot to clarify this code and prepare it for
future changes.

Differential Revision: https://reviews.llvm.org/D103333
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
Commit 4af2730ac3e9e712266bcdb754e605d7d9c190fd by nikita.ppv
[LoopUnroll] Add store to unreachable latch test (NFC)

This is to show that we currently only convert the terminator to
unreachable, but don't clean up instructions before it (unless
trivial DCE removes them).

Also clean up excessive whitespace in this test.
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
Commit bc6799f2f79f0ae87e9f1ebf9d25ba799fbd25a9 by craig.topper
[RISCV] Add separate MxList tablegen classes for widening/narrowing and sext.zext.vf2/4/8. NFC

This is cleaner than slicing the MxList to remove elements from
the beginning or end since that requires hardcoding the size.

I don't expect the size of the list to change, but we shouldn't
repeat it in multiple places.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 90310dfff8fd17b0cabdee1fd72d675e5eb2aa78 by nikita.ppv
[LoopUnroll] Use changeToUnreachable() (NFC)

When fulling unrolling with a non-latch exit, the latch block is
folded to unreachable. Replace this folding with the existing
changeToUnreachable() helper, rather than performing it manually.

This also moves the fold to happen after the manual DT update
for exit blocks. I believe this is correct in that the conversion
of an unconditional backedge into unreachable should not affect
the DT at all.

Differential Revision: https://reviews.llvm.org/D103340
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
Commit 2644399ce7721cba9a546a9af09fd2a942a4d0cd by i
[lld-macho][test] Simplify --allow-empty with count 0
The file was modifiedlld/test/MachO/lto-archive.ll
The file was modifiedlld/test/MachO/treat-undef-sym.s
The file was modifiedlld/test/MachO/u.s
Commit 577fea4e1a13319adf2b660f57bf570195a7f78d by efriedma
[CGAtomic] Delete outdated code comparing success/failure ordering for cmpxchg.

This doesn't actually have any effect: we only call this code with
SequentiallyConsistent orderings.  But delete it anyway for consistency
with other recent changes.
The file was modifiedclang/lib/CodeGen/CGAtomic.cpp
Commit bde21b624585255dbd28c0bc0e93d37045b5a9a9 by clattner
[Verifier] Significantly speed up IsolatedFromAbove checking. NFC.

The implementation had a couple of problems, including checking
"isProperAncestor" in an inefficient way.  It also recursed into
other "isolated from above" ops.  In the case of CIRCT, we get
three levels of isolated ops:

  mlir::ModuleOp
    firrtl::CircuitOp
       firrtl::FModuleOp

The verification for module would recurse into the circuits and
fmodules checking them.  The verifier hook for circuit would
recurse into all the modules reverifying them, fmoduleop would
then reverify them.  The same happens for mlir::ModuleOp and Func.

While here, fix an old design problem: IsolatedFromAbove checking
was implemented by a method on the Region class, which isn't
actually general and isn't used by anything else.  Move it over
to be a trait impl verifier method like the others and specialize
it for its task.

Differential Revision: https://reviews.llvm.org/D103345
The file was modifiedmlir/include/mlir/IR/Region.h
The file was modifiedmlir/lib/IR/Region.cpp
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
The file was modifiedmlir/lib/IR/Operation.cpp
Commit 09b75f480d1d578d48307fd7f3b024b66a75712f by lichray
[clang-format] New BreakInheritanceList style AfterComma

This inheritance list style has been widely adopted by Symantec,
a division of Broadcom Inc. It breaks after the commas that
separate the base-specifiers:

    class Derived : public Base1,
                    private Base2
    {
    };

Differential Revision: https://reviews.llvm.org/D103204
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/lib/Format/Format.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/docs/ClangFormatStyleOptions.rst
The file was modifiedclang/include/clang/Format/Format.h
Commit 018a9641ff1a488f3ffbe1251666696fa5b29915 by Amara Emerson
[AArch64][GlobalISel] Fix a crash during selection of a G_ZEXT(s8 = G_LOAD)

We have special handling for a zext of a load <32b because the load does a zext
for free. In that case, we just select the G_ZEXT as if it were a copy but this
triggered the copy checking code to balk at the mismatched size.

This was being hidden because normally these get combined into G_ZEXTLOAD but
for atomics this doesn't happen. The test case here just uses a normal load
because the particular atomic isn't supported yet anyway.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit 38dbdde7924cb1ab5919dc49bbd7d3ad420967f1 by i
[Internalize] Simplify comdat renaming with noduplicates after D103043

I realized that we can use `comdat noduplicates` which is available on ELF.
Add a special case for wasm which doesn't support the feature.
The file was modifiedllvm/include/llvm/Transforms/IPO/Internalize.h
The file was removedllvm/test/Transforms/Internalize/comdat-empty-moduleid.ll
The file was modifiedllvm/lib/Transforms/IPO/Internalize.cpp
The file was modifiedllvm/test/Transforms/Internalize/comdat.ll
Commit c4053cd14eb9b5fe12b4ea9bc99bd83548d1f371 by thakis
[lld/mac] Don't crash on -order_file with assembly inputs on arm64

.s files with `-g` generate __debug_aranges on darwin/arm64 for some
reason, and those lead to `nullptr` symbols. Don't crash on that.

Fixes PR50517.

Differential Revision: https://reviews.llvm.org/D103350
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/test/MachO/order-file.s
Commit c4c3869554a6fb3cfb268cb1331d611eb7609794 by luke957
[RISCV] Enable interleaved vectorization for RVV

Enable interleaved vectorization for RVV.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101469
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
The file was addedllvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
Commit 9f506fc761cc93ebc3854906e8886e1791c29d28 by i
[InstrProfiling][test] Fix stale tests

* Change linkage/visibility of __profn_ variables to match the reality
* alwaysinline.ll: Add "EnableValueProfiling", otherwise it doesn't test available_externally alwaysinline.
* Delete PR23499.ll - covered by other comdat tests.
The file was removedllvm/test/Instrumentation/InstrProfiling/PR23499.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/always_inline.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/atomic-updates.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/linkage.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/noruntime.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/runtime-counter-relocation.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/early-exit.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/platform.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/profiling.ll
Commit cdd1adfb7d5d5048a7fdedc441e75db019fbb0b5 by i
[InstrProfiling][test] Fix stale linkage.ll
The file was modifiedllvm/test/Instrumentation/InstrProfiling/linkage.ll
Commit b577ec495698c585837db3893c5662d3aa0aab87 by thatlemon
[AtomicExpandPass][AArch64] Promote xchg with floating-point types to integer ones

Follow the same strategy used for atomic loads/stores by converting the operands to equally-sized integer types.
This change prevents the atomic expansion pass from generating illegal LL/SC pairs when targeting AArch64: `expand-atomicrmw-xchg-fp.ll` would previously instantiate intrinsics such as `llvm.aarch64.ldaxr.p0f32` that cannot be lowered.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D103232
The file was modifiedllvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll
The file was addedllvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
The file was modifiedllvm/test/CodeGen/X86/atomicf128.ll
The file was modifiedllvm/lib/CodeGen/AtomicExpandPass.cpp
The file was modifiedllvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
Commit 625920dabf49443d76ae05f954b0aabe33a76eba by nikita.ppv
[LoopUnroll] Make DomTree explicitly required (NFC)

Some of the code was already assuming that DT is non-null, so
make that requirement more explicit and remove unnecessary null
checks.
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
Commit b13edf6e907b32d0b8da09dfe08fa271638eca3c by koraq
Revert "[libc++] NFC: Move unwrap_iter to its own header"

This reverts commit 9968896cd62a62b11ac61085534dd598c4bd3c60.

This commit seems to cause the build failures of main.
The file was removedlibcxx/include/__algorithm/unwrap_iter.h
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/include/algorithm
Commit 42910da585d368208365247e6616f80880d5cc3e by llvmgnsyncbot
[gn build] Port b13edf6e907b
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit c123c178b26ea38a1035093edfa430256bfd1e64 by ulrich.weigand
[SystemZ] Set getExtendForAtomicOps to ISD::ANY_EXTEND

The implementation of subword atomics does not actually
guarantee the result is zero-extended, which now caused
build bot failures after https://reviews.llvm.org/D101342
was landed.
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.h
Commit fae3534b3056bb96d26a6d1b6e7d6a2ccaf4fab1 by dpetrov
[analyzer]  Use Optional as a return type of StoreManager::castRegion

Summary: Make StoreManager::castRegion function usage safier. Replace `const MemRegion *` with `Optional<const MemRegion *>`. Simplified one of related test cases due to suggestions in D101635.

Differential Revision: https://reviews.llvm.org/D103319
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h
The file was modifiedclang/lib/StaticAnalyzer/Core/Store.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/SValBuilder.cpp
The file was modifiedclang/test/Analysis/casts.c
Commit 52f2970036019b54f280bd531c7c65c09e18567a by spatel
[InstCombine] reduce code duplication; NFC
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit c7da0c383a1bb360887a51f094d5891a9108d767 by spatel
[InstCombine] fold zext of masked bit set/clear

This does not solve PR17101, but it is one of the
underlying diffs noted here:
https://bugs.llvm.org/show_bug.cgi?id=17101#c8

We could ease the one-use checks for the 'clear'
(no 'not' op) half of the transform, but I do not
know if that asymmetry would make things better
or worse.

Proofs:
https://rise4fun.com/Alive/uVB

Name: masked bit set
%sh1 = shl i32 1, %y
%and = and i32 %sh1, %x
%cmp = icmp ne i32 %and, 0
%r = zext i1 %cmp to i32
=>
%s = lshr i32 %x, %y
%r = and i32 %s, 1

Name: masked bit clear
%sh1 = shl i32 1, %y
%and = and i32 %sh1, %x
%cmp = icmp eq i32 %and, 0
%r = zext i1 %cmp to i32
=>
%xn = xor i32 %x, -1
%s = lshr i32 %xn, %y
%r = and i32 %s, 1

Note: this is a re-post of a patch that I committed at:
rGa041c4ec6f7a

The commit was reverted because it exposed another bug:
rGb212eb7159b40

But that has since been corrected with:
rG8a156d1c2795189 ( D101191 )

Differential Revision: https://reviews.llvm.org/D72396
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc by jrtc27
[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases

Whilst here, also remove a couple of unnecessary -o - instances.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D103201
The file was modifiedllvm/test/MC/RISCV/rv64d-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv-user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32d.s
The file was modifiedllvm/test/MC/RISCV/rv32dc-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-debug-info.s
The file was modifiedllvm/test/MC/RISCV/option-pic.s
The file was modifiedllvm/test/MC/RISCV/rv64b-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv/others.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32c-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32e-valid.s
The file was modifiedllvm/test/MC/RISCV/rvd-aliases-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/test/MC/RISCV/rv64zbb-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32zfh-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64d-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64-machine-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rv32c-only-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32-machine-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rv64a-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64f-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-invalid.s
The file was modifiedllvm/test/MC/RISCV/rvv/aliases.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64m-valid.s
The file was modifiedllvm/test/MC/RISCV/rva-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv64b.s
The file was modifiedllvm/test/CodeGen/RISCV/patchable-function-entry.ll
The file was modifiedllvm/test/MC/RISCV/rv32b-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-cjal.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-invalid.s
The file was modifiedllvm/test/MC/RISCV/rv64-user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rvdc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv/load.s
The file was modifiedllvm/test/MC/RISCV/supervisor-csr-names.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32i.s
The file was modifiedllvm/test/MC/RISCV/rv64dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32d-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32zbb-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32f-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32i-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64zfh-valid.s
The file was modifiedllvm/test/MC/RISCV/rvc-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv/zvlsseg.s
The file was modifiedllvm/test/MC/RISCV/rv32m-valid.s
The file was modifiedllvm/test/MC/RISCV/rvf-user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/option-rvc.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32b.s
The file was modifiedllvm/test/MC/RISCV/rv64zbproposedc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64a-valid.s
The file was modifiedllvm/test/MC/RISCV/option-pushpop.s
The file was modifiedllvm/test/MC/RISCV/relocations.s
The file was modifiedllvm/test/MC/RISCV/rv32c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/debug-valid.s
The file was modifiedllvm/test/MC/RISCV/deprecated-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rvc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32-user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rv64f-valid.s
The file was modifiedllvm/test/MC/RISCV/fixups.s
The file was modifiedllvm/test/MC/RISCV/priv-valid.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32f.s
The file was modifiedllvm/test/MC/RISCV/rvf-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32a-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-valid.s
The file was modifiedllvm/test/MC/RISCV/option-nopic.s
The file was modifiedllvm/test/MC/RISCV/rvv/fothers.s
The file was modifiedllvm/test/MC/RISCV/compress-rv64i.s
The file was modifiedllvm/test/MC/RISCV/user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/compressed-relocations.s
The file was modifiedllvm/test/MC/RISCV/rvv/store.s
The file was modifiedllvm/test/MC/RISCV/machine-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rv32zbproposedc-valid.s
The file was modifiedllvm/test/MC/RISCV/rvzfh-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32zbbp-only-valid.s
Commit 762f707c0072abba60b5b4bdbb64c2c69c6152b1 by jrtc27
[Support] Fix getMainExecutable on FreeBSD when called via an absolute path

On FreeBSD, absolute paths are passed unmodified in AT_EXECPATH, but
relative paths are resolved to absolute paths, and any symlinks will be
followed in the process. This means that the resource dir calculation
will be wrong if Clang is invoked as an absolute path to a symlink, and
this currently causes clang/test/Driver/rocm-detect.hip to fail on
FreeBSD. Thus, make sure to call realpath on the result, just like is
done on macOS.

Whilst here, clean up the old fallback auxargs loop to use the actual
type for auxargs rather than using lots of hacky casts that rely on
addresses and pointers being the same (which is not the case on CHERI,
and thus Arm's prototype Morello, although for little-endian systems it
happens to work still as the word-sized integer will be padded to a full
pointer, and it's someone academic given dereferencing past the end of
environ will give a bounds fault, but CheriBSD is new enough that the
elf_aux_info path will be used). This also makes the code easier to
follow, and removes the confusing double-increment of p.

Reviewed By: dim, arichardson

Differential Revision: https://reviews.llvm.org/D103346
The file was modifiedllvm/lib/Support/Unix/Path.inc
Commit 00dfd4f870411b1b4353906163dd8b673076850b by jrtc27
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"

The replacement doesn't work for llc, but it is needed by
patchable-function-entry.ll.

This reverts commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc.
The file was modifiedllvm/test/MC/RISCV/rv32b-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/supervisor-csr-names.s
The file was modifiedllvm/test/MC/RISCV/compressed-relocations.s
The file was modifiedllvm/test/MC/RISCV/rv64d-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32zbproposedc-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64c-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32a-valid.s
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The file was modifiedllvm/test/MC/RISCV/rv32zbbp-only-valid.s
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The file was modifiedllvm/test/MC/RISCV/rv64i-valid.s
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The file was modifiedllvm/test/MC/RISCV/rv32-user-csr-names.s
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The file was modifiedllvm/test/MC/RISCV/rv64d-aliases-valid.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/test/MC/RISCV/fixups.s
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The file was modifiedllvm/test/MC/RISCV/relocations.s
The file was modifiedllvm/test/CodeGen/RISCV/patchable-function-entry.ll
The file was modifiedllvm/test/MC/RISCV/debug-valid.s
The file was modifiedllvm/test/MC/RISCV/option-pic.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-invalid.s
The file was modifiedllvm/test/MC/RISCV/rvf-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv-user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/rvv/store.s
The file was modifiedllvm/test/MC/RISCV/compress-debug-info.s
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The file was modifiedllvm/test/MC/RISCV/rv64zbb-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-valid.s
The file was modifiedllvm/test/MC/RISCV/user-csr-names.s
The file was modifiedllvm/test/MC/RISCV/priv-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv32zfh-valid.s
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The file was modifiedllvm/test/MC/RISCV/rv32-machine-csr-names.s
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The file was modifiedllvm/test/MC/RISCV/rv64c-hints-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64f-valid.s
The file was modifiedllvm/test/MC/RISCV/rva-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64-machine-csr-names.s
The file was modifiedllvm/test/MC/RISCV/compress-rv32d.s
The file was modifiedllvm/test/MC/RISCV/option-nopic.s
The file was modifiedllvm/test/MC/RISCV/rv32fc-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rvv/load.s
The file was modifiedllvm/test/MC/RISCV/rv32dc-valid.s
The file was modifiedllvm/test/MC/RISCV/rvf-user-csr-names.s