AbortedChanges

Summary

  1. [SafeStack] Use proper API to get stack guard (details)
  2. [NFCI] Move DEBUG_TYPE definition below #includes (details)
  3. [DAGCombine] Poison-prove scalarizeExtractedVectorLoad. (details)
  4. [InstCombine] fix miscompile from vector select substitution (details)
  5. [VectorCombine] Add tests with noundef index for load scalarization. (details)
  6. Revert "[clang-tidy] Simplify static assert check" (details)
  7. [clang][AVR] Add avr-libc/include to clang system include paths (details)
  8. [mlir] StandardToLLVM: option to disable AllocOp lowering (details)
  9. [LoopDeletion] Add more tests with infinite sub-loops & mustprogress. (details)
  10. [AVR] Improve inline assembly (details)
  11. [ARM] Guard against loop variant gather ptr operands (details)
  12. [ORC-RT] Add OrcRTCWrapperFunctionResult. (details)
  13. [ORC-RT] Add common.h -- Logging, casting and remote dispatch utilities. (details)
  14. [CSE] Make domInfo a stored property, cut use of DominanceInfo::hasDominanceInfo. NFC. (details)
  15. [lldb] Fix typos. NFC. (details)
  16. [AVR][NFC] Refactor 8-bit & 16-bit shifts (details)
  17. [InstCombine] Fix miscompile on GEP+load to icmp fold (PR45210) (details)
  18. [clangd] Move gtest include to TestTU.cpp from TestTU.h (details)
  19. [mlir][NFC] Rename MathToLLVM->MathToLibm (details)
  20. [libcxx] [test] Add UNSUPPORTED: msvc in a couple verify.cpp tests (details)
  21. [LangRef] update according to unwinding support in inline asm (details)
  22. [mlir] Support permutation maps in vector transfer op folder (details)
  23. [mlir][NFC] Remove illegal TanhOp in LLVMConversionTarget (details)
  24. [WebAssembly][CodeGen] IR support for WebAssembly local variables (details)
  25. [clang] Add support for the "abstract" contextual keyword of MSVC (details)
  26. Revert "[WebAssembly][CodeGen] IR support for WebAssembly local variables" (details)
  27. [clang] NFC: split HeaderMapTest to have re-usable header map implementation for testing (details)
  28. [RISCV] Support vector conversions between fp and i1 (details)
Commit 056733d0195b28fb1c5a7952b2adc10013edf19c by pzheng
[SafeStack] Use proper API to get stack guard

Using the proper API automatically sets `__stack_chk_guard` to `dso_local` if
`Reloc::Static`. This wasn't strictly necessary until recently when dso_local was
no longer implied by `TargetMachine::shouldAssumeDSOLocal` for
`__stack_chk_guard`. By using the proper API, we can avoid generating unnecessary
GOT relocations.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102646
The file was modifiedllvm/test/Transforms/SafeStack/X86/abi_ssp.ll
The file was modifiedllvm/test/Transforms/SafeStack/X86/ssp.ll
The file was modifiedllvm/lib/CodeGen/SafeStack.cpp
Commit 71acce68daf4987529bf08d81a9c5d396536d7c4 by chenmindong1
[NFCI] Move DEBUG_TYPE definition below #includes

When you try to define a new DEBUG_TYPE in a header file, DEBUG_TYPE
definition defined around the #includes in files include it could
result in redefinition warnings even compile errors.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D102594
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
The file was modifiedllvm/lib/Transforms/Scalar/Float2Int.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
The file was modifiedllvm/utils/TableGen/DFAEmitter.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
The file was modifiedllvm/lib/Target/ARC/ARCBranchFinalize.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
The file was modifiedllvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
The file was modifiedllvm/lib/Analysis/AssumeBundleQueries.cpp
The file was modifiedllvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp
The file was modifiedllvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
The file was modifiedllvm/lib/Target/M68k/M68kRegisterInfo.cpp
The file was modifiedllvm/utils/TableGen/DFAPacketizerEmitter.cpp
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonGenMux.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
Commit 126f90b252509486eab5bfbe06894805b26c8da2 by flo
[DAGCombine] Poison-prove scalarizeExtractedVectorLoad.

extractelement is poison if the index is out-of-bounds, so just
scalarizing the load may introduce an out-of-bounds load, which is UB.

To avoid introducing new UB, we can mask the index so it only contains
valid indices.

Fixes PR50382.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D103077
The file was modifiedllvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
The file was modifiedllvm/test/CodeGen/X86/vecloadextract.ll
The file was modifiedllvm/test/CodeGen/SystemZ/vec-extract-02.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 7bb8bfa0622b8ee55c3f748004dcf4d83d48cf97 by spatel
[InstCombine] fix miscompile from vector select substitution

This is similar to the fix in c590a9880d7a ( PR49832 ), but
we missed handling the pattern for select of bools (no compare
inst).

We can't substitute a vector value because the equality condition
replacement that we are attempting requires that the condition
is true/false for the entire value. Vector select can be partly
true/false.

I added an assert for vector types, so we shouldn't hit this again.
Fixed formatting while auditing the callers.

https://llvm.org/PR50500
The file was modifiedllvm/test/Transforms/InstCombine/select-safe-bool-transforms.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/include/llvm/Analysis/InstructionSimplify.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 829978744d244cbf487e86c0cd385989a3e96a39 by flo
[VectorCombine] Add tests with noundef index for load scalarization.
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
Commit be6b9e8ae71768d2e09ec14619ca4ecfdef553fa by lebedev.ri
Revert "[clang-tidy] Simplify static assert check"

This patch starts to produce a very obvious false-positives,
despite the fact the preexisting tests already cover the pattern.
they clearly don't actually cover it.

https://godbolt.org/z/3zdqvbfxj

This reverts commit 1709bb8c7395418236ec94fe3b9d91fed746452b.
The file was modifiedclang-tools-extra/clang-tidy/misc/StaticAssertCheck.h
The file was modifiedclang-tools-extra/clang-tidy/misc/StaticAssertCheck.cpp
Commit c1ee4fb5af49af5911ad7dc7932d975073030ec3 by powerman1st
[clang][AVR] Add avr-libc/include to clang system include paths

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D97669
The file was addedclang/test/Driver/Inputs/basic_avr_tree/usr/lib/avr/include/.keep
The file was modifiedclang/lib/Driver/ToolChains/AVR.h
The file was modifiedclang/test/Driver/avr-toolchain.c
The file was modifiedclang/lib/Driver/ToolChains/AVR.cpp
Commit bb542f2a76d4256e98e4bf249b77f5b18163fc24 by ivan.butygin
[mlir] StandardToLLVM: option to disable AllocOp lowering

Differential Revision: https://reviews.llvm.org/D103237
The file was modifiedmlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit 268e24a46af0eb3aceb67cf2aba250aef84aa20a by flo
[LoopDeletion] Add more tests with infinite sub-loops & mustprogress.

A couple of additional tests inspired by PR50511.
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
Commit 86812faa5f9bff64656c162cd1afee6948e02adb by powerman1st
[AVR] Improve inline assembly

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D96394
The file was addedllvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
The file was modifiedllvm/lib/Target/AVR/AVRRegisterInfo.td
Commit 2176be556b448361a35c01cfedd5d3fd54b3e2b9 by david.green
[ARM] Guard against loop variant gather ptr operands

This ensures that the operands of any gather/scatter instructions that
we attempt to push out of the loop are invariant, preventing invalid IR
from being generated.
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
Commit 442f2d7bc0bc4f19ce056018231fbed9166c9b08 by Lang Hames
[ORC-RT] Add OrcRTCWrapperFunctionResult.

OrcRTCWrapperFunctionResult is a C struct that can be used to return serialized
results from "wrapper functions" -- functions that deserialize an argument
buffer, call through to an actual implementation function, then serialize and
return the result of that function. Wrapper functions allow calls between ORC
and the ORC Runtime to be written using a single signature,
WrapperFunctionResult(const char *ArgData, size_t ArgSize), and without coupling
either side to a particular transport mechanism (in-memory, TCP, IPC, ... the
actual mechanism will be determined by the TargetProcessControl implementation).

OrcRTCWrapperFunctionResult is designed to allow small serialized buffers to
be returned by value, with larger serialized results stored on the heap. They
also provide an error state to report failures in serialization/deserialization.
The file was addedcompiler-rt/lib/orc/c_api.h
The file was addedcompiler-rt/lib/orc/unittests/c_api_test.cpp
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was modifiedcompiler-rt/lib/orc/unittests/CMakeLists.txt
Commit 1ed29f8784ee528f54cd33300ab8420372141283 by Lang Hames
[ORC-RT] Add common.h -- Logging, casting and remote dispatch utilities.
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/common.h
Commit 1e344ce4f3fac4beb5e23e04dc3dd59398125956 by clattner
[CSE] Make domInfo a stored property, cut use of DominanceInfo::hasDominanceInfo. NFC.

CSE is the only client of this API, refactor it a bit to pull the query
internally to make changes to DominanceInfo a bit easier.  This commit
also improves comments a bit.
The file was modifiedmlir/lib/Transforms/CSE.cpp
The file was modifiedmlir/include/mlir/IR/Dominance.h
Commit 36597e4719e9de6d374f7953aad83234d42ca181 by bruce.mitchener
[lldb] Fix typos. NFC.

Differential Revision: https://reviews.llvm.org/D103381
The file was modifiedlldb/examples/python/process_events.py
The file was modifiedlldb/test/API/commands/expression/call-function/TestCallUserDefinedFunction.py
The file was modifiedlldb/test/API/lang/c/enum_types/TestEnumTypes.py
The file was modifiedlldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/RenderScriptRuntime.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
The file was modifiedlldb/source/API/SBDebugger.cpp
The file was modifiedlldb/docs/design/overview.rst
The file was modifiedlldb/docs/resources/test.rst
The file was modifiedlldb/unittests/Symbol/TestClangASTImporter.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
The file was modifiedlldb/docs/status/projects.rst
The file was modifiedlldb/docs/use/python-reference.rst
The file was modifiedlldb/include/lldb/Core/Debugger.h
The file was modifiedlldb/source/Core/ValueObject.cpp
The file was modifiedlldb/test/API/lang/cpp/covariant-return-types/TestCovariantReturnTypes.py
Commit 22668c6e1f36b375944a00495d71e20ee15639fb by powerman1st
[AVR][NFC] Refactor 8-bit & 16-bit shifts

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D98335
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.h
The file was modifiedllvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.td
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
Commit 4f2fd3818b0eb26806f366bc37369349aeedcaf9 by aqjune
[InstCombine] Fix miscompile on GEP+load to icmp fold (PR45210)

As noted in PR45210: https://bugs.llvm.org/show_bug.cgi?id=45210
...the bug is triggered as Eli say when sext(idx) * ElementSize overflows.

```
   // assume that GV is an array of 4-byte elements
   GEP = gep GV, 0, Idx // this is accessing Idx * 4
   L = load GEP
   ICI = icmp eq L, value
 =>
   ICI = icmp eq Idx, NewIdx
```

The foldCmpLoadFromIndexedGlobal function simplifies GEP+load operation to icmp.
And there is a problem because Idx * ElementSize can overflow.

Let's assume that the wanted value is at offset 0.
Then, there are actually four possible values for Idx to match offset 0: 0x00..00, 0x40..00, 0x80..00, 0xC0..00.
We should return true for all these values, but currently, the new icmp only returns true for 0x00..00.

This problem can be solved by masking off (trailing zeros of ElementSize) bits from Idx.

```
   ...
 =>
   Idx' = and Idx, 0x3F..FF
   ICI = icmp eq Idx', NewIdx
```

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D99481
The file was modifiedllvm/test/Transforms/InstCombine/load-cmp.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit e972068840710a8c832d21603b8409692604b865 by kadircet
[clangd] Move gtest include to TestTU.cpp from TestTU.h
The file was modifiedclang-tools-extra/clangd/unittests/TestTU.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TestTU.h
The file was modifiedclang-tools-extra/clangd/unittests/TestWorkspace.cpp
Commit 5aa5eba135b7a5ee98ea99c56d3206891a260268 by tpopp
[mlir][NFC] Rename MathToLLVM->MathToLibm
The file was addedmlir/test/Conversion/MathToLibm/convert-to-libm.mlir
The file was removedmlir/test/Conversion/MathToLLVM/convert-to-libm.mlir
Commit 7d7b72bad7ff1fc22c79d535826de43452f3379d by martin
[libcxx] [test] Add UNSUPPORTED: msvc in a couple verify.cpp tests

Due to issues with the detection of the clang-verify feature, these
tests have been skipped in the Windows CI configuration so far.

Differential Revision: https://reviews.llvm.org/D103308
The file was modifiedlibcxx/test/std/utilities/meta/meta.trans/meta.trans.other/underlying_type.fail.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.categories.pre/zero_type.verify.cpp
Commit 22f635b1b31a6bee1b0b8df58d5c8207c835b216 by amanieu
[LangRef] update according to unwinding support in inline asm

https://reviews.llvm.org/D95745 introduced a new `unwind` keyword for inline assembler expressions. Inline asms marked with the `unwind` keyword allows stack unwinding from inline assembly because the compiler emits unwinding information ("around" the inline asm) as it would for calls/invokes. Unwinding the stack from within non-unwind inline asm may cause UB.

Reviewed By: Amanieu

Differential Revision: https://reviews.llvm.org/D102642
The file was modifiedllvm/docs/LangRef.rst
Commit 2bc8ffa8afabeaf1cc97640419c1c2a926265170 by springerm
[mlir] Support permutation maps in vector transfer op folder

Fold away in_bounds attribute even if the transfer op has a non-identity permutation map.

Differential Revision: https://reviews.llvm.org/D103133
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit 2290a80b4dcbeb230ea47ea59b00205ccefbaa96 by tpopp
[mlir][NFC] Remove illegal TanhOp in LLVMConversionTarget

No tests fail and this seems to be technical debt from when the math
dialect was created. This should not be there as it prevents users from
configuring their converion target freely and results in unexpected
behavior on seemingly unrelated ops.

Differential Revision: https://reviews.llvm.org/D103388
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit bf35f4af51cddd743435bb6b94a45592c967891a by wingo
[WebAssembly][CodeGen] IR support for WebAssembly local variables

This patch adds TargetStackID::WasmLocal.  This stack holds locations of
values that are only addressable by name -- not via a pointer to memory.
For the WebAssembly target, these objects are lowered to WebAssembly
local variables, which are managed by the WebAssembly run-time and are
not addressable by linear memory.

For the WebAssembly target IR indicates that an AllocaInst should be put
on TargetStackID::WasmLocal by putting it in the non-integral address
space WASM_ADDRESS_SPACE_WASM_VAR, with value 1.  SROA will mostly lift
these allocations to SSA locals, but any alloca that reaches instruction
selection (usually in non-optimized builds) will be assigned the new
TargetStackID there.  Loads and stores to those values are transformed
to new WebAssemblyISD::LOCAL_GET / WebAssemblyISD::LOCAL_SET nodes,
which then lower to the type-specific LOCAL_GET_I32 etc instructions via
tablegen patterns.

Differential Revision: https://reviews.llvm.org/D101140
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was addedllvm/test/CodeGen/WebAssembly/ir-locals-stackid.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISD.def
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/WebAssembly/ir-locals.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
Commit 818338add77411f5e9713247ea66142f332ef350 by hans
[clang] Add support for the "abstract" contextual keyword of MSVC

https://docs.microsoft.com/en-us/cpp/extensions/abstract-cpp-component-extensions?view=msvc-160
Note: like the already supported "sealed" keyword, the "abstract"
keyword is supported by MSVC by default.

Differential revision: https://reviews.llvm.org/D102517
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Sema/DeclSpec.h
The file was modifiedclang/test/SemaCXX/MicrosoftExtensions.cpp
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/Sema/DeclSpec.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was modifiedclang/include/clang/Parse/Parser.h
Commit bc1ad6e3c49dacea862ca6fa44297c64bb053ad8 by wingo
Revert "[WebAssembly][CodeGen] IR support for WebAssembly local variables"

This reverts commit bf35f4af51cddd743435bb6b94a45592c967891a.  There was
an error in a shared-library build.
The file was removedllvm/test/CodeGen/WebAssembly/ir-locals.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
The file was removedllvm/test/CodeGen/WebAssembly/ir-locals-stackid.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISD.def
Commit 37b530a2ea8bdc28a22a3f8ca701455fb7febdea by dmitry.polukhin
[clang] NFC: split HeaderMapTest to have re-usable header map implementation for testing

NFC changes required for https://reviews.llvm.org/D103142

Test Plan: check-clang

Differential Revision: https://reviews.llvm.org/D103229
The file was addedclang/unittests/Lex/HeaderMapTestUtils.h
The file was modifiedclang/unittests/Lex/HeaderMapTest.cpp
Commit eb2393659113696adf2bd770917f3109d1455c76 by fraser
[RISCV] Support vector conversions between fp and i1

This patch custom lowers FP_TO_[US]INT and [US]INT_TO_FP conversions
between floating-point and boolean vectors. As the default action is
scalarization, this patch both supports scalable-vector conversions and
improves the code generation for fixed-length vectors.

The lowering for these conversions can piggy-back on the existing
lowering, which lowers the operations to a supported narrowing/widening
conversion and then either an extension or truncation.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103312
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll