SuccessChanges

Summary

  1. [VectorCombine] Add tests with multiple noundef indices for scalarization. (details)
  2. [WebAssembly][CodeGen] IR support for WebAssembly local variables (details)
  3. [RISCV] Support vector types in combination with fastcc (details)
  4. [VectorCombine] Freeze index unless it is known to be non-poison. (details)
  5. [mlir][linalg] Fix signed/unsigned comparison warnings (NFC). (details)
  6. [mlir] Use interfaces in MathToLibm (details)
  7. [SDAG] add helper function for sext-of-setcc folds; NFC (details)
  8. [LoopDeletion] Consider infinite loops alive, unless mustprogress. (details)
  9. [compiler-rt] Fix compilation when multiple architectures can be targeted (details)
  10. [InstCombine] Relax constraints of uses for exp(X) * exp(Y) -> exp(X + Y) (details)
  11. [AMDGPU][Libomptarget] Remove g_atmi_machine global (details)
  12. [OpenCL] Fix ICE with invalid use of half (details)
  13. [clang][Parse] Add parsing support for C++ attributes on using-declarations (details)
  14. [llvm-dwarfdump][test] Add missing dedicated tests for some options (details)
  15. [SLP]Better detection of perfect/shuffles matches for gather nodes. (details)
  16. Simplify coro-zero-alloca.ll (details)
  17. [x86] add test for sext-of-setcc; NFC (details)
  18. [lldb] Remove SBCommandReturnObject::ref (details)
  19. [lldb][NFC] Use Language plugins in Mangled::GuessLanguage (details)
  20. [RISCV] Remove earlyclobber from compares with LMUL<=1. (details)
  21. [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. (details)
  22. [ADT] Move DenseMapInfo for APInt into APInt.h (PR50527) (details)
  23. [polly] Fix SCEVLoopAddRecRewriter to avoid invalid AddRecs. (details)
  24. [SystemZ] Return true from hasBitPreservingFPLogic(). (details)
  25. [MLIR] Add missing APSInt.h include (details)
  26. [X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB (details)
Commit f000c4cfb66ce5f86394920db35397d618c0855a by flo
[VectorCombine] Add tests with multiple noundef indices for scalarization.
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
Commit 82f92e35c6464e23859c29422956caaceb623967 by wingo
[WebAssembly][CodeGen] IR support for WebAssembly local variables

This patch adds TargetStackID::WasmLocal.  This stack holds locations of
values that are only addressable by name -- not via a pointer to memory.
For the WebAssembly target, these objects are lowered to WebAssembly
local variables, which are managed by the WebAssembly run-time and are
not addressable by linear memory.

For the WebAssembly target IR indicates that an AllocaInst should be put
on TargetStackID::WasmLocal by putting it in the non-integral address
space WASM_ADDRESS_SPACE_WASM_VAR, with value 1.  SROA will mostly lift
these allocations to SSA locals, but any alloca that reaches instruction
selection (usually in non-optimized builds) will be assigned the new
TargetStackID there.  Loads and stores to those values are transformed
to new WebAssemblyISD::LOCAL_GET / WebAssemblyISD::LOCAL_SET nodes,
which then lower to the type-specific LOCAL_GET_I32 etc instructions via
tablegen patterns.

Differential Revision: https://reviews.llvm.org/D101140
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/MIRYamlMapping.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISD.def
The file was addedllvm/test/CodeGen/WebAssembly/ir-locals-stackid.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
The file was addedllvm/test/CodeGen/WebAssembly/ir-locals.ll
Commit 4f500c402b7357808d9595313438f223447dcace by fraser
[RISCV] Support vector types in combination with fastcc

This patch extends the RISC-V lowering of the 'fastcc' calling
convention to vector types, both fixed-length and scalable. Without this
patch, any function passing or returning vector types by value would
throw a compiler error.

Vectors are handled in 'fastcc' much as they are in the default calling
convention, the noticeable difference being the extended set of scalar
GPR registers that can be used to pass vectors indirectly.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D102505
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit d4c070d801413186c5a59cede9d721e9ca099708 by flo
[VectorCombine] Freeze index unless it is known to be non-poison.

If the index itself is already poison, the poison propagates through
instructions clamping the index to a valid range. This still causes
introducing a load of poison, as flagged by Alive2 and pointed out
at 575e2aff5574.

This patch updates the code to freeze the index, unless it is proven to
not be poison.

Reviewed By: nlopes

Differential Revision: https://reviews.llvm.org/D103378
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 07576cc4dc891294e31a8ff10ff08c662042c572 by gysit
[mlir][linalg] Fix signed/unsigned comparison warnings (NFC).

Fix signedness warnings in Utils.cpp and LinalgInterfaces.cpp.
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 1ebf7ce950bb72599055d2f2789fd604a02b6d15 by tpopp
[mlir] Use interfaces in MathToLibm

Previously, this assumed use of ModuleOp and FuncOp. There is no need to
restrict this, and using interfaces allows these patterns to be used
during dialect conversion to LLVM.

Some assertions were removed due to inconsistent implementation of
FunctionLikeOps.

Differential Revision: https://reviews.llvm.org/D103447
The file was modifiedmlir/lib/Conversion/MathToLibm/MathToLibm.cpp
Commit 1b14f3951a205536d95ce7fab5b9f57f9ffa2ee0 by spatel
[SDAG] add helper function for sext-of-setcc folds; NFC

Try to make this easier to read as noted in D103280
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 1b84acb23acac2fbb450312049495164a16ee715 by flo
[LoopDeletion] Consider infinite loops alive, unless mustprogress.

The current loop or any of its sub-loops may be infinite. Unless the
function or the loops are marked as mustprogress, this in itself makes
the loop *not* dead.

This patch moves the logic to check whether the current loop is finite
or mustprogress to `isLoopDead` and also extends it to check the
sub-loops. This should fix PR50511.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D103382
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
The file was modifiedllvm/test/Transforms/LoopDeletion/unreachable-loops.ll
Commit 7879fa6884723f35463de33cbe03b2acb93ea3cf by eleviant
[compiler-rt] Fix compilation when multiple architectures can be targeted

When toolchain can supports all of arm, armhf and armv6m architectures compiler-rt
libraries won't compile because architecture specific flags are appended to single
BUILTIN_CFLAGS variable.

Differential revision: https://reviews.llvm.org/D103363
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt
Commit 13140120dcca64c35508880e10e14bcee3c54a58 by spatel
[InstCombine] Relax constraints of uses for exp(X) * exp(Y) -> exp(X + Y)

InstCombine didn't perform the transformations when fmul's operands were
the same instruction because it required to have one use for each of them
which is false in the case. This patch fixes this + adds tests for them
and introduces a new function isOnlyUserOfAnyOperand to check these cases
in a single place.

This patch is a result of discussion in D102574.

Differential Revision: https://reviews.llvm.org/D102698
The file was modifiedllvm/test/Transforms/InstCombine/fmul-exp.ll
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/test/Transforms/InstCombine/fmul-exp2.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Commit fb113264a8da1d8e456e64f99920fac6b4fae548 by Pushpinder.Singh
[AMDGPU][Libomptarget] Remove g_atmi_machine global

Turns out the only purpose of this class was verify if device ID
was in range or not which could be done easily by using g_atl_machine.

Still getting rid of g_atl_machine is pending which would be done in
a later patch.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D103443
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/rt.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi_runtime.h
Commit 94b0aec0f5c6b4f6a27cf3a542f795bbba72e851 by olemarius.strohm
[OpenCL] Fix ICE with invalid use of half

Because half is limited to the `cl_khr_fp16` extension being enabled,
`DefaultLvalueConversion` can fail when it's not enabled.
The original assumption that it will never fail is therefore wrong now.

Fixes: PR47976

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D103175
The file was addedclang/test/SemaOpenCLCXX/half.clcpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
Commit 97d234935f1514af128277943f30efc469525371 by Louis Dionne
[clang][Parse] Add parsing support for C++ attributes on using-declarations

This is a re-application of dc67299 which was reverted in f63adf5b because
it broke the build. The issue should now be fixed.

Attribution note: The original author of this patch is Erik Pilkington.
I'm only trying to land it after rebasing.

Differential Revision: https://reviews.llvm.org/D91630
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/include/clang/Basic/Features.def
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was addedclang/test/SemaCXX/cxx11-attributes-on-using-declaration.cpp
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/test/Parser/cxx0x-attributes.cpp
Commit e60f147324b64f7740de58e6b936cdc0e26daadd by gbreynoo
[llvm-dwarfdump][test] Add missing dedicated tests for some options

This change adds tests specifically for --parent-recurse-depth, --quiet
and -o. The test for -o found a typo in an error message which is also
fixed in this change.

Differential Revision: https://reviews.llvm.org/D103250
The file was addedllvm/test/tools/llvm-dwarfdump/X86/quiet.s
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was addedllvm/test/tools/llvm-dwarfdump/X86/parent_recurse_depth.s
The file was addedllvm/test/tools/llvm-dwarfdump/X86/output.s
Commit 36911971a58d1ba8b15e97790ac816eaadb0603e by a.bataev
[SLP]Better detection of perfect/shuffles matches for gather nodes.

Implemented better scheme for perfect/shuffled matches of the gather
nodes which allows to fix the performance regressions introduced by
earlier patches. Starting detecting matches for broadcast nodes and
extractelement gathering.

Differential Revision: https://reviews.llvm.org/D102920
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
Commit 41d08541e88467992ff6116cfcf18190a10402b3 by lxfind
Simplify coro-zero-alloca.ll

D101841 added this test. It appears to generate different outcome on different platforms.
Make it to only call -coro-split instead of entire O2 pipeline to simplify the test flow.
Hope this will make  the test more robust.

Reviewed By: djtodoro

Differential Revision: https://reviews.llvm.org/D103418
The file was modifiedllvm/test/Transforms/Coroutines/coro-zero-alloca.ll
Commit de65b1ab7de1f4651d930d8f445167918ebf9908 by spatel
[x86] add test for sext-of-setcc; NFC
The file was modifiedllvm/test/CodeGen/X86/sext-vsetcc.ll
Commit 01fb14e17763269779f2c03b772db960540f47ed by Raphael Isemann
[lldb] Remove SBCommandReturnObject::ref

This function was added in D67589 and returns an internal CommandReturnObject
which isn't allowed in the SB API. This patch just makes it private as all uses
of this function are inside SBCommandReturnObject.

Reviewed By: jankratochvil

Differential Revision: https://reviews.llvm.org/D103390
The file was modifiedlldb/include/lldb/API/SBCommandReturnObject.h
Commit ecfca427f9601a7789c0703582cff92e7a3277c0 by Raphael Isemann
[lldb][NFC] Use Language plugins in Mangled::GuessLanguage

This removes the direct dependency to the ObjC and C++ plugins.

Reviewed By: bulbazord

Differential Revision: https://reviews.llvm.org/D103158
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
The file was modifiedlldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.h
The file was modifiedlldb/source/Plugins/Language/ObjC/ObjCLanguage.h
The file was modifiedlldb/include/lldb/Target/Language.h
The file was modifiedlldb/source/Core/Mangled.cpp
Commit 5a5219a0f961b91253dc3fdb4b33e088b199b451 by craig.topper
[RISCV] Remove earlyclobber from compares with LMUL<=1.

Compares are considered a narrowing operation for register overlap.
I believe for LMUL<=1 they meet this exception to allow overlap

"The destination EEW is smaller than the source EEW and the overlap is in the
lowest-numbered part of the source register group"

Both the result and the sources will occupy a single register for
LMUL<=1 so the overlap would always be in the "lowest-numbered part".

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D103336
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/select-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
Commit 896f9bc350eba0baf17f1ceae7383d88f0ce2a85 by craig.topper
[RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register.

This guarantees they meet this overlap exception:

"The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group"

Being a single register guarantees the overlap is always in the
lowerst-number part of the group.

Reviewed By: frasercrmck, khchen

Differential Revision: https://reviews.llvm.org/D103351
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
Commit fd7e309e02fd226b0390888388ed732608e52c73 by nikita.ppv
[ADT] Move DenseMapInfo for APInt into APInt.h (PR50527)

As suggested in https://bugs.llvm.org/show_bug.cgi?id=50527, this
moves the DenseMapInfo for APInt and APSInt into the respective
headers, removing the need to include APInt.h and APSInt.h from
DenseMapInfo.h.

We could probably do the same from StringRef and ArrayRef as well.

Differential Revision: https://reviews.llvm.org/D103422
The file was modifiedllvm/include/llvm/ADT/APInt.h
The file was modifiedllvm/lib/Support/APInt.cpp
The file was modifiedllvm/include/llvm/ADT/DenseMapInfo.h
The file was modifiedllvm/include/llvm/ADT/APSInt.h
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
Commit fd229caa0138d296090c101655c82ca7da58ddd6 by efriedma
[polly] Fix SCEVLoopAddRecRewriter to avoid invalid AddRecs.

When we're remapping an AddRec, the AddRec constructed by a partial
rewrite might not make sense.  This triggers an assertion complaining
it's not loop-invariant.

Instead of constructing the partially rewritten AddRec, just skip
straight to calling evaluateAtIteration.

Testcase was automatically reduced using llvm-reduce, so it's a little
messy, but hopefully makes sense.

Differential Revision: https://reviews.llvm.org/D102959
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
The file was addedpolly/test/Isl/CodeGen/OpenMP/scev-rewriting.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 9ee3f16919acb753d011290446efd12bc59d9605 by paulsson
[SystemZ] Return true from hasBitPreservingFPLogic().

This is currently NFC on benchmarks and tests.

Review: Ulrich Weigand
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.h
Commit bd0a9880d02f12df8374e05e67b0d95a7af939d7 by nikita.ppv
[MLIR] Add missing APSInt.h include

Since fd7e309e02fd226b0390888388ed732608e52c73 this is no longer
pulled in indirectly through DenseMapInfo.h.
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
Commit 1b748faf2bae246e2fc77d88420df13c2e60f4df by carrot
[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB

This patch transforms the sequence

    lea (reg1, reg2), reg3
    sub reg3, reg4

to two sub instructions

    sub reg1, reg4
    sub reg2, reg4

Similar optimization can also be applied to LEA/ADD sequence.
The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register of ADD).

Differential Revision: https://reviews.llvm.org/D101970
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
The file was modifiedllvm/test/CodeGen/X86/lea-opt2.ll
The file was modifiedllvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/lib/Target/X86/X86FixupLEAs.cpp