SuccessChanges

Summary

  1. [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF (details)
  2. [libcxx][ranges] removes default_initializable from weakly_incrementable and view (details)
  3. Preserve more MD_mem_parallel_loop_access and MD_access_group in SROA (details)
  4. [clang] Implement P2266 Simpler implicit move (details)
  5. [Profile] Handle invalid profile data (details)
  6. [IR] make -warn-frame-size into a module attr (details)
  7. [Profile] Remove redundant check (details)
  8. LoadStoreVectorizer: support different operand orders in the add sequence match (details)
  9. [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. (details)
  10. [IR] Value: Fix OpCode checks (details)
  11. [RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC (details)
  12. [SDAG] Fix pow2 assumption when splitting vectors (details)
  13. [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32 (details)
  14. [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. (details)
  15. [mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file (details)
  16. [mlir] Add new SubElementAttr/SubElementType Interfaces (details)
  17. [mlir-ir-printing] Prefix the dump message with the split marker(// -----) (details)
  18. [Flang] Compile fix after D99459. (details)
  19. [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. (details)
  20. [VectorCombine] Fix alignment in single element store (details)
  21. Revert "[clang] Implement P2266 Simpler implicit move" (details)
  22. Revert "[clang] NRVO: Improvements and handling of more cases." (details)
  23. [RISCV] Remove extra assignment of intrinsic ID in ManualCodegen. NFC (details)
Commit 933df6ca796c0ace889bcc64706ec53462bd859a by Jessica Paquette
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF

This adds legalization for scalar G_CTTZ and G_CTTZ_ZERO_UNDEF. Vector support
requires handling vector G_BITREVERSE, which I haven't gotten around to yet.

For G_CTTZ_ZERO_UNDEF, we just lower it to G_CTTZ.

For G_CTTZ, we match SelectionDAG's lowering to a G_BITREVERSE + G_CTLZ.

e.g. https://godbolt.org/z/nPEseYh1s

(With this patch, we have slightly worse codegen than SDAG for types smaller
than s32; it seems like we're missing a combine.)

Also, this adds in a function to build G_BITREVERSE to MachineIRBuilder.

Differential Revision: https://reviews.llvm.org/D104065
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
Commit 462f8f06113616ac5646144972d3f453639aac69 by cjdb
[libcxx][ranges] removes default_initializable from weakly_incrementable and view

also:

* removes default constructors from predefined iterators
* makes span and string_view views

Partially implements P2325.
Partially resolves LWG3326.

Differential Revision: https://reviews.llvm.org/D102468
The file was modifiedlibcxx/include/string_view
The file was modifiedlibcxx/test/std/containers/views/range_concept_conformance.compile.pass.cpp
The file was removedlibcxx/test/std/iterators/stream.iterators/ostreambuf.iterator/ostreambuf.iter.cons/default.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.req/range.view/view.subsumption.compile.pass.cpp
The file was modifiedlibcxx/docs/Cxx2aStatusIssuesStatus.csv
The file was modifiedlibcxx/include/__ranges/enable_view.h
The file was removedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.winc/subsumption.compile.pass.cpp
The file was modifiedlibcxx/include/span
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iter.ops/front.insert.iter.cons/default.pass.cpp
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iter.ops/insert.iter.cons/default.pass.cpp
The file was modifiedlibcxx/include/__iterator/concepts.h
The file was modifiedlibcxx/include/iterator
The file was removedlibcxx/test/std/iterators/stream.iterators/ostream.iterator/ostream.iterator.cons.des/default.pass.cpp
The file was modifiedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.winc/weakly_incrementable.compile.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.req/range.view/view.compile.pass.cpp
The file was modifiedlibcxx/test/std/strings/string.view/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was removedlibcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iter.ops/back.insert.iter.cons/default.pass.cpp
The file was modifiedlibcxx/docs/Cxx2aStatusPaperStatus.csv
Commit 41555eaf65b12db00c8a18e7fe530f72ab9ebfc0 by andrew.kaylor
Preserve more MD_mem_parallel_loop_access and MD_access_group in SROA

SROA sometimes preserves MD_mem_parallel_loop_access and MD_access_group metadata on loads/stores, and sometimes fails to do so. This change adds copying of the MD after other CreateAlignedLoad/CreateAlignedStores. Also fix a case where the metadata was being copied from a load, rather than the store.

Added a LIT test to catch one case.

Patch by Mark Mendell

Differential Revision: https://reviews.llvm.org/D103254
The file was addedllvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
Commit cbd0054b9eb17ec48f0702e3828209646c8f5ebd by mizvekov
[clang] Implement P2266 Simpler implicit move

This Implements [[http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2021/p2266r1.html|P2266 Simpler implicit move]].

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: Quuxplusone

Differential Revision: https://reviews.llvm.org/D99005
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p7-cxx14.cpp
The file was modifiedclang/test/SemaCXX/deduced-return-type-cxx14.cpp
The file was modifiedclang/test/SemaCXX/warn-return-std-move.cpp
The file was modifiedclang/test/CXX/class/class.init/class.copy.elision/p3.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/test/CXX/temp/temp.decls/temp.mem/p5.cpp
The file was modifiedclang/test/SemaCXX/return-stack-addr.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p4-cxx14.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/SemaCXX/coroutine-rvo.cpp
The file was modifiedclang/test/SemaCXX/coroutines.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx11.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/test/CXX/drs/dr3xx.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx14.cpp
Commit 189428c8fc2465c25efbf4f0bb73e26fecf150ce by aeubanks
[Profile] Handle invalid profile data

This mostly follows LLVM's InstrProfReader.cpp error handling.
Previously, attempting to merge corrupted profile data would result in
crashes. See https://crbug.com/1216811#c4.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D104050
The file was modifiedcompiler-rt/test/profile/instrprof-without-libc.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingMerge.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
The file was addedcompiler-rt/test/profile/Linux/corrupted-profile.c
The file was modifiedcompiler-rt/test/profile/Linux/instrprof-merge-vp.c
The file was modifiedcompiler-rt/lib/profile/InstrProfiling.h
The file was modifiedcompiler-rt/test/profile/instrprof-merge.c
Commit fc018ebb608ee0c1239b405460e49f1835ab6175 by ndesaulniers
[IR] make -warn-frame-size into a module attr

-Wframe-larger-than= is an interesting warning; we can't know the frame
size until PrologueEpilogueInsertion (PEI); very late in the compilation
pipeline.

-Wframe-larger-than= was propagated through CC1 as an -mllvm flag, then
was a cl::opt in LLVM's PEI pass; this meant it was dropped during LTO
and needed to be re-specified via -plugin-opt.

Instead, make it part of the IR proper as a module level attribute,
similar to D103048. Introduce -fwarn-stack-size CC1 option.

Reviewed By: rsmith, qcolombet

Differential Revision: https://reviews.llvm.org/D103928
The file was modifiedllvm/include/llvm/IR/Module.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Frontend/backend-diagnostic.c
The file was modifiedllvm/lib/IR/Module.cpp
The file was modifiedclang/test/Misc/backend-stack-frame-diagnostics-fallback.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was addedclang/test/Driver/Wframe-larger-than.c
The file was modifiedllvm/test/CodeGen/X86/warn-stack.ll
The file was addedllvm/test/Linker/warn-stack-frame.ll
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was modifiedllvm/test/CodeGen/ARM/warn-stack.ll
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit b73742bc8d2ec53f0892f1609837c088f9cfcf64 by aeubanks
[Profile] Remove redundant check

This is already checked outside the loop.

Followup to D104050.
The file was modifiedcompiler-rt/lib/profile/InstrProfilingMerge.c
Commit 119965865cc730060e4cc95690ee7dab91c2c440 by vkeles
LoadStoreVectorizer: support different operand orders in the add sequence match

First we refactor the code which does no wrapping add sequences
match: we need to allow different operand orders for
the key add instructions involved in the match.

Then we use the refactored code trying 4 variants of matching operands.

Originally the code relied on the fact that the matching operands
of the two last add instructions of memory index calculations
had the same LHS argument. But which operand is the same
in the two instructions is actually not essential, so now we allow
that to be any of LHS or RHS of each of the two instructions.
This increases the chances of vectorization to happen.

Reviewed By: volkan

Differential Revision: https://reviews.llvm.org/D103912
The file was modifiedllvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
Commit 5a1589fc6d1131e6d73c498cc5987433d1c5e098 by wolfgang_pieb
[static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used.

Reviewed By: rnk, MaskRay, efriedma

Differential Revision: https://reviews.llvm.org/D103495
The file was modifiedllvm/test/CodeGen/SPARC/constructor.ll
The file was modifiedllvm/test/CodeGen/X86/constructor.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/X86/2011-08-29-InitOrder.ll
Commit ffaca140d01b0b93723c3322b08351b03b95831f by ndesaulniers
[IR] Value: Fix OpCode checks

Value::SubclassID cannot be directly compared to Instruction enums, such as
Instruction::{Call,Invoke,CallBr}. We have to first subtract InstructionVal
from the SubclassID to get the OpCode, similar to Instruction::getOpCode().

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D104043
The file was modifiedllvm/lib/IR/Value.cpp
Commit b35a842581f089daa57dd7e6b78ccb08d92709b2 by craig.topper
[RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
Commit cfbb92441f17d1f5a9d9c3e195646df4117cb0ca by carl.ritson
[SDAG] Fix pow2 assumption when splitting vectors

When reducing vector builds to shuffles it possible that
the DAG combiner may try to extract invalid subvectors.

This happens as the existing code assumes vectors will be power
of 2 sizes, which is already untrue, but becomes more noticable
with v6 and v7 types.
Specifically the existing code assumes that half PowerOf2Ceil of
a given vector index will fit twice into a given vector.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103880
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 2c2d2922a24b7fa8a92f38d9043ab476d330210d by carl.ritson
[ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32

For use in AMDGPU selection DAG.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103881
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
Commit 670edf3ee0045ce007f2f6aec94a2c3344c5682e by Amara Emerson
[AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.

When the extend is from 8 or 16 bits, the addressing modes don't support those
extensions, but we weren't checking that and therefore always generated the 32->64b
extension mode. Fun.

Differential Revision: https://reviews.llvm.org/D104070
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit f8a1d652da00ecff448213c58522da5a61d9bc4b by riddleriver
[mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file

This allows for using other type interfaces in the builtin dialect, which currently results in a compile time failure (as it generates duplicate interface declarations).
The file was modifiedmlir/lib/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt
The file was addedmlir/include/mlir/IR/BuiltinTypeInterfaces.td
Commit c42dd5dbb015afaef99cf876195c474c63c2393e by riddleriver
[mlir] Add new SubElementAttr/SubElementType Interfaces

These interfaces allow for a composite attribute or type to opaquely provide access to any held attributes or types. There are several intended use cases for this interface. The first of which is to allow the printer to create aliases for non-builtin dialect attributes and types. In the future, this interface will also be extended to allow for SymbolRefAttr to be placed on other entities aside from just DictionaryAttr and ArrayAttr.

To limit potential test breakages, this revision only adds the new interfaces to the builtin attributes/types that are currently hardcoded during AsmPrinter alias generation. In a followup the remaining builtin attributes/types, and non-builtin attributes/types can be extended to support it.

Differential Revision: https://reviews.llvm.org/D102945
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/lib/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
The file was addedmlir/include/mlir/IR/SubElementInterfaces.h
The file was addedmlir/include/mlir/IR/SubElementInterfaces.td
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h
The file was addedmlir/lib/IR/SubElementInterfaces.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td
The file was modifiedmlir/unittests/IR/CMakeLists.txt
The file was addedmlir/unittests/IR/SubElementInterfaceTest.cpp
Commit 8800047707a9cd86fb7143699af0e5564c28f4aa by riddleriver
[mlir-ir-printing] Prefix the dump message with the split marker(// -----)

This allows for better interaction with tools (such as mlir-lsp-server), as it separates the IR into separate modules for consecutive dumps.

Differential Revision: https://reviews.llvm.org/D104073
The file was modifiedmlir/test/Pass/ir-printing.mlir
The file was modifiedmlir/lib/Pass/IRPrinting.cpp
The file was modifiedmlir/test/Pass/run-reproducer.mlir
Commit 7836d058c7e115eace62e324ef6c01670326f518 by llvm-project
[Flang] Compile fix after D99459.

Fix Flang build after addition of a new OpenMP clauses for a Clang
patch (D99459). Flang is using TableGen to generation the declaration
of clause checks and the new clause was missing a definiton.
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
Commit 420bd5ee8ec996a2c2e305541e59465a5ba436e3 by craig.topper
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rem.ll
Commit 2670c7dd5b25e87825edc0aca7729c1d3dba5afc by qiucofan
[VectorCombine] Fix alignment in single element store

This fixes the concern in single element store scalarization that the
alignment of new store may be larger than it should be. It calculates
the largest alignment if index is constant, and a safe one if not.

Reviewed By: lebedev.ri, spatel

Differential Revision: https://reviews.llvm.org/D103419
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
Commit db26615aa6a165483e6540b3f6ed684a0cbe06df by aeubanks
Revert "[clang] Implement P2266 Simpler implicit move"

This reverts commit cbd0054b9eb17ec48f0702e3828209646c8f5ebd.
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/test/CXX/temp/temp.decls/temp.mem/p5.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx14.cpp
The file was modifiedclang/test/SemaCXX/coroutines.cpp
The file was modifiedclang/test/SemaCXX/return-stack-addr.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx11.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p7-cxx14.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/SemaCXX/coroutine-rvo.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/test/SemaCXX/warn-return-std-move.cpp
The file was modifiedclang/test/SemaCXX/deduced-return-type-cxx14.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p4-cxx14.cpp
The file was modifiedclang/test/CXX/class/class.init/class.copy.elision/p3.cpp
The file was modifiedclang/test/CXX/drs/dr3xx.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit 85ca7e424fd050582026a299906c9e8397043c52 by aeubanks
Revert "[clang] NRVO: Improvements and handling of more cases."

This reverts commit 667fbcdd0b2ee5e78f5ce9789b862e3bbca94644.

Causes crashes on a stage 2 build on Windows.
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/test/CodeGen/nrvo-tracking.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
Commit 081ae5fe1aa3ead6d9da75747d3698f09ff89cb9 by craig.topper
[RISCV] Remove extra assignment of intrinsic ID in ManualCodegen. NFC

There's already an autogenerated assignment.

Fixes static analyzer warning reported in PR50593.
The file was modifiedclang/include/clang/Basic/riscv_vector.td