1. [mlir][sparse] add sparse tensor type conversion operation (details)
  2. [ConstantFold] Get rid of special cases for sizeof etc. (details)
  3. Fix a couple regression tests I missed updating in 2a284782 (details)
  4. Fix the default alignment of i1 vectors. (details)
  5. [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. (details)
  6. [RISCV][Docs] Add description about inline asm constraint for V. (details)
  7. [nfc] [lldb] Removed unused DWARFDebugInfo::GetDIEForDIEOffset (details)
  8. [GlobalOpt] support ConstantExpr use of global address for OptimizeGlobalAddressOfMalloc (details)
Commit 697ea09d47a93d92e40990a38fccf9e246cc22e6 by ajcbik
[mlir][sparse] add sparse tensor type conversion operation

Introduces a conversion from one (sparse) tensor type to another
(sparse) tensor type. See the operation doc for details. Actual
codegen for all cases is still TBD.

Reviewed By: ThomasRaoux

Differential Revision:
The file was modifiedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/invalid.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
Commit 2a2847823f0d13188c43ebdd0baf42a95df750c7 by efriedma
[ConstantFold] Get rid of special cases for sizeof etc.

Target-dependent constant folding will fold these down to simple
constants (or at least, expressions that don't involve a GEP).  We don't
need heroics to try to optimize the form of the expression before that

Fixes .

Differential Revision:
The file was modifiedllvm/lib/IR/ConstantFold.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/for_reduction_codegen.cpp
The file was modifiedclang/test/CodeGenCXX/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp
The file was modifiedllvm/test/tools/llvm-as/slow-ptrtoint.ll
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
The file was modifiedllvm/test/Other/constant-fold-gep.ll
The file was modifiedclang/test/OpenMP/taskloop_reduction_codegen.cpp
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset-in-offsetof-idiom.c
The file was modifiedllvm/test/Transforms/LowerTypeTests/function-disjoint.ll
Commit 6eb2ffbaeb56c8b08ad17c823e1699b964e10b8b by efriedma
Fix a couple regression tests I missed updating in 2a284782
The file was modifiedclang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
The file was modifiedmlir/test/Target/LLVMIR/openacc-llvm.mlir
Commit bdd55b2f1810eb5a2474a36229d08a9e5ca870fc by efriedma
Fix the default alignment of i1 vectors.

Currently, the default alignment is much larger than the actual size of
the vector in memory.  Fix this to use a sane default.

For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.

This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway.  If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).

Differential Revision:
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-load.ll
The file was modifiedllvm/test/CodeGen/NVPTX/f16x2-instructions.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
The file was modifiedllvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
The file was modifiedllvm/lib/Target/AArch64/
The file was modifiedllvm/test/CodeGen/AMDGPU/lower-kernargs.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
The file was modifiedllvm/test/CodeGen/X86/avx512-select.ll
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
The file was modifiedllvm/test/CodeGen/X86/vector-sext.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
The file was modifiedllvm/test/CodeGen/NVPTX/param-load-store.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
The file was modifiedllvm/test/Transforms/InstCombine/abs-intrinsic.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-store.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-min-max.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll
The file was modifiedllvm/test/Transforms/SROA/vector-promotion-different-size.ll
The file was modifiedllvm/test/CodeGen/AArch64/spillfill-sve.ll
The file was modifiedllvm/test/CodeGen/X86/pr41619.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
The file was modifiedllvm/test/CodeGen/X86/load-local-v3i129.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp-vec.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-pair-mma.c
The file was modifiedllvm/lib/IR/DataLayout.cpp
Commit 8b33839f010fe780fdaf68160be7c45d07fdfcad by
[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision:
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/inline-asm.ll
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
The file was modifiedclang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
Commit ee3aef93b73646ef98f0241498d807a4fb68b78c by
[RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision:
The file was modifiedllvm/docs/LangRef.rst
Commit 6ef6616e07f5be69557e744fc28459d6051cfa9c by jan.kratochvil
[nfc] [lldb] Removed unused DWARFDebugInfo::GetDIEForDIEOffset

Its last use was removed by D63428.
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
Commit 732b05555c71cfdbf135a100a06472c5efc4eefb by scui
[GlobalOpt] support ConstantExpr use of global address for OptimizeGlobalAddressOfMalloc

I'm working on extending the OptimizeGlobalAddressOfMalloc to handle some more general cases. This is to add support of the ConstantExpr use of the global variables. The function allUsesOfLoadedValueWillTrapIfNull is now iterative with the added CE use of GV. Also, the recursive function valueIsOnlyUsedLocallyOrStoredToOneGlobal is changed to iterative using a worklist with the GEP case added.

Reviewed By: efriedma

Differential Revision:
The file was modifiedllvm/lib/Transforms/Utils/GlobalStatus.cpp
The file was addedllvm/test/Transforms/GlobalOpt/new-promote.ll
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp