Changes

Summary

  1. Enabling ccache for all ppc64 buildbots (details)
  2. Force HAVE_LIB_RT to NO when building with Xcode toolchains (details)
  3. Add new worker debian-tritium-mips64el for Linux 64-bit MIPS LE (details)
  4. [lldb] Enable libcxx(abi) and compiler-rt as runtimes (details)
Commit 0f1b47ed6bf17d7b5114d2c6d18e0b1900fe1805 by kamau.bridgeman.ibm
Enabling ccache for all ppc64 buildbots

This changed turns on the cmake variable that makes buildbots
build with ccache. Its intent is to use ccache to improve the
build times of the PowerPC 64-bit Big Endian buildbots.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D125890
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit 793716f3d6bfa3304ac06a1439320cbdb8f1c36e by Jon Roelofs
Force HAVE_LIB_RT to NO when building with Xcode toolchains

Fixes an issue revealed by https://reviews.llvm.org/D121343, causing several of
the test-suite-verify-machineinstrs* bots on GreenDragon to fail with:

  ld: library not found for -lrt

rdar://91014785

Differential revision: https://reviews.llvm.org/D125275

cherry-pick 33c34454f1 from llvm-test-suite
The file was modifiedtasks/cmake/caches/util/xcode_sdk.cmake (diff)
Commit e31efc974c5d03b559aadfc508fd7484a54932a5 by gkistanova
Add new worker debian-tritium-mips64el for Linux 64-bit MIPS LE

This adds a new builder called debian-tritium-mips64el which
will build LLVM and Clang on Debian unstable on mips64el.

Differential revision: https://reviews.llvm.org/D125872
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit 66fc9ebe900844ae810aabb2776f267db88a7b61 by Jonas Devlieghere
[lldb] Enable libcxx(abi) and compiler-rt as runtimes
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake (diff)

Summary

  1. [clang-tidy] Restore test parameter operator<< function (NFC) (details)
  2. [libc++] Simplify the string structures a bit more (details)
  3. [libc++][ranges][NFC] Mark completed issues related to the One Ranges Proposal. (details)
  4. [RISCV] Remove unneeded check for ISD::VSCALE operand being a constant. NFC (details)
  5. [mlir][LLVMIR] Add support for translating insert/extractvalue (details)
  6. [mlir][LLVMIR] Add support for translating shufflevector (details)
  7. Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h` (details)
  8. [M68k][Disassembler] Adopt the new variable length decoder (details)
  9. [LowerTypeTests][clang] Implement and allow -fsanitize=cfi-icall for RISCV (details)
  10. fix typos to cycle bots (details)
  11. [TargetLowering] expandCTPOP don't create an used constant mask for i8 ctpop. NFC (details)
  12. [libc++][test] Verify std::views::drop and std::views::join are CPOs (details)
  13. [clang-format] Handle "if consteval { ... }" for RemoveBracesLLVM (details)
  14. ARMFixCortexA57AES1742098Pass.cpp: Suppress a warning. [-Wunused-but-set-variable] (details)
  15. [clang][docs] Add escape code to fix missing '*' in reduction operation list (details)
  16. ScalarEvolution.cpp: Reformat. (details)
  17. [X86] Adjust tests for vector widening to use freeze(poison) (details)
  18. [X86] Add shuffles showing failure to use PERMUTE(BLEND(X,Y)) (details)
  19. [X86] lowerV4I64Shuffle - try harder to lower to PERMQ(BLENDD(V1,V2)) pattern (details)
  20. [X86] Pull out repeated isShuffleMaskInputInPlace calls. NFC. (details)
  21. [VPlan] Improve printing of VPReplicateRecipe with calls. (details)
  22. [X86] lowerShuffleAsLanePermuteAndSHUFP always succeeds, so just return the result. NFC. (details)
  23. [X86] Add checks to illegal-insert.ll (details)
  24. [X86] Add test coverage for PR44915 / Issue #44260 (details)
  25. [RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC (details)
  26. [RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC (details)
  27. [SLP] Fix misspelling of 'analyzed'. NFC (details)
  28. [flang][nfc] Fix driver method names overridden by the plugins (details)
  29. Revert "[libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE." (details)
  30. [DWARFLinker][NFC] cleanup AddressManager interface. (details)
  31. [X86] Adjust fadd costs to match SoG (details)
  32. [LV] Set SCEVCheckCond to nullptr whenever it was used. (details)
  33. [X86] Move combineAddOrSubToADCOrSBB earlier. NFC. (details)
  34. [mlir][bufferize] Infer memref types when possible (details)
  35. [RISCV] Fix incorrect use of tail agnostic vslideup. (details)
  36. [Diagnostic] Warn if the size argument of memset is character literal (details)
  37. [RISCV][NFC] Replace for-each with array argument call. (details)
  38. [LLVM][Casting.h] Add trivial self-cast (details)
  39. [clang] Prevent folding of non-const compound expr (details)
  40. [DivRemPairs][Mips] Pre-commit test for Mips target (details)
  41. [Mips] Implement hasDivRemOp() (details)
  42. [gn build] Port 0a0d6489ef2e (details)
  43. [RISCV][NFC] Refactor RISC-V vector intrinsic utils. (details)
  44. [clang-format] Fix PointerAlignment: Right not working with tab indentation. (details)
  45. [RISCV][NFC] Fix build issue (details)
  46. Add ThreadPriority::Low, and use QoS class Utility on Mac (details)
  47. [clangd] Include Cleaner: ignore headers with IWYU export pragmas (details)
  48. [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors (details)
  49. [clangd] NFC: Rename field to be compatible with the function name (details)
  50. [clang-format] fix alignment w/o binpacked args (details)
  51. [FastISel] Fix load folding for registers with fixups (details)
  52. [flang] Install Fortran_main library (details)
  53. [ControlHeightReduction] Freeze condition when converting select to branch (details)
  54. [pseudo] Support parsing variant target symbols. (details)
  55. [AMDGPU] Extract SIInstrInfo::removeModOperands. NFC. (details)
  56. [AMDGPU] SIShrinkInstructions: change static functions to methods (details)
  57. [llvm-c] Add functions for enabling and creating opaque pointers (details)
  58. [clangd] parse all make_unique-like functions in preamble (details)
  59. [clang-format][NFC] Don't call mightFitOnOneLine() unnecessarily (details)
  60. [StatepointLowering] Properly handle local and non-local relocates of the same value. (details)
  61. [AArch64] Handle 64bit vectors in tryCombineFixedPointConvert (details)
  62. [SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags. (details)
  63. [X86][AVX] Add test showing poor expansion of bit-reversal permutation shuffles (details)
  64. [AMDGPU][GlobalISel] Pre-commit tests for D125516 (details)
  65. [GlobalISel] Handle constant splat in funnel shift combine (details)
  66. [ADT] Adopt the new casting infrastructure for PointerUnion (details)
  67. [lldb][NFC] Make cmd a reference in GenerateOptionUsage (details)
  68. [lldb][NFC] Simplify GenerateOptionUsage (details)
  69. AArch64: support ISel for fence instructions (details)
  70. [DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine (details)
  71. [InstCombine] Combine instructions of type or/and where AND masks can be combined. (details)
  72. [AST] Cleanup on getting the underlying decl of using-shdow decl. (details)
  73. [clang][NFC] Cleanup some coroutine tests (details)
  74. [runtimes] Introduce object libraries (details)
  75. [RISCV] remove useless code (details)
  76. [runtimes] Generalize how we reorder projects (details)
  77. [CodeGen] Use ArrayRef in TargetLowering functions (details)
  78. [clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVisitors (details)
  79. Apply clang-tidy fixes for performance-move-const-arg in SerializeToHsaco.cpp (NFC) (details)
  80. Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cpp (NFC) (details)
  81. [MSVC] Add support for pragma alloc_text (details)
  82. [AMDGPU] gfx11 BUF Instructions (details)
  83. [ConstantRange] Add toKnownBits() method (details)
  84. [AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10 (details)
  85. [AMDGPU] Mark sendmsg hasSideEffects. NFC (details)
  86. [LAA,LV] Add initial support for pointer-diff memory checks. (details)
  87. [ValueTracking] Handle and/or on RHS of isImpliedCondition() (details)
  88. [SLP]Check if the root of the buildvector has one use only. (details)
  89. [InstCombine] fix test name; NFC (details)
  90. [PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC (details)
  91. [AArch64] Update check lines in arm64-scvt.ll. NFC (details)
  92. [polly] Remove 'using namespace llvm/polly' from ScopGraphPrinter.h header. (details)
  93. [LiveIntervals] Add range accessors for value numbers [nfc] (details)
  94. [IR] create and use helper functions that test the signbit; NFCI (details)
  95. [InstrProf][NFC] Save profile bias to function map (details)
  96. [mlir][bufferize] Better user control of layout maps (details)
  97. [llvm-profgen] Update callsite body samples by summing up all call target samples. (details)
  98. [RISCV] Add further trace output to InsertVSETLVI (details)
  99. [DAGCombiner] Fix incorrect indentation. NFC (details)
  100. [TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift. (details)
  101. [AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC (details)
  102. [InstCombine] add tests for zext-of-signbit test; NFC (details)
  103. [InstCombine] invert canonicalization for cast of signbit test (details)
  104. [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32 (details)
  105. Remove stale file from modulemap (details)
  106. [llvm-objdump] Let --symbolize-operands symbolize basic block addresses based on the SHT_LLVM_BB_ADDR_MAP section. (details)
  107. [docs] Re-generate ClangCommandLineReference.rst (details)
  108. [Driver] Change "zlib not installed" diagnostic to "zlib not enabled" (details)
  109. [mlir:toy][NFC] Remove unnecessary trailing return type (details)
  110. [WebAssembly][TableGen][NFCI] Use getValueAsBit rather than converting TableGen 'bit' to string (details)
  111. Add documentHighlight in clangd check for performance measurements. (details)
  112. [AMDGPU] Revert wide LDS DMA support. (details)
  113. [AIX] fixed llvm-ar can not read empty big archive correctly. (details)
  114. [mlir][tosa] Use math.ctlz intrinsic for tosa.clz (details)
  115. Optimise findRefs for XRefs and docHighlights (details)
  116. [sanitizer] Don't use newfstatat for Linux on SPARC (details)
  117. [libc++] Remove the legacy LIBCXX_LIBCPPABI_VERSION option (details)
  118. [libc++] Remove overly conservative error in <stdatomic.h> (details)
  119. [SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes. (details)
  120. [DomPrinter] Migrate -dot-dom to the new pass manager. (details)
  121. [mlir][sparse] introduce complex type to sparse tensor support (details)
  122. [mlir][ods] Ignore AttributeSelfTypeParameter in assembly formats (details)
  123. [AIX] llvm-link support big archive. (details)
  124. [mlir][transforms] Add a topological sort utility and pass (details)
  125. [mlir] Remove the `type` keyword from type alias definitions (details)
  126. [mlir][ods] Fix verification of attribute + colon type ambiguity (details)
  127. [mlir][bufferize] Better propagation of errors (details)
  128. [InstrProf] Fix promoter when using counter relocations (details)
  129. [AArch64] Use ADDV for boolean xor reductions. (details)
  130. [compiler-rt builtins] Assert that atomic.c can be compiled correctly. (details)
  131. [ARM] Rename the isARMAreaXRegister parameter isIOS to SplitFramePushPop. NFC. (details)
  132. [MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog (details)
  133. [MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64 (details)
  134. Revert "[InstCombine] invert canonicalization for cast of signbit test" (details)
  135. [lldb] Prevent underflow in crashlog.py (details)
  136. [mlir] allow for re-registering extension ops (details)
  137. [Libomptarget] Don't build the device runtime without a new Clang (details)
  138. [OpenMP] Don't build the offloading driver without a source input (details)
  139. [NFC] Don't bother with unstripped binary w/ dSYM, don't DebugSymbols twice (details)
  140. [mlir] Restrict dialect doc gen to a single dialect (details)
  141. [mlir][sparse] Enhancing sparse=>sparse conversion. (details)
  142. [mlir][sparse] Adding "final" keyword wherever appropriate (details)
  143. [clang] Avoid suggesting typoed directives in `.S` files (details)
  144. [mlir][Tablegen-LSP] Add support for a basic TableGen language server (details)
  145. [llvm-objcopy][test] Add cmp after copy (details)
  146. [mlir][NFC] Fix a few langref typos (details)
  147. [llvm-ar][NFC] Address post-commit comments on D125439. (details)
  148. Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV) (details)
  149. [mlir][sparse] Restyling macros in the runtime library (details)
  150. [mlir][PDLL] Tweak the grammar to highlight partial code better (details)
  151. [mlir][NFC] Fix the tags for various doc code blocks (details)
  152. [lld-macho] Demangle symbol names in export-symbol error messages when -demangle is specified. (details)
  153. [dwarf] Emit a DIGlobalVariable for constant strings. (details)
  154. [test-suite][cmake] sort unit test targets (details)
  155. [RISCV] Fix missing vsetvli in transparent block case (details)
  156. [RISCV] Use classic dataflow for VSETVLI insertion (details)
  157. [lld-macho] Temporarily disable test on windows (details)
  158. [nfc][lld-macho] Fixed test from https://reviews.llvm.org/D125732 (details)
  159. [WebAssembly] Update relaxed SIMD opcodes and names (details)
  160. [mlir][sparse] Moved _mlir_ciface_newSparseTensor closer to its macros (details)
  161. [nfc][lld-macho] Follow up fixes to bd9e46815d73e4236c207bad8b5c54e7188154d7 (details)
  162. Revert "[dwarf] Emit a DIGlobalVariable for constant strings." (details)
  163. [Frontend] [Coroutines] Emit error when we found incompatible allocation (details)
  164. [mlir][LLVMIR] Add support for translating insertelement/extractelement. (details)
  165. [RISCV] Support getHostCpuName for sifive-u74 (details)
  166. [flang][OpenMP] Support lowering to MLIR for ordered clause (details)
  167. [flang] Add one semantic check for elemental call arguments (details)
  168. [KnownBits] Add operator== (details)
  169. [StackColoring] Don't merge slots with differing StackIDs (details)
  170. [RISCV] Add a test w/ RVV stack objects misaligning non-RVV ones (details)
  171. [ConstantRange] Implement binaryXor() using known bits (details)
  172. [CVP] Add test for xor (NFC) (details)
  173. [LVI] Compute range for xor (details)
  174. [XCOFF] support writing sections, relocations and symbols for XCOFF64. (details)
  175. [llvm] Fix typo for libxml2 detection (details)
  176. [InstCombine] precommit tests for foldSelectToCopysign (details)
  177. [RISCV][NFC] Fix comment typos in split SP adjustment (details)
  178. [SelectionDAG] Support more VP reduction mask operation. (details)
  179. [mlir] support isa/cast/dyn_cast<Operation *>(operation) again (details)
  180. [RISCV][NFC] Reword split SP adjustment comments (details)
  181. [SROA] Precommit test for D124967 (details)
  182. [SROA] Avoid postponing rewriting load/store by ignoring lifetime intrinsics in partition's promotability checking (details)
  183. [DWARFLinker][NFC] Add None value to the DwarfLinkerAccelTableKind enum. (details)
  184. [JumpThreading] Don't pass DT to isGuaranteedNotToBeUndefOrPoison() (details)
  185. [OpenCL] Do not guard vload/store_half builtins (details)
  186. [X86] Attempt to fold EFLAGS into X86ISD::ADD/SUB ops (details)
  187. [WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string (details)
  188. [WebAssembly][NFC] Convert IsWasm64 instruction field to 'bit' from string (details)
  189. [JumpThreading] Regenerate test checks (NFC) (details)
  190. [AArch64] Extra tests useful for D-lane shuffles. NFC (details)
  191. [VPlan] Move usesScalars/onlyFirstLaneUsed to VPUser. (details)
  192. [mlir][Tablegen-LSP] Don't link with llvm dylib (details)
  193. [RegAllocGreedy] New hook regClassPriorityTrumpsGlobalness (details)
  194. [clang] Expose CoawaitExpr's operand in the AST (details)
  195. [libc++] Introduce LIBCXX_LIBRARY_VERSION (details)
  196. [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses (details)
  197. Enabling the detection of devtoolset-11 toolchain. (details)
  198. [pgo] Fix doc typo: thingswith -> things with (details)
  199. [SLP]Add an  extra check for select minmax reduction to avoid crash. (details)
  200. [pseudo] Add the missing ; terminal for module-declaration rule. (details)
  201. [concepts] Implement dcl.decl.general p4: No constraints on non-template funcs (details)
  202. Fix an unused variable warning in no-asserts build mode (details)
  203. [mlir][licm] Fix debug output with newlines (details)
  204. [mlir] vim: add bf16 type (details)
  205. Fix release note typo from 6da3d66f (details)
  206. [IRBuilder] Move insertvalue/extractvalue to fold infrastructure (details)
  207. [NFC][AIX] Reenable mri1.test (details)
  208. [RISCV] Drop notion of "strict" vsetvli compatibility (details)
  209. [clangd] Indexing of standard library (details)
  210. [gn build] Port ecaa4d9662c9 (details)
  211. [LV] Fetch vector loop region once and remember it (NFC). (details)
  212. [RISCV] Add a test showing incorrect RVV stack alignment (details)
  213. [InstCombine] remove cast-of-signbit to shift transform (details)
  214. Revert "[clangd] Indexing of standard library" (details)
  215. [gn build] Port 76ddbb1ca747 (details)
  216. Fix the std::string formatter to report errors in the case where the (details)
  217. [OpaquePtr][LLParser] Explicitly turn off opaque pointers if we see a star (details)
  218. [OpaquePtr][BitcodeReader] Explicitly turn off opaque pointers if we see a typed pointer (details)
  219. Revert "[llvm-objcopy][test] Add cmp after copy" (details)
  220. [lldb-vscode] Fix data race in lldb-vscode when running with ThreadSanitizer (details)
  221. [llvm][json] Fix UINT64 json parsing (details)
  222. [AMDGPU] Add a MIR test for D125567 (details)
  223. [clang-cl] Add /Zc:wchar_t- option (details)
  224. [LV] Regenerate check lines for some tests. (details)
  225. [Polly] Mark classes as final by default. NFC. (details)
  226. [AArch64] Teach perfect shuffles tables about D-lane movs (details)
  227. fix typo error in DivergenceAnalysis.h (details)
  228. [mlir][LLVMIR] Use a new way to verify GEPOp indices (details)
  229. [AMDGPU] Add intrinsics llvm.amdgcn.{raw|struct}.buffer.load.lds (details)
  230. [X86] Rename combineCONCAT_VECTORS\INSERT_SUBVECTOR\EXTRACT_SUBVECTOR to match Opcode name. NFCI. (details)
  231. [AMDGPU] Add test for no waitcnt before issuing LDS DMA. NFC. (details)
  232. [AMDGPU] gfx11 scalar alu instructions (details)
  233. [NFC][lldb][trace] Use uint64_t when decoding and enconding json (details)
  234. [RISCV] Enable strict assertions in InsertVSETVLI data flow (details)
  235. [clangd] Add command-line flag to set background indexing thread priority. (details)
  236. [mlir] Update LLVMIR Fastmath flags use of MLIR BitEnum functionality (details)
  237. [pseudo] benchmark cleanups. NFC (details)
  238. [InstCombine] fold more shuffles with FP<->Int cast operands (details)
  239. [libc] add sprintf (details)
  240. [RISCV] Canonicalize AVL=setvli to AVL=Imm or AVL=VLMAX (details)
  241. [clang][dataflow] Weaken guard to only check for storage location (details)
  242. Reland "[clangd] Indexing of standard library" (details)
  243. [RISCV] Minor reorganization of VSETVLIInfo::operator== for readability [NFC] (details)
  244. [gn build] Port ccdb56ac10ee (details)
  245. [AMDGPU] Enable FLAT LDS DMA on gfx9/10 before gfx940 (details)
  246. Revert "Reland "[clangd] Indexing of standard library"" (details)
  247. [AMDGPU] Add llvm.amdgcn.global.load.lds intrinsic (details)
  248. [gn build] Port 6aabf60f2fb7 (details)
  249. [trace][intelpt] Support system-wide tracing [4] - Support per core tracing on lldb-server (details)
  250. [trace][intelpt] Support system-wide tracing [5] - Disable/enable per-core tracing based on the process state (details)
  251. [trace][intelpt] Support system-wide tracing [6] - Break IntelPTCollector into smaller files and minor refactor (details)
  252. [gn build] Port 1188faa7ab4b (details)
  253. [gn build] Port 1f49714d3e19 (details)
  254. [clang][dataflow] Fix double visitation of nested logical operators (details)
  255. [libc] add snprintf (details)
  256. [docs][LangRef] Fix typo in llvm.smul.fix example (details)
  257. [RISCV] Add additional test coverage of 11a7e77c and related transforms (details)
  258. [BOLT][NFC] Move BinaryDominatorTree out of BinaryLoop header (details)
  259. [BOLT][NFC] Suppress unused variable warnings (details)
  260. [ConstantRange] Improve the implementation of binaryAnd (details)
  261. [pseudo] Design notes from discussion today. NFC (details)
  262. [mlir][SCF] Fix scf.while bufferization (details)
  263. Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow" (details)
  264. [mlir][tosa] Rework tosa.apply_scale lowering for 32-bit (details)
  265. [lld][ELF] Support BFD name elf32-avr (details)
  266. Precommit a test file for D84941 (details)
  267. [JumpThreading] Let ProcessImpliedCondition look into freeze instructions (details)
  268. [InstCombine] add tests for icmp-fsh (details)
  269. [NFC][AMDGPU][CodeGen] Use ArrayRef in TargetLowering functions (details)
  270. [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different (details)
  271. [BasicAA] Remove unneeded special case for malloc/calloc (details)
  272. [MLIR][Presburger] Attach values only to non-local identifiers in FAVC (details)
  273. [MLIR][Presburger] Cleanup getMaybeValues in FACV (details)
  274. Revert "[clang-format] Fix WhitespaceSensitiveMacros not being honoured when macro closing parenthesis is followed by a newline." (details)
  275. [ArgPromotion] Add unused-argument.ll test (NFC) (details)
  276. [llvm-readobj] Fix printing of Windows ARM unwind opcodes, add tests (details)
  277. [mlir:PDLL] Drop space as a completion commit character (details)
  278. [mlir:PDLL] Improve the location ranges of several expressions during parsing (details)
  279. [mlir:PDLL] Don't append / for directory code completion (details)
  280. [mlir][Canonicalize] Fix command-line options (details)
  281. [llvm-nm] Always use opaque pointers (PR55506) (details)
  282. [LoopUnroll] Avoid branch on poison for runtime unroll with multiple exits (details)
  283. [SCEVExpander] Expand umin_seq using freeze (details)
  284. [GreedyPatternRewriter] Avoid reversing constant order (details)
  285. [PowerPC] Treat llvm.fmuladd intrinsic as using CTR (details)
  286. [flang][Runtime] Use proper prototypes in Fortran_main. NFCI (details)
  287. [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes. (details)
  288. [flang][driver] Support parsing response files (details)
  289. [test, x86] Fix spurious x86-target-features.c failure (details)
  290. [LV] set Header earlier, use variable instead of repeated access (NFC). (details)
  291. [clang][ASTImporter] Add isNewDecl (details)
  292. [clang][analyzer][ctu] Make CTU a two phase analysis (details)
  293. [JumpThreading] Use common code to skip freeze (NFC) (details)
  294. [lldb] const a couple of getters on MemoryRegionInfo (details)
  295. [AMDGPU] Shrink F16 MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10 (details)
  296. [mlir:GreedyDriver] Return WalkResult::skip after deleting a known constant (details)
  297. [AMDGPU] Aggressively fold immediates in SIFoldOperands (details)
  298. [JumpThreading] Simplify getPredicateAt() based folding (details)
  299. [MLIR] Make `parseDimensionListRanked` configurable wrt parsing a trailing `x` (details)
  300. [llvm][fix-irreducible] ensure that loop subtree under child is correctly reconnected to new loop (details)
  301. [IR] Report whether replaceUsesOfWith() changed something (NFC) (details)
  302. [JumpThreading] Add additional freeze tests (NFC) (details)
  303. [AMDGPU] Aggressively fold immediates in SIShrinkInstructions (details)
  304. [JumpThreading] Look through freeze in getPredicateAt() fold (details)
  305. [AMDGPU][MC][GFX10] Add missing s_scratch_load tests. (details)
  306. [lldb] Add --all option to "memory region" (details)
  307. AArch64: fall back to DWARF instead of crashing on weird .cfi directives (details)
  308. [X86] Regenerate select-ext.ll test for D125604 (details)
  309. [X86] coalesce-dead-lanes.mir - fix CHECK-LABEL typo identified in D125604 (details)
  310. [X86] copy-propagation.ll - fix CHECK-NEXT typo identified in D125604 (details)
  311. [X86] lvi-hardening-indirectbr.ll - fix X64-NOT typo identified in D125604 (details)
  312. [X86] statepoint-vreg-details.ll - fix CHECK-VREG-LABEL typo identified in D125604 (details)
  313. [DebugInfo][X86] debug-info-template-parameter.ll - fix broken DW_AT_default_value checks identified in D125604 (details)
  314. [AArch64] fp16-v8-instructions.ll - remove some old defunct CHECKS identified in D125604 (details)
  315. Revert "[lldb] Add --all option to "memory region"" (details)
  316. [lldb] Remove non-address bits from read/write addresses in lldb (details)
  317. [AMDGPU][MC][NFC] MUBUF code cleanup (details)
  318. [OpenCL] Add cl_khr_subgroup_rotate builtins (details)
  319. [mlir][complex] Add pow/sqrt/tanh ops and lowering to libm (details)
  320. [ARM] Don't Enable AES Pass for Generic Cores (details)
  321. [AMDGPU][MC][GFX7] Disable cache policy modifiers with SMRD (details)
  322. [Security Group] Update representative for Rust. (details)
  323. [AArch64] neon-vmull-high-p64.ll - fix name/check mismatch identified in D125604 (details)
  324. [X86] addcarry.ll - add nounwind to prevent cfi noise on tests (details)
  325. [libcxx] [test] Add missing header for std::numeric_limits (details)
  326. [libcxx] [test] Include header for strverscmp (details)
  327. [AMDGPU][MC][GFX940] Correct tied operand decoding for smfmac opcodes (details)
  328. [InstCombine] Remove disable-verify tests (NFC) (details)
  329. [lldb][AArch64] Fix corefile memory reads when there are non-address bits (details)
  330. [InstCombine] reduce code duplication for checking types; NFC (details)
  331. [InstCombine] avoid crash on fold of icmp with cast operand (details)
  332. Reland(2) "[clangd] Indexing of standard library" (details)
  333. [lit] pass LLVM_SYMBOLIZER_PATH through to tests. (details)
  334. [CGP] Regenerate test checks (NFC) (details)
  335. Assert on polymorphic pointer intrinsic param (details)
  336. [gn build] Port ca875539f788 (details)
  337. [NFC] correcting a code comment. (details)
  338. [SCEV] Part 1, Serialize function calls in function arguments. (details)
  339. [SystemZ] Bugfix in SystemZTargetLowering::combineINT_TO_FP() (details)
  340. Revert "[BasicAA] Remove unneeded special case for malloc/calloc" (details)
  341. clang-cl: Move /Zc: tests from cl-options.c to cl-zc.cpp (details)
  342. [OpenMP] libomp: honor passive wait policy requested with tasking (details)
  343. [ARM] Clean up a test check from D125604. NFC (details)
  344. [RISCV][NFC] Rename variable in RISCVVEmitter.cpp (details)
  345. [tests] Add test coverage for issue causing revert f7988d0 (details)
  346. [LoopUnroll] Regenerate test checks (NFC) (details)
  347. Revert "Reland(2) "[clangd] Indexing of standard library"" (details)
  348. [AArch64] Add tests showing reassoc breaks (s|u)ml(a|s)l selection. (details)
  349. [gn build] Port 77533ea443ac (details)
  350. [lldb] Change implementation of memory read --show-tags option (details)
  351. [gn build] Port 29e556fc2ba9 (details)
  352. [mlir][sparse] Add support for complex.im and complex.re to the sparse compiler. (details)
  353. [libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE. (details)
  354. Apply clang-tidy fixes for performance-for-range-copy in LinalgOps.cpp (NFC) (details)
  355. Apply clang-tidy fixes for llvm-else-after-return in OpenMPDialect.cpp (NFC) (details)
  356. [DAGCombiner] Fix bug in MatchBSwapHWordLow. (details)
  357. [clang-tidy] Fix readability-simplify-boolean-expr crash with implicit cast in return. (details)
  358. [ObjCopy][NFC] Remove unneeded zero initialization (details)
  359. Correct the diagnostic behavior for unreachable _Generic associations in C++ (details)
  360. [Debuginfod] Add --debug-file-directory to llvm-debuginfod-find. (details)
  361. Partially revert "[CMake] Passthrough OSX CMake options to builtins and runtimes" (details)
  362. Add a darwin platform setting to specify which exceptions debugserver (details)
  363. [gn build] port 6694491affa18 (details)
  364. [mlir][ods] Simplify useDefaultType/AttributePrinterParser (details)
  365. [RISCV] Add test cases showing failure to remove mask on rotate amounts. (details)
  366. [RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates. (details)
  367. [runtimes] Default LIB*_HERMETIC_STATIC_LIBRARY to ON on Windows (details)
  368. [MC] [Win64EH] Remove an unused parameter to ARM64EmitUnwindCode. NFC. (details)
  369. [MC] [Win64EH] Don't produce packed ARM64 unwind info with homed parameters (details)
  370. [libc] Add strlcpy (details)
  371. [libc] Add String to bsd headers (details)
  372. [libc++][format] Adds a formattable concept. (details)
  373. [gn build] Port 15c809e8e780 (details)
  374. [libc++][format] Adds formatter<charT[N], charT>. (details)
  375. [libc++][format] Improve format-arg-store. (details)
  376. [SystemZ][z/OS] Add the PPA1 to SystemZAsmPrinter (details)
  377. [libc++][format][5/6] Improve format_to_n. (details)
  378. [CMake][Fuchsia] Build runtimes as universal libraries on OS X (details)
  379. [libc] fix missing semicolon in bsd_ext.td (details)
  380. [gn build] Port 4d8268fbf4cd (details)
  381. [llvm-readobj] Improve printing of Windows ARM packed unwind info (details)
  382. [InstCombine] add tests for bswap with shift op; NFC (details)
  383. [InstCombine] allow variable shift amount in bswap + shift fold (details)
  384. [GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM (details)
  385. [Driver] Refactor /opt/rh detection (details)
  386. Fix some -Wstrict-prototypes issues in ORC examples (details)
  387. [libc++][CI] fixed a return curr_symbol() for Russian in the libcxx/test/support/locale_helpers.h for AIX (details)
  388. [clang-tidy] Fix readability-simplify-boolean-expr when Ifs have an init statement or condition variable (details)
  389. [SystemZ][z/OS] Add missing include to llvm/include/llvm/BinaryFormat/GOFF.h (details)
  390. [SLP]Improve reductions vectorization. (details)
  391. Reland "[dwarf] Emit a DIGlobalVariable for constant strings." (details)
  392. [NFCI] clang-format scudo standalone (details)
  393. [mlir] Fix the error message for missing explicit TypeID (details)
  394. [NFCI] clang-format gwp-asan files. (details)
  395. [libc][windows] fix strlcpy tests (details)
  396. [Analyzer] Remove extra space from NSErrorChecker message. (details)
  397. [Sanitizers][Darwin] Rename Apple macro  SANITIZER_MAC -> SANITIZER_APPLE (details)
  398. [RISCV] Add a test case where mutation still violates strict asserts in InsertVSETVLI (details)
  399. [Debuginfod] Fix shared libs build break after eafa0530417e (details)
  400. [Analysis] Avoid virtual dtor. NFC. (details)
  401. [SPIRV] Add simple tests to improve test coverage (details)
  402. [BOLT] Testcase to repro R_X86_64_REX_GOTPCRELX bug (details)
  403. Extend switch condition in optimizeSwitchPhiConst when free (details)
  404. [flang] test conforming & non-conforming lcobound (details)
  405. [Sparc] Make sure that we really don't emit quad-precision unless the "hard-quad-float" feature is available (details)
  406. [M68k][Disassembler] Fix decoding conflict (details)
  407. [llvm/Support] Fallback to $TERM if terminfo has no "colors" capability (details)
  408. [lldb/Test] Add `use_colors` argument to the PExpect.launch wrapper (details)
  409. [lldb/Core] Fix "sticky" long progress messages (details)
  410. [lldb/crashlog] Fix line entries resolution in interactive mode (details)
  411. dyld patch (details)
  412. [lldb/test] Make some tests as XFAIL while I investigate the issue (details)
  413. Revert 821ee172cdcd7196b6130321b53b6cc66bf1222b (details)
  414. Fix an or+and miscompile w/ GlobalISel (details)
  415. [InstCombine] Allow undef vectors when foldSelectToCopysign (details)
  416. [InstCombine] (rot X, ?) == 0/-1 --> X == 0/-1 (details)
  417. Revert "[lldb/test] Make some tests as XFAIL while I investigate the issue" (details)
  418. [lldb/test] Fix failures caused by a previous PExpect.launch change (details)
  419. [NFC][RISCV] Enable TuneNoDefaultUnroll feature to control targets which use default unroll preference (details)
  420. [LV] Widen freeze instead of scalarizing it (details)
  421. Fix if statement in DebugInfo/GSYM/LookupResult.cpp (details)
  422. [mlir] Add GlobalOp, GlobalLoadConstOp to ml_program. (details)
  423. [mlir][python] Add Python bindings for ml_program dialect. (details)
  424. Reland(3) "[clangd] Indexing of standard library" (details)
  425. [clang-tidy] Fix logic of assertion (details)
  426. [gn build] Port 03ea140b3a28 (details)
  427. [pseudo] Squash some warnings. NFC (details)
  428. [clangd] Suppress warning: control reaches end of function (details)
  429. [LegalizeTypes][VP][NFC] Use an if and two returns instead of ?: operator (details)
  430. [LegalizeTypes][VP] Add integer promotions support for VP_TRUNCATE (details)
  431. [Serialization] Delta-encode consecutive SourceLocations in TypeLoc (details)
  432. [libunwind] Remove -Wsign-conversion warning (details)
  433. [LegalizeVectorTypes][VP] Add widen and split support for VP_SETCC (details)
  434. [Serialization] Add missing includes for CHAR_BIT (details)
  435. [gn build] Port 4df795bff752 (details)
  436. [WebAssembly] Fix bug where -no-type-check failed to completely disable the typechecker (details)
  437. [libc] Apply no-builtin everywhere, remove unnecessary flags (details)
  438. [WebAssembly][NFC] Fix errant tabs in test case in last commit (details)
  439. [release] Add cmake as an extra tarball and not bundle it (details)
  440. [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation (details)
  441. [clangd] NFC: Clarify the Include Cleaner warning (details)
  442. [clangd] Update the test after diagnostic message change (details)
  443. [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir. (details)
  444. [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf (details)
  445. [APInt] Deprecate truncOrSelf, zextOrSelf and sextOrSelf (details)
  446. [AMDGPU][MC][GFX940] Add SMFMAC aliases (details)
  447. [flang][driver] Make driver accept `-module-dir<value>` (details)
  448. [AArch64] Extend zero vector TBL codegen tests. NFC (details)
  449. Reland "[lldb] Add --all option to "memory region"" (details)
  450. [NFC][M68k] Replace `APInt::zextOrSelf` with `APInt::zext` (details)
  451. [AArch64] Fix zero element TBL indices (details)
  452. [M68k] Fix a bug in disassembler (details)
  453. [lldb] Add --show-tags option to "memory find" (details)
  454. [SLP][NFC] Pre-commit test showing vectorization preventing FMA (details)
  455. Add an option to fill container for ref (details)
  456. [AArch64][SVE] Convert SRSHL to LSL when the fed from an ABS intrinsic (details)
  457. [libc++] Enable move semantics for vector in C++03 (details)
  458. [flang][NFC] Allow whitespaces before `ERROR` (details)
  459. [libc++] Granularize algorithm benchmarks (details)
  460. [AMDGPU] gfx11 LDSDIR instructions MC support (details)
  461. [flang][OpenMP] Support for Collapse (details)
  462. [flang][driver] Add support for generating executables on MacOSX/Darwin (details)
  463. [runtimes] Fix the build of merged ABI/unwinder libraries (details)
  464. [AMDGPU] gfx11 scalar memory instructions (details)
  465. [libunwind] Remove unused _LIBUNWIND_HAS_NO_THREADS macro in tests (details)
  466. [NFC] Fix typos in X86CmovConversion (details)
  467. [libc++] Override the value of LIBCXX_CXX_ABI in the cache (details)
  468. [VPlan] Update VPWidenMemoryInstruction to not inherit from VPValue. (details)
  469. [LoopVectorize] Precommit a test for D122126 (details)
  470. [LoopVectorize] Don't interleave when the number of runtime checks exceeds the threshold (details)
  471. [clang] Fix __has_builtin (details)
  472. [lldb] Add non-address bit improvements to release notes (details)
  473. [AMDGPU] Allow multiple uses of the same literal in SOP2/SOPC (details)
  474. [SimpleLoopUnswitch] Skip trivial selects during trivial unswitching. (details)
  475. [AMDGPU] emit macro __GFX9__ etc (details)
  476. [PowerPC] Implement XL compat __fnabs and __fnabss builtins. (details)
  477. [NVVM] Update intrinsic defintions to include the `nocallback` attribute (details)
  478. [SelectOpti][1/5] Setup new select-optimize pass (details)
  479. [gn build] Port ca7c307d1816 (details)
  480. [DeadArgElim] Use poison instead of undef as placeholder for dead arguments (details)
  481. Drop qualifiers from return types in C (DR423) (details)
  482. [NFC] Fix a couple of whitespace issues. (details)
  483. [mlir][tensor] Add canonicalization for tensor.cast from extract_slice (details)
  484. [mlir][vector] Fix crash in DropInnerMostUnitDims pattern (details)
  485. [llvm-jitlink] Print session report even if entry-point lookup errors out. (details)
  486. [ORC] Add missing std::moves, pass SymbolLookupSet by value. (details)
  487. [ORC] Add a FIXME. (details)
  488. [ORC] Avoid more SymbolStringPtr copies. (details)
  489. [Object] Fix updating darwin archives (details)
  490. [docs][tools] Remove old llvm-bcanalyzer options (details)
  491. [llvm-dis] Improve missing file error message (details)
  492. [WebAssembly] Use CHECK-NEXT for irreducible-cfg.mir (details)
  493. [WebAssembly] Fix register use-def in FixIrreducibleControlFlow (details)
  494. [Libomptarget] Add `leaf` attribute to `vprintf` declaration (details)
  495. [ValueTracking] Baseline tests for Power-of-2 value tracking on PHI nodes (details)
  496. [llvm-dis][test] Fix error case on Windows (details)
  497. [ValueTracking] Added support to deduce PHI Nodes values being a power of 2 (details)
  498. [Office Hours] add initial guidance for hosts (details)
  499. [InstCombine] NEW Baseline tests for InstCombine optimization to merge GEP instructions with constant indices (details)
  500. [ARM] Cost modelling for scalar fptoi_sat (details)
  501. [OpenMP][libomp] Fix accidental removal of else for core attributes (details)
  502. Revert "[ValueTracking] Added support to deduce PHI Nodes values being a power of 2" (details)
  503. [lld][test] Delete empty Unit test directory (details)
  504. [gn build] (manually) port 505ddb6b7450 (remove Unit/lit.site.cfg.py) (details)
  505. [LV] Drop wrap flags for reductions using VP def-use chain. (details)
  506. [Clang][[OpenMP5.1] Initial parser/sema for default(private) clause (details)
  507. [mlir] Remove unused properties from the standalone example's lit configuration (details)
  508. [AMDGPU] Mark s_getreg as having side effects instead of reading memory (details)
  509. [AMDGPU] Mark s_get_waveid_in_workgroup as not reading memory (details)
  510. [mlir][sparse] fix unsigned comparison bug in assert (details)
  511. Handle instrumentation of scalar single-precision (_ss) intrinsics (details)
  512. [Flang][OpenMP] Upstream the lowering of the parallel do combined construct (details)
  513. [bazel] Add lib/Basic/BuiltinTargetFeatures.h to clang:basic `hdrs`. (details)
  514. [ConstantRange] Improve the implementation of binaryOr (details)
  515. Revert "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates." (details)
  516. Revert "[RISCV] Add test cases showing failure to remove mask on rotate amounts." (details)
  517. [lldb/test] Fix PExpect.launch issue when disabling color support (details)
  518. [libc] Add strlcat (details)
  519. [DirectX backend] When cleanup module flags only remove unused flags. (details)
  520. [TableGen] Add generation of argument register lists (details)
  521. [mlir][sparse] Using the name "dimSizes" more consistently (details)
  522. [mlir][sparse] Simplifying closure (details)
  523. Revert "[TableGen] Add generation of argument register lists" (details)
  524. [TableGen] Add generation of argument register lists (details)
  525. [mlir][sparse] Factored out a "FATAL" macro for unrecoverable assertion failure (details)
  526. [bazel][libc] Fix bazel build (details)
  527. [Serialization] Delta encode locations in expansion sloc entries (details)
  528. [mlir][sparse] Adding x-macros for OverheadType (details)
  529. [AArch64] Add support for -fzero-call-used-regs (details)
  530. [mlir][Arithmetic] fold overlapping negf. (details)
  531. [lit] Fix setup of sanitizer environment (details)
  532. [InstCombine] [NFC] Use a pattern matcher for ExtractElementInst (details)
  533. [ASan] Add sleep_before_init flag (details)
  534. [RISCV] Add test showing codegen for unaligned loads and stores of scalar types (details)
  535. [lldb] Fix 'ptsname_r' is only available on macOS 10.13.4 or newer (details)
  536. [lldb] Update test_software_breakpoint_set_and_remove_work for AS (details)
  537. [MIR] Provide location of extra instruction operand when diagnosing it. (details)
  538. [RISCV][NFC] Remove `*=` operator for LMULType (details)
  539. [RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions. (details)
  540. [flang][OpenMP] Fix the types of worksharing-loop variables (details)
  541. Make CompoundStmtBitfields::NumStmts not a bit-field (details)
  542. [amdgpu] Add amdgpu_kernel calling conv attribute to clang (details)
  543. [AArch64] Fix the generation of BE Nops (details)
  544. [NFC][test] Fix the line num of expected-error for CSKY at builtin-alloca-with-align.c (details)
  545. [LV] Do not LoopSimplify/LCSSA after generating main vector loop. (details)
  546. [flang] Fix use-associated false-positive error (details)
  547. [AArch64][SME][NFC] Add implicit operands for SME instructions in the disassembly. (details)
  548. [AArch64][SME]Tied up ZA operand for accumulate instructions (details)
  549. [ARM] Cost modelling for MVE vector fptoi_sat (details)
  550. [mlir] do not elide dialect prefix for ops with dots in the name (details)
  551. [AMDGPU][MC][GFX8+] Correct SMEM offset parsing (details)
  552. [X86][AMX][NFC] Refactor X86LowerAMXCast.cpp (details)
  553. tsan: add lock free stack pattern test (details)
  554. [AMDGPU] Add a test case for an SIFoldOperands bug (details)
  555. Minutes for pauth sync-ups have moved to Discourse. (details)
  556. [RISCV] Add a test showing overlapping stack offsets with RVV (details)
  557. [RISCV] Fix logic for determining RVV stack padding (details)
  558. [AArch64] Generate AND in place of CSEL for predicated CTTZ (details)
  559. [clangd] Support UnresolvedUsingTypeLoc AST node in FindTarget. (details)
  560. [SLP][NFC]Use SmallPtrSet to avoid n*m complexity, NFC. (details)
  561. [SLP]Do not emit extract elements for insertelements users, replace with shuffles directly. (details)
  562. [InstCombine] add casted bitwise logic tests to show missing use check; NFC (details)
  563. [InstCombine] add use check to fold of bitwise logic with cast ops (details)
  564. [DebugInfo][NFC] Add instr-ref documentation, migration guide (details)
  565. Fix test from df2a4e to work with 32 bit windows targets. (details)
  566. [libc++abi] Add missing XFAIL on test (details)
  567. [libunwind] Introduce a cmake-bridge.cfg.in file to reduce test config duplication (details)
  568. [libc++] Improve error messages for disabled modes (details)
  569. [clang] Honor __attribute__((no_builtin("foo"))) on functions (details)
  570. [analyzer][NFC] Remove the unused LocAsInteger::getPersistentLoc() (details)
  571. [clang-format] Don't break lines after pragma region (details)
  572. [clangd] Provide links to clang-tidy and include-cleaner diagnostic docs (details)
  573. Revert "[libc] Apply no-builtin everywhere, remove unnecessary flags" (details)
  574. [libc++] Use _LIBCPP_ASSERT by default for _PSTL_ASSERTions (details)
  575. Fix an unused variable warning in no-asserts build mode (details)
  576. [AMDGPU] Add verification for mandatory literals (details)
  577. [AMDGPU] Handle mandatory literals in isOperandLegal (details)
  578. [lldb] Disable scripted_crashlog_json.test on Apple Silicon (details)
  579. [X86] Add tests for FREM (details)
  580. [ifs] Switch to using OptTable (details)
  581. [MLIR][GPU] Add NvGpu mma.sync path to the VectorToGPU pass (details)
  582. [clangd][ObjC] Filter ObjC method completions on the remaining selector (details)
  583. [mlir][sparse] add support for complex zero/one building (details)
  584. Adjust BUILD files for [MLIR][GPU] Add NvGpu mma.sync path to the VectorToGPU pass (details)
  585. Adjust BUILD files for [ifs] Switch to using OptTable (details)
  586. Use the public clang::Builtin API in the unit test (details)
  587. [AMDGPU] Mark SMEM cache invalidations as not reading memory (details)
  588. [clang] Fixing arm-common, windows only and openmp header install targets (details)
  589. [TypePromotion] Fix another case for sext vs zext in promoted constant. (details)
  590. [lldb] Set correct register number for cpsr (GENERIC_REGNUM_FLAGS) (details)
  591. [mlir] Add missing NVGPU link dependency to VectorToGPU (details)
  592. [gn build] (manually) port 480dcdc8975d8 (llvm-ifs OptTable) (details)
  593. [RISCV] Add initial test coverage for LSR (details)
  594. [InstructionSimplify] Remove multiple 'break' after 'return'. NFC (details)
  595. Revert "[ConstantRange] Improve the implementation of binaryOr" (details)
  596. Update fuzzing test to comply with new optimisation. (details)
  597. Adapt C++ std::string dataformatter for D125496 (details)
  598. Fix up fuzzing test on Windows. (details)
  599. Avoid uninitialized Diag.ID (which we pass but never read) (details)
  600. Add some diagnostics to diagnose bot-only failures for TestIgnoredExceptions.py (details)
  601. Recommit "[ConstantRange] Improve the implementation of binaryOr" (details)
  602. [AArch64] Use proper instruction mnemonics for FPRs (details)
  603. [CodeView] Combine variable def ranges that are continuous. (details)
  604. Reland "[clang-tidy] modernize-deprecated-headers check should respect extern "C" blocks"" (details)
  605. [Libomptarget] Add branch prediction intrinsic to state check (details)
  606. [clang-tidy] Introduce the WarnIntoHeaders option to modernize-deprecated-headers (details)
  607. [clang-tidy] modernize-deprecated-headers should ignore system headers (details)
  608. Mark new TSan test as unsupported on PPC. (details)
  609. Add a page to track C defect report status (details)
  610. [OpenMP] Fix partial unrolling off-by-one. (details)
  611. Add 'ppc' as a target (for both 32- and 64-bit ppc). (details)
  612. [lldb] Consider binary as module of last resort (details)
  613. [lldb] Fix spurious assertion in PrintCommandOutput (details)
  614. PPC+TSan whack-a-mole, round 3. (details)
  615. [LLVM] Add a check if should cast atomic operations to integer type (details)
  616. [NVPTX] Enable AtomicExpandPass for NVPTX (details)
  617. [mlir][sparse] Support more complex operations. (details)
  618. [lld-macho] Stop crash when emitting personalities with -dead_strip (details)
  619. Convert the test file for TestIgnoredExceptions.py to the mach_vm API. (details)
  620. [WebAssembly] Strip TLS when "atomics" is not enabled (details)
Commit 9d99cf59a151a715ebebf3a4c4782dfdb48d7f4b by richard
[clang-tidy] Restore test parameter operator<< function (NFC)

Clang erroneously flagged the function as "unused", but it is most
definitely used by gtest to pretty print the parameter value when
a test fails.

Make the pretty printing function a friend function in the parameter
class similar to other clang unit tests.
The file was modifiedclang-tools-extra/unittests/clang-tidy/ModernizeModuleTest.cpp
Commit 5d55ffe94dc947308059a7a2484321b7f1bd6270 by nikolasklauser
[libc++] Simplify the string structures a bit more

This simplifies the string structs a bit more and the normal layout should not contain any undefined behaviour anymore. I don't think there is a way to achieve this in the alternate string mode without breaking the ABI.

Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D125496
The file was modifiedlibcxx/include/string
Commit 44ae09d75ffbf077aaad4bc1f6f75292fb5a1b52 by varconst
[libc++][ranges][NFC] Mark completed issues related to the One Ranges Proposal.

Quite a few C++20 LWG issues/papers related to the One Ranges Proposal
were already effectively implemented (or contain semantic-only wording
changes that don't affect the implementation), mark them as such.

Differential Revision: https://reviews.llvm.org/D125065
The file was modifiedlibcxx/docs/Status/Cxx20Papers.csv
The file was modifiedlibcxx/docs/ReleaseNotes.rst
The file was modifiedlibcxx/docs/Status/Cxx20Issues.csv
The file was modifiedlibcxx/docs/Status/RangesIssues.csv
Commit 5a19fbad83018b705923e13fee957c049c295bbf by craig.topper
[RISCV] Remove unneeded check for ISD::VSCALE operand being a constant. NFC

ISD::VSCALE only allows constant operands.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit b8f52c08f85aac47cb2079a7a80a9d88875e0692 by minyihh
[mlir][LLVMIR] Add support for translating insert/extractvalue

Add support for translating llvm::InsertValue and llvm::ExtractValue.

Differential Revision: https://reviews.llvm.org/D125028
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/test/Target/LLVMIR/Import/basic.ll
Commit 3da65c4c0b00b9fc0cf2db77c18a58bc6fca251f by minyihh
[mlir][LLVMIR] Add support for translating shufflevector

Add support for translating llvm::ShuffleVectorInst

Differential Revision: https://reviews.llvm.org/D125030
The file was modifiedmlir/test/Target/LLVMIR/Import/basic.ll
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
Commit c644488a8b8a2e831c5665a6167a9debabbb2d72 by ox59616e
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`

The name `MCFixedLenDisassembler.h` is out of date after D120958.

Rename it as `MCDecoderOps.h` to reflect the change.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D124987
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
The file was modifiedllvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
The file was modifiedllvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was modifiedllvm/utils/TableGen/DecoderEmitter.cpp
The file was modifiedllvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
The file was modifiedllvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
The file was modifiedllvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was addedllvm/include/llvm/MC/MCDecoderOps.h
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was removedllvm/include/llvm/MC/MCFixedLenDisassembler.h
The file was modifiedllvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
The file was modifiedllvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
The file was modifiedllvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
The file was modifiedllvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
The file was modifiedllvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
Commit cf0b6df6dbf57334537f827fc8f14f2d7698c3f0 by ox59616e
[M68k][Disassembler] Adopt the new variable length decoder

This is an example usage of D120958.

After these patches are landed, we can strip off the codebeads officially.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D120960
The file was modifiedllvm/lib/Target/M68k/CMakeLists.txt
The file was modifiedllvm/test/MC/Disassembler/M68k/control.txt
The file was modifiedllvm/test/MC/M68k/Relaxations/branch.s
The file was modifiedllvm/test/MC/Disassembler/M68k/shift-rotate.txt
The file was modifiedllvm/test/MC/Disassembler/M68k/arithmetic.txt
The file was modifiedllvm/test/MC/Disassembler/M68k/bits.txt
The file was modifiedllvm/test/MC/Disassembler/M68k/data.txt
The file was modifiedllvm/test/MC/M68k/Control/call-pc-rel.s
The file was modifiedllvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
Commit 59afc4038b1096bc6fea7b322091f6e5e2dc0b38 by i
[LowerTypeTests][clang] Implement and allow -fsanitize=cfi-icall for RISCV

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D106888
The file was modifiedllvm/test/Transforms/LowerTypeTests/function-weak.ll
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedllvm/test/Transforms/LowerTypeTests/function.ll
The file was modifiedclang/test/Driver/fsanitize.c
Commit c554aeeea7941324776bbff5e53f6fc486d3fa2d by thakis
fix typos to cycle bots
The file was modifiedlld/test/COFF/gfids-icf.s
The file was modifiedlld/test/COFF/gfids-relocations32.s
The file was modifiedlld/test/COFF/wrap-real-missing.s
Commit b4ad450953f0d7fd85f29d467297ed266c3d33be by craig.topper
[TargetLowering] expandCTPOP don't create an used constant mask for i8 ctpop. NFC

Use early out for the i8 case.

I'm looking at avoiding MUL on targets that use libcalls for MUL.
So doing a little pre-refactoring.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 496e135b034d7d9a9f06853899b204644a0bfb1a by joeloser93
[libc++][test] Verify std::views::drop and std::views::join are CPOs

`std::views::drops` and `std::views::join` have been implemented, but the tests
verifying the CPOs for them are still commented out. Uncomment the tests.

Differential Revision: https://reviews.llvm.org/D125618
The file was modifiedlibcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
Commit 2cdabc0322929a3954b63c1f29f23959e2e50278 by owenca
[clang-format] Handle "if consteval { ... }" for RemoveBracesLLVM

Differential Revision: https://reviews.llvm.org/D125593
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
Commit bdab5c4b3d2053d4981365f8b839f5637720f934 by geek4civic
ARMFixCortexA57AES1742098Pass.cpp: Suppress a warning. [-Wunused-but-set-variable]
The file was modifiedllvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
Commit f66596c94f772e214fd9d96cc78f7fec17209281 by llvm-dev
[clang][docs] Add escape code to fix missing '*' in reduction operation list
The file was modifiedclang/docs/LanguageExtensions.rst
Commit da7d8de1e4abd3265f18df033002edd5fe190a79 by geek4civic
ScalarEvolution.cpp: Reformat.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 019fa346b99c600b32e1bc295ebac527a5ad825c by llvm-dev
[X86] Adjust tests for vector widening to use freeze(poison)

I incorrectly used freeze(undef) in rG1b07bd9034bd
The file was modifiedllvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/avx-intrinsics-x86.ll
The file was modifiedllvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
Commit df5ea2b12d482986269b74f7c9d2ccb8c5c90676 by llvm-dev
[X86] Add shuffles showing failure to use PERMUTE(BLEND(X,Y))

One AVX2+ targets we have a immediate VPERMQ/PD cross-lane permute thats better than relying on a pair of VPERM2F128 cross-lanes to feed a blend.

Reported on discourse
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
Commit 32162cf291d40b8ead01061ea68bcdbc79ba9573 by llvm-dev
[X86] lowerV4I64Shuffle - try harder to lower to PERMQ(BLENDD(V1,V2)) pattern
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
The file was modifiedllvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
Commit c0f59be3584932b50f63b8c0207537453d2b0f44 by llvm-dev
[X86] Pull out repeated isShuffleMaskInputInPlace calls. NFC.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 39552964e168652ff6e9eaf31fc8cf11f046f3c2 by flo
[VPlan] Improve printing of VPReplicateRecipe with calls.

Suggested as part of D124718.
The file was modifiedllvm/test/Transforms/LoopVectorize/interleave-with-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit fd1f0c51ef7f64ae7317a695ebb4f22fec3b8958 by llvm-dev
[X86] lowerShuffleAsLanePermuteAndSHUFP always succeeds, so just return the result. NFC.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 9b44b0318e7d6f6cb36327477fbf1bce768c9b76 by llvm-dev
[X86] Add checks to illegal-insert.ll
The file was modifiedllvm/test/CodeGen/X86/illegal-insert.ll
Commit 6bf8133f9f34a17d4e7378af05e7eb71ea2c21a6 by llvm-dev
[X86] Add test coverage for PR44915 / Issue #44260
The file was addedllvm/test/CodeGen/X86/pr44915.ll
Commit c748d2cdd9c47a8ed35deeb419c861280cc862a1 by craig.topper
[RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC

Add more i8/16 tets.
Add ctlz_zero_undef tests.
The file was modifiedllvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
Commit d0312a5c3f876c38e9c62588478025f310600861 by craig.topper
[RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC

ctpop and cttz default expansion both end up using a multiply. This
can either use a mul instruction or libcall. Make sure we test both
cases.
The file was modifiedllvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
Commit b3097eb6cda67f8f5ff0d2a77c3af530e1b6fe04 by craig.topper
[SLP] Fix misspelling of 'analyzed'. NFC
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit ea18987094eff5a5835135da1f472d2e7bf6c68e by andrzej.warzynski
[flang][nfc] Fix driver method names overridden by the plugins

After the recent re-factoring of the driver code
(https://reviews.llvm.org/D125007), `ExecuteAction` was renamed as
`executeAction`. This patch updates the examples in Flang accordingly.

If you set `FLANG_BUILD_EXAMPLES` to `On` when building Flang, then the
refactoring from D125007 would have caused build failures for you. This
patch fixes that.

This is fairly straightforward and fixes buildbot failures, so I'm
sending this without a review.
The file was modifiedflang/examples/PrintFlangFunctionNames/PrintFlangFunctionNames.cpp
The file was modifiedflang/examples/FlangOmpReport/FlangOmpReport.cpp
Commit fd864238fca1435cb1ceffdca0d4294cf3419ac7 by daniel.kiss
Revert "[libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE."

This reverts commit f6366ef7f4f3cf1182fd70e0c50a9fa54374b612.
The file was removedlibunwind/test/aarch64.ra_sign_state.pass.cpp
The file was modifiedlibunwind/src/DwarfInstructions.hpp
Commit fdae8641adbefd0c9522887f7c6c83a19e227591 by a.v.lapshin
[DWARFLinker][NFC] cleanup AddressManager interface.

this review is extracted from D86539

1. delete areRelocationsResolved() method.
2. rename hasLiveMemoryLocation() -> isLiveVariable()
          hasLiveAddressRange() -> isLiveSubprogram().

Differential Revision: https://reviews.llvm.org/D125492
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.h
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
Commit 896557e129c2ca74c8f87ed56e4fc37958eaa130 by llvm-dev
[X86] Adjust fadd costs to match SoG

znver1/2 models were incorrectly modelling these on fpupipe 0 instead of 2/3 and znver1 ymm variants also require double pumping.

Now matches AMD SoG, Agner and instlatx64 numbers.

Thanks to @fabian-r for the report
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-avx1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-sse3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-x87.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver2.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-sse1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse3.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver1.td
Commit 8b7c3d2179b3c0dadb957ff255d7bdf3283474a8 by flo
[LV] Set SCEVCheckCond to nullptr whenever it was used.

Under some circumstances, SCEVExpander will insert new instructions when
expanding a predicate, but the final result of the expansion can be a
false constant.

In those cases, the expanded instructions may later be used by other
expansions, e.g. the trip count. This may trigger an assertion during
SCEVExpander cleanup. To avoid this, always mark the result as used.

Fixes #55100.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/pr55100-expand-scev-predicate-used.ll
Commit b3077f563d9f15aaf1868e54c91a82e2aab666a3 by llvm-dev
[X86] Move combineAddOrSubToADCOrSBB earlier. NFC.

Make it easier to reuse in X86 ADD/SUB combines in an upcoming patch.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 12e41d9264b6f84213be86aab75016fb82ebc1d1 by springerm
[mlir][bufferize] Infer memref types when possible

Instead of recomputing memref types from tensor types, try to infer them when possible. This results in more precise layout maps.

Differential Revision: https://reviews.llvm.org/D125614
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
The file was modifiedmlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
The file was modifiedmlir/lib/Dialect/Arithmetic/Transforms/BufferizableOpInterfaceImpl.cpp
The file was modifiedmlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
Commit 1878f240c9ad99f16293831857d1f826e6671cad by zakk.chen
[RISCV] Fix incorrect use of tail agnostic vslideup.

We need to use tail undisturbed for vslideup to implement
vector insert operation correctly.

Ideally, we cound use the tail agnostic when insert subvector
or element at the end of the vector. This will be in follow-up
patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125545
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vector-splice.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
Commit 3bef90dff64fc717c5d5e33a4d5fb47a4566d04a by yedeng.yd
[Diagnostic] Warn if the size argument of memset is character literal
zero

Closing https://github.com/llvm/llvm-project/issues/55402

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D125521
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/Sema/transpose-memset.c
Commit a8426ada49e873852ab31d406ee767541099f90f by jacquesguan
[RISCV][NFC] Replace for-each with array argument call.

This patch replaces some for-each set with the new arrayref argument API, since it already used an array in defination, I think this change won't cause any ambiguity.

Differential Revision: https://reviews.llvm.org/D125455
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 0809f63826d36c89574d6ac056ebf46a4b6f29ff by aman.lachapelle
[LLVM][Casting.h] Add trivial self-cast

Casting from a type to itself should always be possible. Make this simple for all users, and add tests to ensure we keep being able to do this. Ref: https://reviews.llvm.org/D125543

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125590
The file was modifiedllvm/unittests/Support/Casting.cpp
The file was modifiedllvm/include/llvm/Support/Casting.h
Commit 924acb624f58030652ecc8c07db313fde0f31395 by sguelton
[clang] Prevent folding of non-const compound expr

When a non-const compound statement is used to initialize a constexpr pointer,
the pointed value is not const itself and cannot be folded at codegen time.

This matches GCC behavior for compound literal expr arrays.

Fix issue #39324.

Differential Revision: https://reviews.llvm.org/D124038
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx11.cpp
The file was modifiedclang/test/SemaTemplate/constexpr-instantiate.cpp
Commit 49b0c605424b7e54cd7c287563f3650bcd7f0382 by jim
[DivRemPairs][Mips] Pre-commit test for Mips target

Copied from PowerPC.

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D124979
The file was addedllvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll
The file was addedllvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll
The file was addedllvm/test/Transforms/DivRemPairs/Mips/lit.local.cfg
Commit 0a0d6489ef2e46c9b365c5db77dddd13b681c2d1 by jim
[Mips] Implement hasDivRemOp()

SDIVREM and UDIVREM can be customized lowered in MipsSE.

Fix https://github.com/llvm/llvm-project/issues/54991.

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D124980
The file was addedllvm/lib/Target/Mips/MipsTargetTransformInfo.h
The file was modifiedllvm/test/Transforms/DivRemPairs/Mips/div-expanded-rem-pair.ll
The file was modifiedllvm/lib/Target/Mips/CMakeLists.txt
The file was modifiedllvm/test/Transforms/DivRemPairs/Mips/div-rem-pairs.ll
The file was addedllvm/lib/Target/Mips/MipsTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Mips/MipsTargetMachine.cpp
Commit c71f6376ebaf57802788464b2655915e853e5b97 by llvmgnsyncbot
[gn build] Port 0a0d6489ef2e
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
Commit 7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9 by kito.cheng
[RISCV][NFC] Refactor RISC-V vector intrinsic utils.

This patch is preparation for D111617, use class/struct/enum rather than char/StringRef to present internal information as possible, that provide more compact way to store those info and also easier to serialize/deserialize.

And also that improve readability of the code, e.g. "v" vs TypeProfile::Vector.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D124730
The file was modifiedclang/lib/Support/RISCVVIntrinsicUtils.cpp
The file was modifiedclang/utils/TableGen/RISCVVEmitter.cpp
The file was modifiedclang/include/clang/Support/RISCVVIntrinsicUtils.h
Commit e20bc892b6facc56fffc012929157888bb798bed by marek.kurdej+llvm.org
[clang-format] Fix PointerAlignment: Right not working with tab indentation.

Fixes https://github.com/llvm/llvm-project/issues/55407.

Given configuration:
```
UseTab: Always
PointerAlignment: Right
AlignConsecutiveDeclarations: true
```

Before, the pointer was misaligned in this code:
```
void f() {
unsigned long long big;
char       *ptr; // misaligned
int    i;
}
```

That was due to the fact that when handling right-aligned pointers, the Spaces were changed but StartOfTokenColumn was not.

Also, a tab was used not only for indentation but for spacing too when using `UseTab: ForIndentation` config option:
```
void f() {
unsigned long long big;
char       *ptr; // \t after char
int                i;
}
```

Reviewed By: owenpan

Differential Revision: https://reviews.llvm.org/D125528
The file was modifiedclang/lib/Format/WhitespaceManager.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit 5bc469fd96192039bafe4bb9f74c85b37f63212e by kito.cheng
[RISCV][NFC] Fix build issue
The file was modifiedclang/lib/Support/RISCVVIntrinsicUtils.cpp
Commit 9902a0945d22cd5757b16ebe85fe07059723aa09 by sam.mccall
Add ThreadPriority::Low, and use QoS class Utility on Mac

On Apple Silicon Macs, using a Darwin thread priority of PRIO_DARWIN_BG seems to
map directly to the QoS class Background. With this priority, the thread is
confined to efficiency cores only, which makes background indexing take forever.

Introduce a new ThreadPriority "Low" that sits in the middle between Background
and Default, and maps to QoS class "Utility" on Mac. Make this new priority the
default for indexing. This makes the thread run on all cores, but still lowers
priority enough to keep the machine responsive, and not interfere with
user-initiated actions.

I didn't change the implementations for Windows and Linux; on these systems,
both ThreadPriority::Background and ThreadPriority::Low map to the same thread
priority. This could be changed as a followup (e.g. by using SCHED_BATCH for Low
on Linux).

See also https://github.com/clangd/clangd/issues/1119.

Reviewed By: sammccall, dgoldman

Differential Revision: https://reviews.llvm.org/D124715
The file was modifiedllvm/lib/Support/Windows/Threading.inc
The file was modifiedllvm/include/llvm/Support/Threading.h
The file was modifiedllvm/lib/Support/Unix/Threading.inc
The file was modifiedclang-tools-extra/clangd/index/Background.h
The file was modifiedclang/tools/libclang/CIndex.cpp
Commit 40f361ace3e9a9c24bd99300216aeabd49ad99bb by kbobyrev
[clangd] Include Cleaner: ignore headers with IWYU export pragmas

Disable the warnings with `IWYU pragma: export` or `begin_exports` +
`end_exports` until we have support for these pragmas. There are too many
false-positive warnings for the headers that have the correct pragmas for now
and it makes the user experience very unpleasant.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D125468
The file was modifiedclang-tools-extra/clangd/Headers.cpp
The file was modifiedclang-tools-extra/clangd/unittests/IncludeCleanerTests.cpp
The file was modifiedclang-tools-extra/clangd/Headers.h
The file was modifiedclang-tools-extra/clangd/IncludeCleaner.cpp
The file was modifiedclang-tools-extra/clangd/unittests/HeadersTests.cpp
Commit befc952045066e840c7d84b3d3a4ab112a36366a by david.sherwood
[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors

When the loop vectoriser encounters a known low trip count it tries
to create a single predicated loop in order to get the benefit of
vectorisation and eliminate the scalar tail. However, until now the
vectoriser prevented the use of scalable vectors in this case due
to concerns in the past about stability. I believe that tail-folded
loops using scalable vectors are now sufficiently well tested that
we can enable this. For the same reason I've also enabled it when
optimising for code size too.

Tests added here:

  Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
  Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
  Transforms/LoopVectorize/RISCV/low-trip-count.ll

Differential Revision: https://reviews.llvm.org/D121595
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
Commit 106e63ce47b5b00e376be9eef03a084c71c03f11 by kbobyrev
[clangd] NFC: Rename field to be compatible with the function name
The file was modifiedclang-tools-extra/clangd/Headers.cpp
The file was modifiedclang-tools-extra/clangd/Headers.h
Commit e57f57841fbb0cd1d1dbd3237c2cbe6ce15984dd by marek.kurdej+llvm.org
[clang-format] fix alignment w/o binpacked args

The combination of

- AlignConsecutiveAssignments.Enabled = true
- BinPackArguments = false

would result in the first continuation line of a braced-init-list being
improperly indented (missing a shift) when in a continued function call.
Indentation was also wrong for braced-init-lists continuing a
direct-list-initialization.  Check for opening braced lists in
continuation and ensure that the correct shift occurs.

Fixes https://github.com/llvm/llvm-project/issues/55360

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D125162
The file was modifiedclang/lib/Format/WhitespaceManager.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit 05c3fe075d608a3e14f6ab272a24132912ebc861 by npopov
[FastISel] Fix load folding for registers with fixups

FastISel tries to fold loads into the single using instruction.
However, if the register has fixups, then there may be additional
uses through an alias of the register.

In particular, this fixes the problem reported at
https://reviews.llvm.org/D119432#3507087. The load register is
(at the time of load folding) only used in a single call instruction.
However, selection of the bitcast has added a fixup between the
load register and the cross-BB register of the bitcast result.
After fixups are applied, there would now be two uses of the load
register, so load folding is not legal.

Differential Revision: https://reviews.llvm.org/D125459
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was addedllvm/test/CodeGen/X86/fast-isel-load-bitcast-fold.ll
Commit 3d2e05d542e646891745c5278a09950d3c4fb4a5 by diana.picus
[flang] Install Fortran_main library

At the moment the Fortran_main library is not installed, so it cannot be
found by the driver when run from an install directory. This patch fixes
the issue by replacing llvm_add_library with add_flang_library, which
already contains all the proper incantations for installing a library.
It also enhances add_flang_library to support a STATIC arg which forces
the library to be static even when BUILD_SHARED_LIBS is on.

Differential Revision: https://reviews.llvm.org/D124759

Co-authored-by: Dan Palermo <Dan.Palermo@amd.com>
The file was modifiedflang/runtime/FortranMain/CMakeLists.txt
The file was modifiedflang/cmake/modules/AddFlang.cmake
Commit 7ba484660b74d5b9d0b342a45cdb0ce8fd5b04bb by npopov
[ControlHeightReduction] Freeze condition when converting select to branch

While select conditions can be poison, branch on poison is
immediate UB. As such, we need to freeze the condition when
converting a select into a branch.

Differential Revision: https://reviews.llvm.org/D125398
The file was modifiedllvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
The file was modifiedllvm/test/Transforms/PGOProfile/chr.ll
Commit 1a65c491be712f89b36af9d828b6ccce02de37db by hokein.wu
[pseudo] Support parsing variant target symbols.

With this patch, we're able to parse smaller chunks of C++ code (statement,
declaration), rather than translation-unit.

The start symbol is listed in the grammar in a form of `_ :=
statement`, each start symbol has a dedicated state (`_ := • statement`).
We create and track all these separate states in the LRTable. When we
start parsing, we lookup the corresponding state to start the parser.

LR pasing table changes with this patch:
- number of states: 1467 -> 1471
- number of actions: 82891 -> 83578
- size of the table (bytes): 334248 -> 336996

Differential Revision: https://reviews.llvm.org/D125006
The file was modifiedclang-tools-extra/pseudo/lib/Grammar.cpp
The file was modifiedclang-tools-extra/pseudo/fuzzer/Fuzzer.cpp
The file was addedclang-tools-extra/pseudo/test/glr-variant-start.cpp
The file was modifiedclang-tools-extra/pseudo/unittests/GrammarTest.cpp
The file was modifiedclang-tools-extra/pseudo/tool/ClangPseudo.cpp
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/LRTable.h
The file was modifiedclang-tools-extra/pseudo/lib/cxx.bnf
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/Grammar.h
The file was modifiedclang-tools-extra/pseudo/lib/LRGraph.cpp
The file was modifiedclang-tools-extra/pseudo/lib/LRTableBuild.cpp
The file was modifiedclang-tools-extra/pseudo/lib/LRTable.cpp
The file was modifiedclang-tools-extra/pseudo/unittests/GLRTest.cpp
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/LRGraph.h
The file was modifiedclang-tools-extra/pseudo/benchmarks/Benchmark.cpp
The file was modifiedclang-tools-extra/pseudo/lib/GLR.cpp
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/GLR.h
Commit dfb006c0c969fbccfde3be6af3c0636e0643fc83 by jay.foad
[AMDGPU] Extract SIInstrInfo::removeModOperands. NFC.

Make this an externally callable function for use in a future patch.

Differential Revision: https://reviews.llvm.org/D125565
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit c1af2d329f85f8b14efd22887914517fd6058be9 by jay.foad
[AMDGPU] SIShrinkInstructions: change static functions to methods

This is a mechanical change to avoid passing MRI and TII around
explicitly. NFC.

Differential Revision: https://reviews.llvm.org/D125566
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Commit 436bbce7657df830dcebd16b2ad675be56f58681 by npopov
[llvm-c] Add functions for enabling and creating opaque pointers

This is based on https://reviews.llvm.org/D125168 which adds a
wrapper to allow use of opaque pointers from the C API.

I added an opaque pointer mode test to echo.ll, and to fix assertions
that forbid the use of mixed typed and opaque pointers that were
triggering in it I had to also add wrappers for setOpaquePointers()
and isOpaquePointer().

I also changed echo.ll to remove a bitcast i32* %x to i8*, because
passing it through llvm-as and llvm-dis was generating a
%0 = bitcast ptr %x to ptr, but when building that same bitcast in
echo.cpp it was getting elided by IRBuilderBase::CreateCast
(https://github.com/llvm/llvm-project/blob/08ac66124874d70dab63c731da0244f9e29ef168/llvm/include/llvm/IR/IRBuilder.h#L1998-L1999).

Differential Revision: https://reviews.llvm.org/D125183
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedllvm/tools/llvm-c-test/llvm-c-test.h
The file was modifiedllvm/tools/llvm-c-test/main.c
The file was modifiedllvm/test/Bindings/llvm-c/echo.ll
The file was modifiedllvm/include/llvm-c/Core.h
The file was modifiedllvm/tools/llvm-c-test/echo.cpp
Commit 71cb8c8cb9c162448159f2bffd2c77a8ee82d71f by sam.mccall
[clangd] parse all make_unique-like functions in preamble

I am working on support for forwarding parameter names in make_unique-like functions, first for inlay hints, later maybe for signature help.
For that to work generically, I'd like to parse all of these functions in the preamble. Not sure how this impacts performance on large codebases though.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D124688
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TestTU.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TestTU.h
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/Compiler.h
The file was modifiedclang-tools-extra/clangd/Preamble.cpp
The file was modifiedclang-tools-extra/clangd/tool/Check.cpp
Commit 9dffab9d524a05742a765dea27aedc8a7080a402 by owenca
[clang-format][NFC] Don't call mightFitOnOneLine() unnecessarily

Clean up UnwrappedLineParser for RemoveBracesLLVM to avoid calling
mightFitOnOneLine() as much as possible.

Differential Revision: https://reviews.llvm.org/D125626
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
The file was modifiedclang/lib/Format/FormatToken.h
The file was modifiedclang/lib/Format/UnwrappedLineParser.h
Commit 8903dbef8ff675e0529ee83ab8c5191ba466e380 by dantrushin
[StatepointLowering] Properly handle local and non-local relocates of the same value.

FunctionLoweringInfo::StatepointRelocationMaps map is used to pass GC pointer
lowering information from statepoint to gc.relocate  which may appear ini
different block.
D124444 introduced different lowering for local and non-local relocates.
Local relocates use SDValue and non-local relocates use value exported to VReg.
But I overlooked the fact that StatepointRelocationMap is indexed not by
GCRelocate instruction, but by derived pointer. This works incorrectly when
we have two relocates (one local and another non-local) of the same value,
because they need different relocation records.

This patch fixes the problem by recording relocation information per relocate
instruction, not per derived pointer. This way, each gc.relocate can be lowered
differently.

Reviewed By: skatkov

Differential Revision: https://reviews.llvm.org/D125538
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-details.ll
Commit 4c3e51ecfa3337be2d091392d6174449aeb35aa3 by david.green
[AArch64] Handle 64bit vectors in tryCombineFixedPointConvert

Under some situations we can visit 64bit vector extract elements in
tryCombineFixedPointConvert, where an assert fires as they are expected
to have been converted to 128bit. Turn the assert into an if statement,
bailing out and letting the extract be handled first.

Also invert some ifs, using early exits to reduce indentation.

Fixes #55417
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
Commit 26a61ab6789fdcc3ad094f09e19e5d653bb86e36 by yeting.kuo
[SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags.

The patch make users not need to know getNode with SDNodeFlags argument may not
pass its flags.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125659
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit fab5c853ff78bdd72f2cc7e75766d065e6cf55ad by llvm-dev
[X86][AVX] Add test showing poor expansion of bit-reversal permutation shuffles

Reported here: https://discourse.llvm.org/t/ir-alternatives-to-freeze-to-selectively-prevent-compiler-from-combining-shufflevectors/62521
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Commit f96d20450c00855a842d91d09cbcf765adaf1f17 by abinavpp
[AMDGPU][GlobalISel] Pre-commit tests for D125516

Differential Revision: https://reviews.llvm.org/D125539
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
Commit 485dd0b752cd78c93b1c41e922a73c07b565a9f0 by abinavpp
[GlobalISel] Handle constant splat in funnel shift combine

This change adds the constant splat versions of m_ICst() (by using
getBuildVectorConstantSplat()) and uses it in
matchOrShiftToFunnelShift(). The getBuildVectorConstantSplat() name is
shortened to getIConstantSplatVal() so that the *SExtVal() version would
have a more compact name.

Differential Revision: https://reviews.llvm.org/D125516
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
Commit aab5bd180a42f7501a91bcaa5b4906ba7e67ce0e by ox59616e
[ADT] Adopt the new casting infrastructure for PointerUnion

Reviewed By: lattner, bzcheeseman

Differential Revision: https://reviews.llvm.org/D125609
The file was modifiedllvm/include/llvm/ADT/PointerUnion.h
The file was modifiedllvm/unittests/ADT/PointerUnionTest.cpp
Commit e473e79cd194d7a74158ff7e8b97076a7f71c511 by david.spickett
[lldb][NFC] Make cmd a reference in GenerateOptionUsage

Nowhere in lldb do we call this with a null pointer.
If we did, the first line of the function would fault anyway.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D125218
The file was modifiedlldb/source/Commands/CommandObjectFrame.cpp
The file was modifiedlldb/source/Interpreter/Options.cpp
The file was modifiedlldb/source/Interpreter/CommandObject.cpp
The file was modifiedlldb/source/Commands/CommandObjectTarget.cpp
The file was modifiedlldb/include/lldb/Interpreter/Options.h
The file was modifiedlldb/source/Commands/CommandObjectDisassemble.cpp
Commit 4a94e3801dd721c0083c1259d019a1540388d9d3 by david.spickett
[lldb][NFC] Simplify GenerateOptionUsage

Once we get into the if block we know the value of only_print_args.
Move some variables closer to point of use.

Depends on D125218

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D125219
The file was modifiedlldb/source/Interpreter/Options.cpp
Commit 1ddc6ab1a9c321e02da4fab836c5f863a906108b by Tim Northover
AArch64: support ISel for fence instructions

Only the most conservative of the DAG patterns matched, leaving GISel with "dmb
ish" everywhere which is inefficient.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/fence-singlethread.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
Commit 7ff5148d6454531dd138f6ef5be77d14f732754f by bradley.smith
[DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine

Differential Revision: https://reviews.llvm.org/D125367
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-fold-loadext-and-splat-vector.ll
Commit ec4adf1f6c333d3d36663d8f763c0896407f1b61 by biplob.mishra
[InstCombine] Combine instructions of type or/and where AND masks can be combined.

The patch simplifies some of the patterns as below

(A | (B & C0)) | (B & C1) -> A | (B & C0|C1)
((B & C0) | A) | (B & C1) -> (B & C0|C1) | A

In some scenarios like byte reverse on half word, we can see this pattern multiple times and this conversion can optimize these patterns.

Differential Revision: https://reviews.llvm.org/D124119
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-or.ll
Commit acc80ea71bac51458df9d75552651e7c161db64b by hokein.wu
[AST] Cleanup on getting the underlying decl of using-shdow decl.

This should be a NFC cleanup. It removes a unnecessary loop to get the underlying
decl, and add an assertion.

The underlying decl of a using-shadow decl is always the original declaration
has been brought into the scope, clang never builds a nested using-shadow
decl (see Sema::BuildUsingShadowDecl).

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D123422
The file was modifiedclang/lib/AST/DeclCXX.cpp
The file was modifiedclang/lib/AST/Decl.cpp
Commit 80bebbc7cb77979ef9d229450b7ea84e3e9c6a5a by nathan
[clang][NFC] Cleanup some coroutine tests

I noticed these two tests emit a warning about a missing
unhandled_exception.  That's irrelevant to what is being tested, but
is unnecessary noise.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D125535
The file was modifiedclang/test/CodeGenCoroutines/coro-ret-void.cpp
The file was modifiedclang/test/CoverageMapping/coroutine.cpp
Commit aa656f6c2dec73faceeed21e15401d8f0c743c8b by Louis Dionne
[runtimes] Introduce object libraries

This is a variant of D116689 rebased on top of the new (proposed) ABI
refactoring in D120727. It should conserve the basic properties of the
original patch by @phosek, except it also allows cleaning up the merging
of libc++abi into libc++ from the libc++ side.

Differential Revision: https://reviews.llvm.org/D125393
The file was modifiedlibcxxabi/src/CMakeLists.txt
The file was modifiedlibunwind/cmake/Modules/HandleLibunwindFlags.cmake
The file was removedlibcxx/utils/merge_archives.py
The file was modifiedlibcxx/src/CMakeLists.txt
The file was modifiedlibunwind/src/CMakeLists.txt
The file was modifiedlibcxxabi/cmake/Modules/HandleLibcxxabiFlags.cmake
The file was modifiedlibcxx/cmake/Modules/HandleLibCXXABI.cmake
Commit d95513ae3a73388cbe18fa1bd2c76fec70f3ec06 by Liqin.Weng
[RISCV] remove useless code

When legality check for vectoring reduction, hasVInstructions() check be unneeded. RISCV can only loop vectorization with hasVInstructions()

Reviewed By: kito-cheng, craig.topper

Differential Revision: https://reviews.llvm.org/D125460
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Commit 06400a0142af8297b5d39b8f34a7c59db6f9910c by Louis Dionne
[runtimes] Generalize how we reorder projects

This way, we could use it for LLVM_ENABLE_PROJECTS too if desired.

Differential Revision: https://reviews.llvm.org/D125121
The file was modifiedruntimes/CMakeLists.txt
The file was addedcmake/Modules/SortSubset.cmake
Commit ff3f4988ed5837d1a99b3dd6bb10acc0aefab60a by Liqin.Weng
[CodeGen] Use ArrayRef in TargetLowering functions

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123656
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit 6f8726191960f068d1068f84dfb9077d85c64fb9 by n.james93
[clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVisitors

Reimplement the matching logic using Visitors instead of matchers.

Benchmarks from running the check over SemaCodeComplete.cpp
Before 0.20s, After 0.04s

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D125026
The file was modifiedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.h
The file was modifiedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.cpp
The file was removedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprMatchers.h
The file was modifiedclang-tools-extra/unittests/clang-tidy/ReadabilityModuleTest.cpp
Commit 59c3be748f89d9084ac71b28784fd4e26322e181 by joker.eph
Apply clang-tidy fixes for performance-move-const-arg in SerializeToHsaco.cpp (NFC)
The file was modifiedmlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
Commit 08482fa05882560a34d9b1a30b387496b86cedf9 by joker.eph
Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cpp (NFC)
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
Commit b147717bb36c915bedfb33c07259cac4f09502a1 by steplong
[MSVC] Add support for pragma alloc_text

`#pragma alloc_text` is a MSVC pragma that names the code section where functions should be placed. It only
applies to functions with C linkage.

https://docs.microsoft.com/en-us/cpp/preprocessor/alloc-text?view=msvc-170

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D125011
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was addedclang/test/CodeGen/msvc_pragma_alloc_text.cpp
The file was modifiedclang/lib/Parse/ParsePragma.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was addedclang/test/Sema/pragma-ms-alloc-text.cpp
Commit c70259405c61b203682e2a03c4688c6d6bc89856 by Joseph.Nash
[AMDGPU] gfx11 BUF Instructions

Includes MachineCode layer support and tests, and MIR tests not requiring
CodeGen pass changes.
Includes a small change in SMInstructions.td to correct encoded bits.

Contributors:
Petar Avramovic <Petar.Avramovic@amd.com>
Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>

Depends on D125316

Patch 6/N for upstreaming of AMDGPU gfx11 architecture.

Reviewed By: dp, Petar.Avramovic

Differential Revision: https://reviews.llvm.org/D125319
The file was addedllvm/test/MC/Disassembler/AMDGPU/mtbuf_dasm_gfx11.txt
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
The file was addedllvm/test/MC/AMDGPU/gfx11_mtbuf.s
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/MC/AMDGPU/gfx11_mubuf_alias.s
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was addedllvm/test/MC/Disassembler/AMDGPU/mubuf_dasm_gfx11.txt
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was addedllvm/test/MC/AMDGPU/gfx11_mubuf.s
The file was addedllvm/test/MC/AMDGPU/gfx11_mtbuf_alias.s
Commit 8ab819ad90d647b96bb4b6842a742d2552ba9e9c by npopov
[ConstantRange] Add toKnownBits() method

Add toKnownBits() method to mirror fromKnownBits(). We know the
top bits that are constant between min and max.

The return value for an empty range is chosen to be conservative.
The file was modifiedllvm/include/llvm/IR/ConstantRange.h
The file was modifiedllvm/lib/IR/ConstantRange.cpp
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
Commit 27fa41583fdee54d40ae680408f697e6d8201a8c by jay.foad
[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10

On GFX10 VOP3 instructions can have a literal operand, so the conversion
from VOP3 MAD/FMA to VOP2 MADAK/MADMK/FMAAK/FMAMK will not happen in
SIFoldOperands. The only benefit of the VOP2 form is code size, so do it
in SIShrinkInstructions instead.

Differential Revision: https://reviews.llvm.org/D125567
The file was modifiedllvm/test/CodeGen/AMDGPU/madak.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Commit 6ef17f20d940dc771c14b83ac1eabdb526575b2a by Joseph.Nash
[AMDGPU] Mark sendmsg hasSideEffects. NFC

Address the FIXME by marking the sendmsg instructions with
hasSideEffects.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D125569
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
Commit b7315ffc3c92d2408780b5748cbac1c651128079 by flo
[LAA,LV] Add initial support for pointer-diff memory checks.

This patch adds initial support for a pointer diff based runtime check
scheme for vectorization. This scheme requires fewer computations and
checks than the existing full overlap checking, if it is applicable.

The main idea is to only check if source and sink of a dependency are
far enough apart so the accesses won't overlap in the vector loop. To do
so, it is sufficient to compute the difference and compare it to the
`VF * UF * AccessSize`. It is sufficient to check
`(Sink - Src) <u VF * UF * AccessSize` to rule out a backwards
dependence in the vector loop with the given VF and UF. If Src >=u Sink,
there is not dependence preventing vectorization, hence the overflow
should not matter and using the ULT should be sufficient.

Note that the initial version is restricted in multiple ways:

1. Pointers must only either be read or written, by a single
   instruction (this allows re-constructing source/sink for
   dependences with the available information)
2. Source and sink pointers must be add-recs, with matching steps
3. The step must be a constant.
3. abs(step) == AccessSize.

Most of those restrictions can be relaxed in the future.

See https://github.com/llvm/llvm-project/issues/53590.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D119078
The file was modifiedllvm/test/Transforms/LoopVectorize/fpsat.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/runtime-check.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
The file was modifiedllvm/include/llvm/Analysis/LoopAccessAnalysis.h
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/test/Transforms/LoopVectorize/no_outside_user.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/runtime-check-readonly.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/multiple-exits-versioning.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/tbaa-nodep.ll
Commit 356d47ccb9b5f69b8b984d37a8b3c8813a84413b by npopov
[ValueTracking] Handle and/or on RHS of isImpliedCondition()

isImpliedCondition() currently handles and/or on the LHS, but not
on the RHS, resulting in asymmetric behavior. This patch adds two
new implication rules:

* LHS ==> (RHS1 || RHS2) if LHS ==> RHS1 or LHS ==> RHS2
* LHS ==> !(RHS1 && RHS2) if LHS ==> !RHS1 or LHS ==> !RHS2

Differential Revision: https://reviews.llvm.org/D125551
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/InstSimplify/select-implied.ll
The file was modifiedllvm/test/Transforms/InstSimplify/and-or-implied-cond.ll
Commit 152072801e24fb1e5cd962b0cb089230bc27b6b9 by a.bataev
[SLP]Check if the root of the buildvector has one use only.

The root of the buildvector can have only one use, otherwise it can be
treated only as a final element of the previous buildvector sequence.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 242910ac3abcdfeb80b3ae2806dc84773f23341a by spatel
[InstCombine] fix test name; NFC

The bug number was typo'd when it was added for D86243.
The file was modifiedllvm/test/Transforms/InstCombine/and-xor-merge.ll
Commit 325896d82339d7328bdaf54b23f2f26cc289d597 by spatel
[PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC

The tests (see C++ source in #54692) have multiple potential
optimizations/canonicalizations, but we should be consistent
since they are logically identical.
The file was addedllvm/test/Transforms/PhaseOrdering/cmp-logic.ll
Commit 7272a8c23ceb218b3bd6f0dd303c6df2c773cc74 by david.green
[AArch64] Update check lines in arm64-scvt.ll. NFC
The file was modifiedllvm/test/CodeGen/AArch64/arm64-scvt.ll
Commit 3cc2c7deed5bb711ab2e4408a692c77f71836933 by llvm-dev
[polly] Remove 'using namespace llvm/polly' from ScopGraphPrinter.h header.

As mentioned on D123678 this appears to be causing namespace resolution issues on some versions of gcc.
The file was modifiedpolly/include/polly/ScopGraphPrinter.h
Commit 55e2df7285c0c60da44a2dccbbb1da7d1c0da2ce by preames
[LiveIntervals] Add range accessors for value numbers [nfc]
The file was modifiedllvm/include/llvm/CodeGen/LiveInterval.h
The file was modifiedllvm/lib/CodeGen/LiveIntervals.cpp
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
Commit be7f09f7b2e83ca4aebb3bdbb83ad1d19662b993 by spatel
[IR] create and use helper functions that test the signbit; NFCI
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 6e23cd2bf073ab5eb5a103b935af54046d007c52 by ellis.sparky.hoag
[InstrProf][NFC] Save profile bias to function map

Add a map from functions to load instructions that compute the profile bias. Previously we assumed that if the first instruction in the function was a load instruction, then it must be computing the bias. This was likely to work out because functions usually start with the `llvm.instrprof.increment` instruction, but optimizations could change this. For example, inlining into a non-profiled function.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D114319
The file was modifiedllvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
Commit f287da8a158113840aeabd04b641d0d2815212f2 by springerm
[mlir][bufferize] Better user control of layout maps

This changes replaces the `fully-dynamic-layout-maps` options (which was badly named) with two new options:

* `unknown-type-conversion` controls the layout maps on buffer types for which no layout map can be inferred.
* `function-boundary-type-conversion` controls the layout maps on buffer types inside of function signatures.

Differential Revision: https://reviews.llvm.org/D125615
The file was modifiedmlir/test/Dialect/Linalg/one-shot-bufferize.mlir
The file was modifiedmlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
The file was modifiedmlir/test/Dialect/SCF/one-shot-bufferize.mlir
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
The file was modifiedmlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
The file was modifiedmlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
The file was modifiedmlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
The file was modifiedmlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
The file was modifiedmlir/docs/Bufferization.md
The file was modifiedmlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
The file was modifiedmlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-allow-return-allocs.mlir
The file was modifiedmlir/test/Dialect/Tensor/one-shot-bufferize.mlir
The file was modifiedmlir/test/Dialect/Arithmetic/one-shot-bufferize.mlir
The file was modifiedmlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-partial.mlir
Commit acfd0a345619c9293ac8fa5f690fa78b27a10814 by hoy
[llvm-profgen] Update callsite body samples by summing up all call target samples.

Current profile generation caculcates callsite body samples and call target samples separately. The former is done based on LBR range samples while the latter is done based on branch samples. Note that there's a subtle difference. LBR ranges is formed from two consecutive branch samples. Therefore the last entry in a LBR record will not be counted towards body samples while there's still a chance for it to be counted towards call targets if it is a function call. I'm making sense of the call body samples by updating it to the aggregation of call targets.

Reviewed By: wenlei

Differential Revision: https://reviews.llvm.org/D122609
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.cpp
The file was modifiedllvm/include/llvm/ProfileData/SampleProf.h
The file was modifiedllvm/test/tools/llvm-profgen/noinline-noprobe.test
The file was modifiedllvm/test/tools/llvm-profgen/inline-noprobe2.test
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.h
The file was addedllvm/test/tools/llvm-profgen/update-samples.test
Commit e2df48bb23d714c031d4a3a4f614e9d863d6c412 by preames
[RISCV] Add further trace output to InsertVSETLVI
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit e6fc8454bee5dc89be27fe1db826fb0bb30d74aa by craig.topper
[DAGCombiner] Fix incorrect indentation. NFC
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 1c4880a2d39fbd95edced0dd97c34a9f53bf62ff by craig.topper
[TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift.

If we use multiply it would be with 0x0101 which is 1 more than a power
of 2. On some targets we would expand this to shl+add. By avoiding the
multiply earlier, we can generate better code.

Note, PowerPC doesn't do the shl+add expansion of multiply so one of
the tests increased in instruction count.

Limiting to scalars because it almost always increased the number of
instructions in vector tests.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D125638
The file was modifiedllvm/test/CodeGen/PowerPC/popcnt-zext.ll
The file was modifiedllvm/test/CodeGen/X86/parity-vec.ll
The file was modifiedllvm/test/CodeGen/X86/popcnt.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
Commit 74f6ded49d8cc745cb28b74e57346d948bac2b2d by craig.topper
[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

This bug is in generic DAG combine and easily reproducible on many
targets.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D125640
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/test/CodeGen/X86/bswap.ll
The file was modifiedllvm/test/CodeGen/Thumb/rev.ll
The file was modifiedllvm/test/CodeGen/RISCV/bswap-bitreverse.ll
The file was modifiedllvm/test/CodeGen/ARM/rev.ll
Commit 836305b24ca7a0dea0f80873bfa79d417d4d798d by spatel
[InstCombine] add tests for zext-of-signbit test; NFC
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
Commit 3794cc0e996481e10307b67c8436aa44e0d65d22 by spatel
[InstCombine] invert canonicalization for cast of signbit test

The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
The file was modifiedllvm/test/Transforms/InstCombine/compare-signs.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/cmp-logic.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-xor-merge.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
Commit 5d29d752735e71b73a54bfc9ab747384be9e4246 by david.green
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32

There have been some patterns in the AArch64 backend to optimize code of
the form:
  ldrsh w8, [x0]
  scvtf s0, w8
to:
  ldr h0, [x0]
  sshll v0.4s, v0.4h, #0
  scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.

This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.

Differential Revision: https://reviews.llvm.org/D125470
The file was modifiedllvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/arm64-scvt.ll
Commit 9c7c8be4a316c9cfcfd064e5dada250a99c405c7 by Adrian Prantl
Remove stale file from modulemap
The file was modifiedllvm/include/llvm/module.modulemap
Commit 5f7ef65245372b9e5d2979a11b57ac8aab4306a6 by rahmanl
[llvm-objdump] Let --symbolize-operands symbolize basic block addresses based on the SHT_LLVM_BB_ADDR_MAP section.

`--symbolize-operands` already symbolizes branch targets based on the disassembly. When the object file is created with `-fbasic-block-sections=labels` (ELF-only) it will include a SHT_LLVM_BB_ADDR_MAP section which maps basic blocks to their addresses. In such case `llvm-objdump` can annotate the disassembly based on labels inferred on this section.

In contrast to the current labels, SHT_LLVM_BB_ADDR_MAP-based labels are created for every machine basic block including empty blocks and those which are not branched into (fallthrough blocks).

The old logic is still executed even when the SHT_LLVM_BB_ADDR_MAP section is present to handle functions which have not been received an entry in this section.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D124560
The file was modifiedllvm/lib/Object/ELFObjectFile.cpp
The file was modifiedllvm/unittests/Object/ELFObjectFileTest.cpp
The file was modifiedllvm/include/llvm/Object/ELFObjectFile.h
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was addedllvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
The file was modifiedllvm/docs/CommandGuide/llvm-objdump.rst
The file was modifiedllvm/include/llvm/Object/ELFTypes.h
Commit babbd96f23d5e21712223ece8f6318e6bc93269b by i
[docs] Re-generate ClangCommandLineReference.rst
The file was modifiedclang/docs/ClangCommandLineReference.rst
Commit 0b69b8384d9b92898ec29f78a2364bec2277e516 by i
[Driver] Change "zlib not installed" diagnostic to "zlib not enabled"

The former is a bit misleading and a user may try installing zlib which
will not help.
The file was modifiedclang/test/Driver/nozlibcompress.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
Commit ffc3a0db003fa9e26b25e55011d83e3fbb5a7ac2 by kubak
[mlir:toy][NFC] Remove unnecessary trailing return type

In this instance, the trailing return type does not improve readability
as it repeats what is returned in the same line.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125697
The file was modifiedmlir/examples/toy/Ch7/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch1/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch2/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch5/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch6/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch4/include/toy/AST.h
The file was modifiedmlir/examples/toy/Ch3/include/toy/AST.h
Commit 92030635318d615f72cd0cd539e458f9cdd9949b by asb
[WebAssembly][TableGen][NFCI] Use getValueAsBit rather than converting TableGen 'bit' to string

The logic around IsCanonical previously used getAsString and compared to
"1". Just using getValueAsBit is simpler.
The file was modifiedllvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
Commit 5edd7665fd163555f1afe2187907eba95d24c11b by usx
Add documentHighlight in clangd check for performance measurements.

Differential Revision: https://reviews.llvm.org/D125682
The file was modifiedclang-tools-extra/clangd/tool/Check.cpp
Commit 332b73fe12c6b383168e03eddd92020d38bc7583 by Stanislav.Mekhanoshin
[AMDGPU] Revert wide LDS DMA support.

This reverts ffbee7acdcaaf, see also bug 37653 which it was fixing.
The bug claims this is an undocumented feature which actually works.
In the reality it is documented as not working for a good reason.
It likely does something, but it is useless anyway. These instructions
write into the LDS. The LDS address is:

M0 + inst_offset + (TIDinWave * 4).

For a store wider than a DWORD neighboring lanes will overwrite each
other.

Differential Revision: https://reviews.llvm.org/D125409
The file was modifiedllvm/test/MC/AMDGPU/mubuf.s
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
Commit 52c615553cd9f774c618ff26507606a1469b40f3 by zhijian
[AIX] fixed llvm-ar can not read empty big archive correctly.

Summary:

llvm-ar can not read empty big archive correctly. it output error as
error: unable to load 'empty.a': truncated or malformed archive (characters in size field in archive member header are not all decimal numbers: '<bigaf>'

Reviewers: James Henderson
Differential Revision: https://reviews.llvm.org/D124017
The file was modifiedllvm/test/tools/llvm-ar/display-empty.test
The file was modifiedllvm/include/llvm/Object/Archive.h
The file was modifiedllvm/test/tools/llvm-ar/quick-append.test
The file was modifiedllvm/test/tools/llvm-lipo/create-archive-input.test
The file was modifiedllvm/test/tools/llvm-size/archive.test
The file was modifiedllvm/test/tools/llvm-ar/full-path-option.test
Commit cb4a5eae1eb3fb8be8c0cf73aa9b1e6f9279eda6 by suderman
[mlir][tosa] Use math.ctlz intrinsic for tosa.clz

We were custom counting per bit for the clz instruction. Math dialect
now has an intrinsic to do this in one instruction. Migrated to this
instruction and fixed a minor bug math-to-llvm for the intrinsic.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D125592
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/MathToLLVM/MathToLLVM.cpp
Commit 2fb6ece2ca83d33909c628d682f821d05aa67a97 by usx
Optimise findRefs for XRefs and docHighlights

Reduces time spent in findRef by 66%.

Differential Revision: https://reviews.llvm.org/D125675
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
Commit d4aacc1a013e9de4011adb051cdcae1ae6fc9baf by eugenis
[sanitizer] Don't use newfstatat for Linux on SPARC

Linux on SPARC uses fstatat64 instead.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D125572
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Commit efcee4b06d2f8ee6c79dd893b702f073593d5823 by Louis Dionne
[libc++] Remove the legacy LIBCXX_LIBCPPABI_VERSION option

I think this notion of libc++abi's version was relevant a long time ago
on Apple platforms when we were using a Xcode project to build the library.
As part of moving Apple's build to CMake, D59489 made it possible to
specify the "ABI version" of libc++abi in use. However, it's not possible
to build libc++abi with that old ABI anymore and we don't need the ability
to link against that version from libc++ anymore.

Hence, we can clean this up and stop falsely pretending that libc++abi
has more than one ABI version.

Differential Revision: https://reviews.llvm.org/D125687
The file was modifiedlibcxx/CMakeLists.txt
The file was removedlibcxx/lib/libc++abi.v1.exp
The file was addedlibcxx/lib/libc++abi.exp
The file was modifiedlibcxx/src/CMakeLists.txt
The file was removedlibcxx/lib/libc++abi.v2.exp
Commit 193f458c30106b114b81cb7b2d21de41099f5191 by Louis Dionne
[libc++] Remove overly conservative error in <stdatomic.h>

As mentionned in D97044, it is fine if users include <atomic> and then
include <stdatomic.h> -- we don't need to error out for that case.

Differential Revision: https://reviews.llvm.org/D125579
The file was removedlibcxx/test/libcxx/atomics/stdatomic.h.syn/incompatible_with_atomic.verify.cpp
The file was modifiedlibcxx/include/stdatomic.h
The file was modifiedlibcxx/test/libcxx/atomics/atomics.syn/incompatible_with_stdatomic.verify.cpp
Commit 7dd05ba9ed5e8c8f0f9a9bd979b6c7a70799aed6 by paul.walker
[SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes.

During early gather/scatter enablement two different approaches
were taken to represent scaled indices:

* A Scale operand whereby byte_offsets = Index * Scale
* An IndexType whereby byte_offsets = Index * sizeof(MemVT.ElementType)

Having multiple representations is bad as shown by this patch which
fixes instances where the two are out of sync. The dedicated scale
operand is more flexible and pervasive so this patch removes the
UNSCALED values from IndexType. This means all indices are scaled
but the scale can be one, hence unscaled. SDNodes now use the scale
operand to answer the "isScaledIndex" question.

I toyed with the idea of keeping the UNSCALED enums and helper
functions but because they will have no uses and force SDNodes to
validate the set of supported values I figured it's best to remove
them. We can re-add them if there's a real need. For similar
reasons I've kept the IndexType enum when a bool could be used as I
think being explicitly looks better.

Depends On D123347

Differential Revision: https://reviews.llvm.org/D123381
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 7dce9eb6e507d48d0b79bfb408592936d378cc28 by llvm-project
[DomPrinter] Migrate -dot-dom to the new pass manager.

In D123677, @YangKeao provided an implementation of `DOTGraphTraits{Viewer,Printer}` in the new pass manager. This commit migrates the `DomPrinter` and `DomViewer` to the new pass manager.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D124904
The file was modifiedllvm/include/llvm/Analysis/DomPrinter.h
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Analysis/Analysis.cpp
The file was modifiedllvm/include/llvm/LinkAllPasses.h
The file was modifiedllvm/include/llvm/Analysis/PostDominators.h
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/lib/Analysis/DomPrinter.cpp
Commit 736c1b66ef332014d0e183627d32edb39a3016dd by ajcbik
[mlir][sparse] introduce complex type to sparse tensor support

This is the first implementation of complex (f64 and f32) support
in the sparse compiler, with complex add/mul as first operations.
Note that various features are still TBD, such as other ops, and
reading in complex values from file. Also, note that the
std::complex<float> had a bit of an ABI issue when passed as
single argument. It is still TBD if better solutions are possible.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D125596
The file was modifiedmlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/CodegenUtils.cpp
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
The file was modifiedmlir/include/mlir/ExecutionEngine/SparseTensorUtils.h
Commit 0533253d81d8ab2641549963c7ad37dfccd39734 by jeffniu22
[mlir][ods] Ignore AttributeSelfTypeParameter in assembly formats

The attribute self type parameter is currently treated like any other attribute parameter in the assembly format. The self type parameter should be handled by the operation parser and printer and play no role in the generated parsers and printers of attributes.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125724
The file was modifiedmlir/test/lib/Dialect/Test/TestAttrDefs.td
The file was modifiedmlir/test/mlir-tblgen/attr-or-type-format.td
The file was modifiedmlir/test/lib/Dialect/Test/TestAttributes.cpp
The file was modifiedmlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
The file was modifiedmlir/test/mlir-tblgen/testdialect-attrdefs.mlir
Commit c38ef550de81631641cb1485e0641d1d2227dce4 by zhijian
[AIX] llvm-link support big archive.

Summary:
Use object::Archive::create so that the returned archive object has a dynamic type of either Archive or BigArchive.

Reviewers: James Henderson,Fangrui Song
Differential Revision: https://reviews.llvm.org/D124940
The file was modifiedllvm/tools/llvm-link/llvm-link.cpp
The file was modifiedllvm/test/tools/llvm-link/archivell.ll
Commit c8457eb5323ca99361c1748a22a16edb3160ae5f by jeffniu22
[mlir][transforms] Add a topological sort utility and pass

This patch adds a topological sort utility and pass. A topological sort reorders
the operations in a block without SSA dominance such that, as much as possible,
users of values come after their producers.

The utility function sorts topologically the operation range in a given block
with an optional user-provided callback that can be used to virtually break cycles.
The toposort pass itself recursively sorts graph regions under the target op.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D125063
The file was modifiedmlir/include/mlir/Transforms/Passes.h
The file was addedmlir/include/mlir/Transforms/TopologicalSortUtils.h
The file was addedmlir/lib/Transforms/TopologicalSort.cpp
The file was modifiedmlir/lib/Transforms/Utils/CMakeLists.txt
The file was addedmlir/test/Transforms/test-toposort.mlir
The file was addedmlir/lib/Transforms/Utils/TopologicalSortUtils.cpp
The file was modifiedmlir/include/mlir/Transforms/Passes.td
The file was modifiedmlir/lib/Transforms/CMakeLists.txt
Commit a6cef03f66ca76169ba629d21f1245b50b646ee0 by riddleriver
[mlir] Remove the `type` keyword from type alias definitions

This was carry over from LLVM IR where the alias definition can
be ambiguous, but MLIR type aliases have no such problems.
Having the `type` keyword is superfluous and doesn't add anything.
This commit drops it, which also nicely aligns with the syntax for
attribute aliases (which doesn't have a keyword).

Differential Revision: https://reviews.llvm.org/D125501
The file was modifiedmlir/test/mlir-cpu-runner/utils.mlir
The file was modifiedmlir/test/Dialect/Quant/parse-calibrated.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_mttkrp.mlir
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_spmm.mlir
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/test/Dialect/Quant/parse-calibrated-invalid.mlir
The file was modifiedmlir/test/Dialect/Quant/parse-uniform.mlir
The file was modifiedmlir/test/IR/parser.mlir
The file was modifiedflang/test/Fir/array-value-copy-3.fir
The file was modifiedmlir/test/Integration/Dialect/Linalg/CPU/benchmark_matmul.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pytaco_utils.py
The file was modifiedmlir/test/Dialect/LLVMIR/types.mlir
The file was modifiedflang/test/Fir/affine-promotion.fir
The file was modifiedmlir/test/IR/print-attr-type-aliases.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_flatten.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was modifiedflang/test/Fir/ignore-missing-type-descriptor.fir
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/test/IR/invalid.mlir
The file was modifiedmlir/utils/tree-sitter-mlir/grammar.js
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-f32.mlir
The file was modifiedmlir/docs/LangRef.md
The file was modifiedmlir/test/Dialect/Quant/parse-uniform-invalid.mlir
The file was modifiedmlir/test/Dialect/Quant/parse-any-invalid.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-i64.mlir
The file was modifiedflang/test/Fir/recursive-type.fir
The file was modifiedmlir/test/Dialect/Quant/parse-any.mlir
The file was modifiedmlir/docs/TargetLLVMIR.md
The file was modifiedmlir/test/Conversion/FuncToLLVM/func-memref.mlir
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td
Commit 67f0e8eec33812fdd531f9d4776ddfe5cabec5c3 by jeffniu22
[mlir][ods] Fix verification of attribute + colon type ambiguity

An attribute without a type builder followed by a colon in an assembly format is potentially ambiguous because the parser will read ahead to parse the colon-type and pass this as the type argument to the attribute's constructor.

However, the previous verifier that checks for this ambiguity erroneously produces an error in the case of

```
let assemblyFormat = "( `(` $attr `)` )? `:`";
```

This patch fixes the bug by implementing a checker that correctly handles all edge cases, including very strange assembly formats like:

```
let assemblyFormat = "( `(` $attr ) : (`>`)? attr-dict (`>` $a^) : (`<`)? `:`";
```

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125445
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was addedmlir/test/mlir-tblgen/op-format-verify.td
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/test/mlir-tblgen/op-format-spec.td
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
Commit 0b293bf0451cd695239867d8dac9b239ab601a70 by springerm
[mlir][bufferize] Better propagation of errors

Return immediately when an op bufferization patterns fails.

Differential Revision: https://reviews.llvm.org/D125087
The file was modifiedmlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
The file was modifiedmlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
The file was modifiedmlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
The file was modifiedmlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
Commit 9a90ea1fdcd29f7245ec0bc1295ce96fc0ec2365 by ellis.sparky.hoag
[InstrProf] Fix promoter when using counter relocations

When using counter relocations, two instructions are emitted to compute
the address of the counter variable.

```
%BiasAdd = add i64 ptrtoint <__profc_>, <__llvm_profile_counter_bias>
%Addr = inttoptr i64 %BiasAdd to i64*
```

When promoting a counter, these instructions might not be available in
the block, so we need to copy these instructions.

This fixes https://github.com/llvm/llvm-project/issues/55125

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125710
The file was modifiedllvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
The file was addedllvm/test/Transforms/PGOProfile/counter_promo_with_bias.ll
Commit ee8aa351e43f27e1dd4240560a3e054ca045186f by paul.walker
[AArch64] Use ADDV for boolean xor reductions.

NEON does not have native support for xor reductions. However, when
reducing predicate vectors the operation is synonymous with an add
reduction that is supported.

Differential Revision: https://reviews.llvm.org/D125605
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/reduce-xor.ll
Commit dd20323f51b676bd0f13c82dc1587e8afcdd527a by efriedma
[compiler-rt builtins] Assert that atomic.c can be compiled correctly.

The spinlock requires that lock-free operations are available;
otherwise, the implementation just calls itself. As discussed in
D120026.

Differential Revision: https://reviews.llvm.org/D123080
The file was modifiedcompiler-rt/lib/builtins/atomic.c
Commit 68f37e7991bf41a6f3fb3dd12d0e7a42822de347 by martin
[ARM] Rename the isARMAreaXRegister parameter isIOS to SplitFramePushPop. NFC.

In f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c in 2016, this parameter
was generalized on the caller side (previously passing
STI.isTargetMachO(), now passing STI.splitFramePushPop()). Rename
the parameter on the receiver side to match the generalization.

Differential Revision: https://reviews.llvm.org/D125681
The file was modifiedllvm/lib/Target/ARM/ARMBaseRegisterInfo.h
Commit cabefea2ec99f80ecdf9d3d5fe955831532ff4b0 by martin
[MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog

The "packed epilog" form only implies that the epilog is located
exactly at the end of the function (so the location of the epilog
is implicit from the epilog opcodes), but it doesn't have to share
opcodes with the prolog - as long as the total number of opcode
bytes and the offset to the epilog fit within the bitfields.

This avoids writing a 4 byte epilog scope in many cases. (I haven't
measured how much this shrinks actual xdata sections in practice
though.)

Differential Revision: https://reviews.llvm.org/D125536
The file was modifiedllvm/test/CodeGen/AArch64/wineh2.mir
The file was modifiedllvm/test/MC/AArch64/seh-packed-epilog.s
The file was modifiedllvm/test/CodeGen/AArch64/wineh1.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh5.mir
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
The file was modifiedllvm/test/MC/AArch64/seh-optimize.s
Commit 64a3c63e01c5f71659797acb511f18628f41d0d8 by martin
[MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64

This allows sharing opcodes between prolog and epilog even when there
is more than one epilog.

I didn't make any handcrafted special MC level testcases for this (yet
at least), but it does seem to have the expected effect on two existing
CodeGen level testcases.

Differential Revision: https://reviews.llvm.org/D125619
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
The file was modifiedllvm/test/CodeGen/AArch64/wineh8.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh4.mir
Commit 07d549bce94fc86fb1dc37aa0fb328e77208a185 by spatel
Revert "[InstCombine] invert canonicalization for cast of signbit test"

This reverts commit 3794cc0e996481e10307b67c8436aa44e0d65d22.
This change is suspected of causing bots to hang at stage 2
compiles, so reverting to confirm and investigate.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/cmp-logic.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
The file was modifiedllvm/test/Transforms/InstCombine/and-xor-merge.ll
The file was modifiedllvm/test/Transforms/InstCombine/compare-signs.ll
Commit 9defb3b4b4a3ab5a95c449471aaa930cf63a7106 by Jonas Devlieghere
[lldb] Prevent underflow in crashlog.py

Avoid a OverflowError (an underflow really) when the pc is zero. This
can happen for "unknown frames" where the crashlog generator reports a
zero pc. We could omit them altogether, but if they're part of the
crashlog it seems fair to display them in lldb as well.

rdar://92686666

Differential revision: https://reviews.llvm.org/D125716
The file was modifiedlldb/examples/python/crashlog.py
Commit 18fc39590978949fb75969e4bd63f8d2f13288ad by zinenko
[mlir] allow for re-registering extension ops

Op registration mechanism does not allow for ops with the same name to be
re-registered. This is okay to avoid name conflicts and debug
double-registration, but may be problematic for dialect extensions that may get
registered several times (unlike dialects that are deduplicated in the
registry). When registering ops through the Transform dialect extension
mechanism, check first if the ops are already registered and only complain in
the case of repeated registration with the same name but different TypeID.

Differential Revision: https://reviews.llvm.org/D125554
The file was modifiedmlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
Commit 5ffecd28c9fb3098049f0477759f779122153499 by jhuber6
[Libomptarget] Don't build the device runtime without a new Clang

The OpenMP device offloading library is a bitcode library and thus only
expect to build and linked with the same version of clang that was used
to create it. This somewhat copmlicates the building process as we
require the Clang that was just built to be used to create the library.
This is either done with a two-step build, where OpenMP is built with
the Clang that was just installed, or through the
`-DLLLVM_ENABLE_RUNTIMES=openmp` option. This has always been the case,
but recent changes have caused this to make it difficult to build the
rest of OpenMP. This patchs adds a check to not build the OpenMP device
runtime if the current compiler is not Clang with the same version as
the LLVM installation. This should allow users to build OpenMP as a
project using any compiler without it erroring out due to the bitcode
library, but if users require it they will need to use the above methods
to compile it.

Reviewed By: jdoerfert, tianshilei1992, ye-luo

Differential Revision: https://reviews.llvm.org/D125698
The file was modifiedopenmp/libomptarget/DeviceRTL/CMakeLists.txt
Commit b653b409ff44b09ade04bb6e579f5f9790424611 by jhuber6
[OpenMP] Don't build the offloading driver without a source input

The Clang driver additional stages to build a complete offloading
program for applications using CUDA or OpenMP offloading. This normally
requires either a source file input or a valid object file to be
handled. This would cause problems when trying to compile an assembly or
LLVM IR file through clang with flags that would enable offloading. This
patch simply adds a check to prevent the offloading toolchain from being
used if we don't have a valid source file.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D125705
The file was modifiedclang/lib/Driver/Driver.cpp
The file was modifiedclang/test/Driver/openmp-offload-gpu-new.c
Commit d2f3b6020fbfa2dd56ebd03c942acda961c421e2 by Jason Molenda
[NFC] Don't bother with unstripped binary w/ dSYM, don't DebugSymbols twice

This patch addresses two perf issues when we find a dSYM on macOS
after calling into the DebugSymbols framework.  First, when we have
a local (probably stripped) binaary, we find the dSYM and we may
be told about the location of the symbol rich binary (probably
unstripped) which may be on a remote filesystem.  We don't need the
unstripped binary, use the local binary we already have.
Second, after we've found the path to the dSYM, save that in the Module
so we don't call into DebugSymbols a second time later on to
rediscover it.  If the user has a DBGShellCommands set, we need to
exec that process twice, serially, which can add up.

Differential Revision: https://reviews.llvm.org/D125616
rdar://84576917
The file was modifiedlldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
The file was modifiedlldb/source/Symbol/LocateSymbolFileMacOSX.cpp
Commit e0c3b94c80143376473ec7110ca0c8a4fe03112e by riddleriver
[mlir] Restrict dialect doc gen to a single dialect

In the overwhelmingly majority of cases only one dialect is generated at a time
anyways, and this restriction more easily catches user error when multiple
dialects might be generated. We hit this semi-recently with the PDL dialect,
and circt+other downstream users are also actively hitting this as well.

Differential Revision: https://reviews.llvm.org/D125651
The file was addedmlir/tools/mlir-tblgen/DialectGenUtilities.h
The file was modifiedmlir/tools/mlir-tblgen/OpDocGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/DialectGen.cpp
The file was modifiedmlir/include/mlir/Dialect/AMX/CMakeLists.txt
The file was modifiedmlir/test/mlir-tblgen/gen-dialect-doc.td
The file was modifiedmlir/include/mlir/Dialect/ArmNeon/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/ArmSVE/CMakeLists.txt
Commit 8cb332406c09c6cd03a70d02fe925840a15d6509 by 2998727+wrengr
[mlir][sparse] Enhancing sparse=>sparse conversion.

Fixes: https://github.com/llvm/llvm-project/issues/51652

Depends On D122060

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D122061
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/python/test_stress.py
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2sparse.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
Commit 76944420115364a8d259b299ca688b18118ae1b6 by 2998727+wrengr
[mlir][sparse] Adding "final" keyword wherever appropriate

This enables the compiler to perform devirtualization.  And benchmarks
indicate devirtualization can sometimes give considerable speedup.

Depends On D122061

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125428
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
Commit 45e01ce5fe6a5e4dc25ffdf626caa344fbcb93dd by ndesaulniers
[clang] Avoid suggesting typoed directives in `.S` files

This patch is itended to avoid suggesting typoed directives in `.S`
files to support the cases of `#` directives treated as comments or
various pseudo-ops. The feature is implemented in
https://reviews.llvm.org/D124726.

Fixes: https://reviews.llvm.org/D124726#3516346.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D125727
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was addedclang/test/Preprocessor/suggest-typoed-directive.S
Commit 5de12bb703c5104b3fd64ee51c6900d6171d826a by riddleriver
[mlir][Tablegen-LSP] Add support for a basic TableGen language server

This follows the same general structure of the MLIR and PDLL language
servers. This commits adds the basic functionality for setting up the server,
and initially only supports providing diagnostics. Followon commits will
build out more comprehensive behavior.

Realistically this should eventually live in llvm/, but building in MLIR is an easier
initial step given that:
* All of the necessary LSP functionality is already here
* It allows for proving out useful language features (e.g. compilation databases)
  without affecting wider scale tablegen users
* MLIR has a vscode extension that can immediately take advantage of it

Differential Revision: https://reviews.llvm.org/D125440
The file was modifiedmlir/tools/CMakeLists.txt
The file was modifiedmlir/utils/vscode/package.json
The file was addedmlir/test/tblgen-lsp-server/exit-eof.test
The file was addedmlir/test/tblgen-lsp-server/diagnostics.test
The file was addedmlir/lib/Tools/tblgen-lsp-server/TableGenServer.cpp
The file was addedmlir/test/tblgen-lsp-server/exit-with-shutdown.test
The file was addedmlir/lib/Tools/tblgen-lsp-server/TableGenLspServerMain.cpp
The file was addedmlir/lib/Tools/tblgen-lsp-server/TableGenServer.h
The file was addedmlir/utils/vscode/tablegen-language-configuration.json
The file was addedmlir/lib/Tools/tblgen-lsp-server/CMakeLists.txt
The file was modifiedmlir/test/CMakeLists.txt
The file was addedmlir/lib/Tools/tblgen-lsp-server/LSPServer.h
The file was addedmlir/test/tblgen-lsp-server/exit-without-shutdown.test
The file was modifiedmlir/utils/vscode/src/mlirContext.ts
The file was modifiedmlir/lib/Tools/lsp-server-support/CMakeLists.txt
The file was addedmlir/lib/Tools/lsp-server-support/SourceMgrUtils.h
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
The file was modifiedmlir/utils/vscode/.gitignore
The file was addedmlir/lib/Tools/lsp-server-support/SourceMgrUtils.cpp
The file was addedmlir/tools/tblgen-lsp-server/tblgen-lsp-server.cpp
The file was addedmlir/lib/Tools/tblgen-lsp-server/LSPServer.cpp
The file was modifiedmlir/docs/Tools/MLIRLSP.md
The file was addedmlir/tools/tblgen-lsp-server/CMakeLists.txt
The file was addedmlir/test/tblgen-lsp-server/initialize-params-invalid.test
The file was modifiedmlir/lib/Tools/CMakeLists.txt
The file was addedmlir/include/mlir/Tools/tblgen-lsp-server/TableGenLspServerMain.h
The file was addedmlir/test/tblgen-lsp-server/initialize-params.test
Commit 0d863b5b90a2f11e58b0b54d7183cb1577fd3a0b by keithbsmiley
[llvm-objcopy][test] Add cmp after copy

All of the other tests here either check that the copy fails, or that
the resulting binary is the same, it seems like this check was omitted
for the universal object case.

Differential Revision: https://reviews.llvm.org/D125478
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/universal-object.test
Commit 9f39867b103213d34121668381cb7dc054eda068 by riddleriver
[mlir][NFC] Fix a few langref typos
The file was modifiedmlir/docs/LangRef.md
Commit 52ddae132f8ccd646e93d42b69f1efd902ecb4f2 by Ben.Dunbobbin
[llvm-ar][NFC] Address post-commit comments on D125439.

Remove errant whitespace.

AIX uses big archive format so check for both !<arch> and <bigaf>.

Only the "gnu" format has thin archives; specify --format=gnu for
thin archive test-cases.
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
The file was modifiedllvm/test/tools/llvm-ar/mri-create-overwrite.test
Commit 7dbf2e7b576f52f1c459665fe524d7521d560dae by preames
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)

The existing redundant copy elimination required a virtual register source, but the same logic works for any physreg where we don't have to worry about clobbers.  On RISCV, this helps eliminate redundant CSR reads from VLENB.

Differential Revision: https://reviews.llvm.org/D125564
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/CodeGen/PeepholeOptimizer.cpp
The file was modifiedllvm/test/CodeGen/RISCV/vlenb.ll
Commit 1313f5d3071c5aee6eaf3c366747d44585522fb4 by 2998727+wrengr
[mlir][sparse] Restyling macros in the runtime library

In addition to reducing code repetition, this also helps ensure that the various API functions follow the naming convention of mlir::sparse_tensor::primaryTypeFunctionSuffix (e.g., due to typos in the repetitious code).

Depends On D125428

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125431
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
Commit 1febbd67aa9cf31119398dde27d2dbf016de351e by riddleriver
[mlir][PDLL] Tweak the grammar to highlight partial code better

This commit enables proper highlighting when inner statements are
outside of a constraint/pattern/etc. This shouldn't really happen in
actual code, but can happen in documentation (which uses the same
syntax grammar).
The file was modifiedmlir/utils/vscode/pdll-grammar.json
Commit 6593886a35025af7b32e5d317dd91779bf60014f by riddleriver
[mlir][NFC] Fix the tags for various doc code blocks
The file was modifiedmlir/docs/Interfaces.md
The file was modifiedmlir/docs/DataLayout.md
The file was modifiedmlir/docs/PassManagement.md
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/docs/AttributesAndTypes.md
Commit 4c5b187f2c065648799e109a6754917e642dc659 by vyng
[lld-macho] Demangle symbol names in export-symbol error messages when -demangle is specified.
PR/55512

Reviewed By: keith

Differential Revision: https://reviews.llvm.org/D125732
The file was modifiedlld/test/MachO/demangle.s
The file was modifiedlld/MachO/Driver.cpp
Commit 4680982b36a84770a1600fc438be8ec090671724 by 31459023+hctim
[dwarf] Emit a DIGlobalVariable for constant strings.

An upcoming patch will extend llvm-symbolizer to provide the source line
information for global variables. The goal is to move AddressSanitizer
off of internal debug info for symbolization onto the DWARF standard
(and doing a clean-up in the process). Currently, ASan reports the line
information for constant strings if a memory safety bug happens around
them. We want to keep this behaviour, so we need to emit debuginfo for
these variables as well.

Reviewed By: dblaikie, rnk, aprantl

Differential Revision: https://reviews.llvm.org/D123534
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was removedllvm/test/Assembler/invalid-diglobalvariable-missing-name.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was addedclang/test/CodeGen/debug-info-variables.c
The file was modifiedclang/test/VFS/external-names.c
The file was addedllvm/test/DebugInfo/COFF/global-no-strings.ll
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
Commit f20e6a6e61da83fbc444e21aa51f4794d1273bec by smeenai
[test-suite][cmake] sort unit test targets

This patch sorts unit test targets into directories corresponding to the
test source file directories to improve target navigation.

Reviewed By: smeenai

Differential Revision: https://reviews.llvm.org/D124810
The file was modifiedllvm/unittests/DebugInfo/DWARF/CMakeLists.txt
The file was modifiedllvm/unittests/ExecutionEngine/JITLink/CMakeLists.txt
The file was modifiedllvm/unittests/Target/PowerPC/CMakeLists.txt
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
The file was modifiedllvm/unittests/Transforms/Vectorize/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/CMakeLists.txt
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
The file was modifiedllvm/unittests/DebugInfo/PDB/CMakeLists.txt
The file was modifiedllvm/unittests/DebugInfo/GSYM/CMakeLists.txt
The file was modifiedllvm/unittests/Target/X86/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-cfi-verify/CMakeLists.txt
The file was modifiedllvm/unittests/ExecutionEngine/CMakeLists.txt
The file was modifiedllvm/unittests/Target/WebAssembly/CMakeLists.txt
The file was modifiedllvm/unittests/Transforms/IPO/CMakeLists.txt
The file was modifiedllvm/unittests/DebugInfo/MSF/CMakeLists.txt
The file was modifiedllvm/unittests/Target/ARM/CMakeLists.txt
The file was modifiedllvm/unittests/CMakeLists.txt
The file was modifiedllvm/unittests/DebugInfo/CodeView/CMakeLists.txt
The file was modifiedllvm/unittests/Target/AArch64/CMakeLists.txt
The file was modifiedllvm/unittests/ExecutionEngine/MCJIT/CMakeLists.txt
The file was modifiedllvm/unittests/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/unittests/Transforms/Scalar/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-profgen/CMakeLists.txt
Commit 3d17c917099a691e12f05d2502d81b972600a4ae by preames
[RISCV] Fix missing vsetvli in transparent block case

We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible miscompiles. D119518 introduced a workaround, but failed to consider blocks which only contain load/stores compatible with their incoming state.

When I went to rebase and simplify D125232, it turned out that not all of the correctness issues had been fixed yet after all. This is the correctness fix accidentally embedded in the original more complicated version.

Note that the test changes here are mostly regressions. It's worth noting that the simplified version of D125232 exactly reverses all the non-functional diffs in the test caused here. D125232 should be the immediate following commit.

Differential Revision: https://reviews.llvm.org/D125703
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit 1474880353f12a5a1beb62fc873477a8a2e6afda by preames
[RISCV] Use classic dataflow for VSETVLI insertion

Our current implementation of the InsertVSETVLI dataflow allows phase 3 to arrive at a different block end state than the data flow in phase 1/2 computed. This arises because a block which contains instructions (e.g. load or stores) which don't consume all the incoming bits of the VL/VTYPE can be compatible with multiple incoming states. The algorithm effectively changes the SEW on such instructions, and propagates the prior state forward. As phase 3 uses the block input state for this propagation, but phase 1/2 doesn't, this can result in different block end states.

If we don't correct for it, this discrepancy can result in miscompiles. This was the source of multiple recent bugs. However, by now we have fixes for all known correctness issues.

The basic strategy we use is to insert a compensation vsetvli to bring the block state leaving the block back into consistency with the one computed. This is correct, but results in extra vsetvlis being placed at the end of blocks.

This change adjusts the phase 1/2 algorithm to propagate the incoming block state through the block, allowing the compatibility rules to modify the end state. The algorithm may need to run slightly more iterations, but the end result is consistent with what phase 3 does.

The benefit of doing this is two fold.

First, we reverse some of the code quality introductions introduced in the functional fixes.

Second, we simplify the invariants, and allow the strict assertions to be enabled. Several humans, myself included, have found it quite surprising that invariant didn't hold already, and arguably that confusion is the cause of several of our recent miscompiles in this code.

The downside to this patch is that the dataflow may require additional iterations to stabilize. In the worse case, we go from O(Edges) to O(E + UniquePaths) as the incoming state (and thus the outgoing one) can now change once for each path from the entry block.

Differential Revision: https://reviews.llvm.org/D125232
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit a997cdc3b798e6294ceb32bcece62abe6276aae1 by vyng
[lld-macho] Temporarily disable test on windows
The metadata seems to be demangled differently
The file was modifiedlld/test/MachO/demangle.s
Commit bd9e46815d73e4236c207bad8b5c54e7188154d7 by vyng
[nfc][lld-macho] Fixed test from https://reviews.llvm.org/D125732

Details:
The test was incorrectly expecting the error messages for the export symbols to have a particular order.
It shouldn't because the export symbol list is processed concurrently.
The file was modifiedlld/test/MachO/demangle.s
Commit 82a13d05ab7184a93befe7c5c284b79596cd5fb3 by tlively
[WebAssembly] Update relaxed SIMD opcodes and names

to reflect the latest state of the proposal:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format.
Moves code around to match the instruction order from the proposal, but the only
functional changes are to the names and opcodes.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D125726
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/MC/WebAssembly/simd-encodings.s
Commit bfadd13df474aac157d759cea946f1e5c1297000 by 2998727+wrengr
[mlir][sparse] Moved _mlir_ciface_newSparseTensor closer to its macros

This is a followup to D125431, to keep from confusing the machinery that generates diffs (since combining these two changes into one would obfuscate the changes actually made in the previous differential).

Depends On D125431

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125432
The file was modifiedmlir/lib/ExecutionEngine/SparseTensorUtils.cpp
Commit 3cde6d83f86c274e5608abfe852b95fd6668f9fd by vyng
[nfc][lld-macho] Follow up fixes to bd9e46815d73e4236c207bad8b5c54e7188154d7

Need -DAG in the first expect statement too
The file was modifiedlld/test/MachO/demangle.s
Commit ed2c3218f5badf88cb7897fabf8faa01e8aa2044 by 31459023+hctim
Revert "[dwarf] Emit a DIGlobalVariable for constant strings."

This reverts commit 4680982b36a84770a1600fc438be8ec090671724.

Broke a fuchsia windows bot. More details in the review:
https://reviews.llvm.org/D123534
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
The file was removedclang/test/CodeGen/debug-info-variables.c
The file was removedllvm/test/DebugInfo/COFF/global-no-strings.ll
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was addedllvm/test/Assembler/invalid-diglobalvariable-missing-name.ll
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedclang/test/VFS/external-names.c
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
Commit 452fac9534c00290e92819202d445810e33d0444 by yedeng.yd
[Frontend] [Coroutines] Emit error when we found incompatible allocation
function in promise_type

According to https://cplusplus.github.io/CWG/issues/2585.html, this
fixes https://github.com/llvm/llvm-project/issues/54881

Simply, the clang tried to found (do lookup and overload resolution. Is
there any better word to use than found?) allocation function in
promise_type and global scope. However, this is not consistent with the
standard. The standard behavior would be that the compiler shouldn't
lookup in global scope in case we lookup the allocation function name in
promise_type. In other words, the program is ill-formed if there is
incompatible allocation function in promise type.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D125517
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was addedclang/test/SemaCXX/coroutine-allocs.cpp
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
Commit 9b519f416b70db0fa3bba020732988d3555a3625 by jacquesguan
[mlir][LLVMIR] Add support for translating insertelement/extractelement.

Add support for translating llvm::InsertElement and llvm::ExtractElement.

Differential Revision: https://reviews.llvm.org/D125674
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/test/Target/LLVMIR/Import/basic.ll
Commit 63c81b23bebed8ca39cf73715952fd40947b5b02 by luxufan
[RISCV] Support getHostCpuName for sifive-u74

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D123978
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedllvm/include/llvm/Support/Host.h
The file was modifiedllvm/unittests/Support/Host.cpp
Commit f305ac3d5d0e02df68efbad42ab9c209f99d51a7 by qiaopeixin
[flang][OpenMP] Support lowering to MLIR for ordered clause

This supports the lowering parse-tree to MLIR for ordered clause in
worksharing-loop directive. Also add the test case for operation
conversion.

Part of this patch is from the fir-dev branch of
https://github.com/flang-compiler/f18-llvm-project.

Co-authored-by: Sourabh Singh Tomar <SourabhSingh.Tomar@amd.com>

Reviewed By: kiranchandramohan, NimishMishra

Differential Revision: https://reviews.llvm.org/D125456
The file was modifiedflang/lib/Lower/OpenMP.cpp
The file was addedflang/test/Lower/OpenMP/omp-wsloop-ordered.f90
Commit 5646d82885f64f1f886d84aff5422697f355f6c4 by qiaopeixin
[flang] Add one semantic check for elemental call arguments

As Fortran 2018 15.8.1(3), in a reference to an elemental procedure, if
any argument is an array, each actual argument that corresponds to an
INTENT (OUT) or INTENT (INOUT) dummy argument shall be an array. Add
this semantic check.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D125685
The file was modifiedflang/test/Semantics/call02.f90
The file was modifiedflang/lib/Semantics/check-call.cpp
Commit a694546f7cdf6fbcacddf229eeff5316e4bd0eae by npopov
[KnownBits] Add operator==

Checking whether two KnownBits are the same is somewhat common,
mainly in test code.

I don't think there is a lot of room for confusion with "determine
what the KnownBits for an icmp eq would be", as that has a
different result type (this is what the eq() method implements,
which returns Optional<bool>).

Differential Revision: https://reviews.llvm.org/D125692
The file was modifiedllvm/include/llvm/Support/KnownBits.h
The file was modifiedllvm/lib/Support/KnownBits.cpp
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
The file was modifiedllvm/unittests/Support/KnownBitsTest.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit 599ff247dee8f462638731c3b2fdd3d1e332a2fe by fraser
[StackColoring] Don't merge slots with differing StackIDs

The documentation for this specifically mentions that this should not
happen. We could think about adding target hooks to permit it (and how
to merge IDs) in the future if that is desirable.

This specific test case was merging a scalable-vector slot into a
non-scalable one and dropping the notion of scalability, meaning we
failed to allocate enough stack space for the object.

Reviewed By: arsenm, MaskRay, sdesmalen

Differential Revision: https://reviews.llvm.org/D125699
The file was addedllvm/test/CodeGen/RISCV/rvv/stack-coloring-scalablevec.mir
The file was modifiedllvm/lib/CodeGen/StackColoring.cpp
Commit 821522d343cd127312fb07b53aa99e22b3aacc0c by fraser
[RISCV] Add a test w/ RVV stack objects misaligning non-RVV ones

This patch adds a simple test which demonstrates a miscompilation of
16-byte-aligned scalar (non-RVV) objects when combined with RVV stack
objects.

The RISCV stack is assumed to be aligned to 16 bytes, and this is
guaranteed/assumed to be true when setting up the stack. However, when
the stack contains RVV objects, we decrement the stack pointer by some
multiple of vlenb, which is only guaranteed to be aligned to 8 bytes.
This means that non-RVV objects specifically requiring 16-byte alignment
fall through the cracks and are misaligned. Objects requiring larger
alignment trigger stack realignment and thus should be okay.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125382
The file was addedllvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
Commit 2db4dc7ec0595dae4b2fb5499da698eb117e2dc7 by npopov
[ConstantRange] Implement binaryXor() using known bits

This allows us to compute known high bits. It's not optimal, but
better than nothing.
The file was modifiedllvm/lib/IR/ConstantRange.cpp
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
Commit c8322adfcf8a1e8959b0e4b95ec821aac915dc58 by npopov
[CVP] Add test for xor (NFC)
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/basic.ll
Commit b9b71c2b872dbb4e0a06187d7f4b48ece8a57495 by npopov
[LVI] Compute range for xor

We do have a non-trivial implementation for binaryXor() now.
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/basic.ll
Commit 8d6e2c3e3db1d8a6474b24e42c7b52d788405cbc by esme.yi
[XCOFF] support writing sections, relocations and symbols for XCOFF64.

This is the second patch to enable the XCOFF64 object writer.

Reviewed By: jhenderson, shchenz

Differential Revision: https://reviews.llvm.org/D122287
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-dwarf.ll
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-return55.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern-weak.ll
The file was modifiedllvm/test/MC/PowerPC/ppc64-abs-reloc.s
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/basic-toc-data-def.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-weak.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-available-externally-linkage.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-huge-relocs.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-lower-comm.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-internal.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-func-align.ll
Commit a9127eb538947307bcba6be93f26fb97e1d2f117 by phosek
[llvm] Fix typo for libxml2 detection

This seems to be a copy-paste from the similar zlib detection code.

Patch By: sthibaul

Differential Revision: https://reviews.llvm.org/D117052
The file was modifiedllvm/lib/WindowsManifest/CMakeLists.txt
Commit 6c81079edf26da23f977a82e82f72cc6abd9cafd by Chenbing.Zheng
[InstCombine] precommit tests for foldSelectToCopysign
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
Commit 05ad4d4f38689114a54f79fdd07d18552ee902e2 by fraser
[RISCV][NFC] Fix comment typos in split SP adjustment
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 26593e73147d5d66d87ad1a69faeaad6776b8d1d by jacquesguan
[SelectionDAG] Support more VP reduction mask operation.

This patch uses VP_REDUCE_AND and VP_REDUCE_OR to replace VP_REDUCE_SMAX,VP_REDUCE_SMIN,VP_REDUCE_UMAX and VP_REDUCE_UMIN for mask vector type.

Differential Revision: https://reviews.llvm.org/D125002
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
Commit 1075c8ca49b467ec5e654a4322fbb36f63e8687f by zinenko
[mlir] support isa/cast/dyn_cast<Operation *>(operation) again

The support for this has been added by 946311b8938114a37db5c9d42fb9f5a1481ccae1
but then ignored by bc22b5c9a2f729460ffdf7627b3534a8d9f3f767.

This enables one to write generic code that can be instantiated for both
specific operation classes and the common base class without
specialization. Examples include functions that take/return ops, such
as:

```mlir
template <typename FnTy>
void applyIf(FnTy &&lambda, ...) {
  for (Operation *op : ...) {
    auto specific = dyn_cast<function_traits<FnTy>::template arg_t<0>>(op);
    if (specific)
      lambda(specific);
  }
}
```

that would otherwise need to rely on template specialization to support
lambdas that take specific operations and those that take `Operation *`.

Differential Revision: https://reviews.llvm.org/D125543

Reviewed by: rriddle
The file was modifiedmlir/include/mlir/IR/Operation.h
Commit f00f894d5d828c3ea7757f62268eaa4cd9a28c88 by fraser
[RISCV][NFC] Reword split SP adjustment comments
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 9983b978f756f150caf6ac4fb2c74bd8c71de7c0 by dvassiliev
[SROA] Precommit test for D124967
The file was addedllvm/test/Transforms/SROA/lifetime-intrinsic.ll
Commit 7759680e2f88f6d055c37aeb77302874a72f19ce by dvassiliev
[SROA] Avoid postponing rewriting load/store by ignoring lifetime intrinsics in partition's promotability checking

This patch fixes a bug that generates unnecessary packing/unpacking structure code because of incorrectly handling lifetime intrinsic.
For example, a partition of an alloca may contain many slices:
```
Partition [0, 4):
  Slice0: [0, 4) used by: load i32 addr;
  Slice1: [0, 4) used by: store i32 v, addr;
  Slice2: [0, 16) used by lifetime.start(16, addr);
```
When SROA determines if the partition can be promoted, lifetime.start is currently treated as a whole alloca load/store, so Slice0 and Slice1 cannot be promoted at this attempt,
but the packing/unpacking code for Slice0 and Slice1 has been generated.
After rewrite lifetime.start/end intrinsic, SROA tries again with Slice0 and Slice1 and finally promotes them, but redundant packing/unpacking code remaining in the IRs.
This patch changes promotability checking to ignore lifetime intrinsic (they will be rewritten to correct sizes later), so we can promote the real users (load/store) at the first attempt with optimal code.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D124967
The file was modifiedllvm/test/Transforms/SROA/lifetime-intrinsic.ll
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
Commit 4d9c083437f729df0c17980cf0ef36f943e9e0bf by a.v.lapshin
[DWARFLinker][NFC] Add None value to the DwarfLinkerAccelTableKind enum.

this review is extracted from D86539.

1. Rename AccelTableKind to DwarfLinkerAccelTableKind
   (to differentiate from AccelTableKind from CodeGen/AsmPrinter/DwarfDebug.h)

2. Add None value to the DwarfLinkerAccelTableKind.

3. added 'None' value for 'accelerator' option of dsymutil.

Differential Revision: https://reviews.llvm.org/D125474
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was modifiedllvm/tools/dsymutil/Options.td
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
The file was modifiedllvm/docs/CommandGuide/dsymutil.rst
The file was modifiedllvm/test/tools/dsymutil/X86/accelerator.test
The file was modifiedllvm/tools/dsymutil/dsymutil.cpp
The file was modifiedllvm/tools/dsymutil/LinkUtils.h
Commit 9ba452b08eb5368bd89126102031b687d0ecdbaf by npopov
[JumpThreading] Don't pass DT to isGuaranteedNotToBeUndefOrPoison()

JumpThreading intentionally does not force updating of the DT
during optimization, because this may be expensive when many CFG
updates and DT calculations are interleaved.

We shouldn't be fetching the DT just for the purpose of calling
isGuaranteedNotToBeUndefOrPoison(), especially as DT availability
doesn't even show benefit in tests.
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
Commit b250cca11d5996ed01d72cb1f933867da0e8d5e0 by sven.vanhaastregt
[OpenCL] Do not guard vload/store_half builtins

The vload*_half* and vstore*_half* builtins do not require the
cl_khr_fp16 extension: pointers to `half` can be declared without the
extension and the _half variants of vload and vstore should be
available without the extension.

This aligns the guards for these builtins for
`-fdeclare-opencl-builtins` with `opencl-c.h`.

Fixes https://github.com/llvm/llvm-project/issues/55275

Differential Revision: https://reviews.llvm.org/D125401
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
The file was modifiedclang/test/SemaOpenCL/half.cl
The file was modifiedclang/lib/Headers/opencl-c-base.h
Commit c64f5d44ad3bebeaccceb20b2730b4e65bb87297 by llvm-dev
[X86] Attempt to fold EFLAGS into X86ISD::ADD/SUB ops

We already use combineAddOrSubToADCOrSBB to fold extended EFLAGS results into ISD::ADD/SUB ops as X86ISD::ADC/SBB carry ops.

This patch extends this to also try to fold EFLAGS results with X86ISD::ADD/SUB ops

Differential Revision: https://reviews.llvm.org/D125642
The file was modifiedllvm/test/CodeGen/X86/add-sub-bool.ll
The file was modifiedllvm/test/CodeGen/X86/subcarry.ll
The file was modifiedllvm/test/CodeGen/X86/addcarry.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sbb.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 601ed0b605310cc13d7ca7235c261dc95c2ced44 by asb
[WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string

This is (IMHO) cleaner and (objectively) more strongly typed than using strings.

A follow-on patch will do the same for IsWasm64.

Differential Revision: https://reviews.llvm.org/D125713
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
The file was modifiedllvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
Commit 8a23df89dadd336f42cde669de72a1ffe86bee83 by asb
[WebAssembly][NFC] Convert IsWasm64 instruction field to 'bit' from string

Extends the cleanup in D125713 to IsWasm64.

Differential Revision: https://reviews.llvm.org/D125714
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
Commit b3bd7328355f2ca7403debe8ca6fdf7b84aaa413 by npopov
[JumpThreading] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/JumpThreading/select.ll
Commit 8311fb75127d2d85752392d1b521da53e969d76d by david.green
[AArch64] Extra tests useful for D-lane shuffles. NFC
The file was addedllvm/test/CodeGen/AArch64/reduce-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/shuffles.ll
Commit c1a9d14982f887355da1959eba3a47b952fc6e7a by flo
[VPlan] Move usesScalars/onlyFirstLaneUsed to VPUser.

Those helpers model properties of a user and they should also be
available to non-recipe users. This will be used in D123537 for a new
exit value user.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D124936
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Commit 9e469ced42cd9335baffd906bed17fd81ce4e6e8 by david.spickett
[mlir][Tablegen-LSP] Don't link with llvm dylib

This updates 5de12bb703c5104b3fd64ee51c6900d6171d826a
to not link with the dylib since that does not include
the tablegen library.

Should fix flang dylib build failures:
https://lab.llvm.org/buildbot/#/builders/177/builds/5120
The file was modifiedmlir/lib/Tools/tblgen-lsp-server/CMakeLists.txt
Commit 77480556c41fbca36b918323c69cb77f8e02b56c by jay.foad
[RegAllocGreedy] New hook regClassPriorityTrumpsGlobalness

Add a new TargetRegisterInfo hook to allow targets to tweak the
priority of live ranges, so that AllocationPriority of the register
class will be treated as more important than whether the range is local
to a basic block or global. This is determined per-MachineFunction.

Differential Revision: https://reviews.llvm.org/D125102
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was addedllvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
The file was modifiedllvm/include/llvm/Target/Target.td
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.h
Commit df2a4eae6b190806c0b96ef3312975e1c97dbda0 by zeratul976
[clang] Expose CoawaitExpr's operand in the AST

Previously the Expr returned by getOperand() was actually the
subexpression common to the "ready", "suspend", and "resume"
expressions, which often isn't just the operand but e.g.
await_transform() called on the operand.

It's important for the AST to expose the operand as written
in the source for traversals and tools like clangd to work
correctly.

Fixes https://github.com/clangd/clangd/issues/939

Differential Revision: https://reviews.llvm.org/D115187
The file was modifiedclang/include/clang/AST/ExprCXX.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/AST/coroutine-source-location-crash-exp-namespace.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/test/AST/coroutine-locals-cleanup-exp-namespace.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/test/AST/coroutine-source-location-crash.cpp
The file was modifiedclang/test/AST/coroutine-locals-cleanup.cpp
The file was addedclang/test/SemaCXX/co_await-ast.cpp
Commit 6de59ca417b491c5ca2ab189aaae83e62369695a by Louis Dionne
[libc++] Introduce LIBCXX_LIBRARY_VERSION

This allows controlling the current_version linker property on Apple
platforms.

Differential Revision: https://reviews.llvm.org/D125686
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/src/CMakeLists.txt
Commit d40b7f0d5aec3b70bd2a5d42c71b1ebb5c28a03b by llvm-dev
[DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses

If we're using shift pairs to mask, then relax the one use limit if the shift amounts are equal - we'll only be generating a single AND node.

AArch64 has a couple of regressions due to this, so I've enforced the existing one use limit inside a AArch64TargetLowering::shouldFoldConstantShiftPairToMask callback.

Part of the work to fix the regressions in D77804

Differential Revision: https://reviews.llvm.org/D125607
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-lo16.ll
The file was modifiedllvm/test/CodeGen/ARM/combine-movc-sub.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
Commit 99639e5a3e6e7f3f207128fc3bfd707596d5ba59 by kamau.bridgeman.ibm
Enabling the detection of devtoolset-11 toolchain.

This patch allows systems to build the llvm-project with the devtoolset-11
toolchain.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125499
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
Commit 329dc5587cea126d203945f0d75eccb6a0eb4258 by kkleine
[pgo] Fix doc typo: thingswith -> things with

The title says it all.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D125763
The file was modifiedllvm/utils/collect_and_build_with_pgo.py
Commit b0f0313febe755eeb7bacd62cf5862d9812f1690 by a.bataev
[SLP]Add an  extra check for select minmax reduction to avoid crash.

Need to check if the reduction is still (not)cmp-select pattern min/max
reduction to avoid compiler crash during building list of reduction
operations. cmp-sel pattern provides 2 reduction operations, while
intrinsics - just one.
The file was addedllvm/test/Transforms/SLPVectorizer/X86/reduction-min-select.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 86bc6399a063439f2c58f9eed3ee6bf2d9276bf6 by hokein.wu
[pseudo] Add the missing ; terminal for module-declaration rule.
The file was modifiedclang-tools-extra/pseudo/lib/cxx.bnf
Commit 6da3d66f03f9162ef341cc67218be40e22fe9808 by erich.keane
[concepts] Implement dcl.decl.general p4: No constraints on non-template funcs

The standard says:
The optional requires-clause ([temp.pre]) in an init-declarator or
member-declarator shall be present only if the declarator declares a
templated function ([dcl.fct]).

This implements that limitation, and updates the tests to the best of my
ability to capture the intent of the original checks.

Differential Revision: https://reviews.llvm.org/D125711
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/CXX/over/over.match/over.match.best/p1-2a.cpp
The file was modifiedclang/test/Parser/cxx2a-concepts-requires-expr.cpp
The file was modifiedclang/test/CXX/dcl/dcl.decl/p3.cpp
The file was addedclang/test/CXX/dcl.decl/dcl.decl.general/p4-20.cpp
The file was modifiedclang/test/Parser/cxx-concepts-requires-clause.cpp
The file was modifiedclang/test/CXX/over/over.match/over.match.viable/p3.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.id/p4.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/CXX/over/over.over/p4-2a.cpp
The file was modifiedclang/test/SemaCXX/cxx20-check-fptr-constraints.cpp
Commit 9c6a2f29660b886044a267bb4de662cd801079bc by gribozavr
Fix an unused variable warning in no-asserts build mode
The file was modifiedclang-tools-extra/pseudo/lib/GLR.cpp
Commit 9bb0f4616a75515e93981af05e58f186ac7714ce by cullen.rhodes
[mlir][licm] Fix debug output with newlines
The file was modifiedmlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
Commit 6ad6b00f6a47cd23b882f65ba6da45e227ba536a by cullen.rhodes
[mlir] vim: add bf16 type
The file was modifiedmlir/utils/vim/syntax/mlir.vim
Commit 2def74bef15a867d940520ddf3808d09b7fff95b by erich.keane
Fix release note typo from 6da3d66f
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 5df22e507b1bd267457d815050b94e81692c33dd by npopov
[IRBuilder] Move insertvalue/extractvalue to fold infrastructure

Move from the old CreateXYZ() to the new FoldXYZ() mechanism.

This change is likely NFC in practice, because I don't think that
the places using InstSimplifyFolder use insertvalue/extractvalue.
The file was modifiedllvm/include/llvm/IR/ConstantFolder.h
The file was modifiedllvm/include/llvm/Analysis/TargetFolder.h
The file was modifiedllvm/include/llvm/Analysis/InstSimplifyFolder.h
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/include/llvm/IR/NoFolder.h
The file was modifiedllvm/include/llvm/IR/IRBuilderFolder.h
Commit 5caa7038a4ca712fcf975f0277263f2119a627cb by jakeegan10
[NFC][AIX] Reenable mri1.test

This test is passing now because of D124017 and D123949.

Reviewed By: DiggerLin

Differential Revision: https://reviews.llvm.org/D125772
The file was modifiedllvm/test/tools/llvm-ar/mri1.test
Commit 8430b827419534cbd0c6ade12abea1d00a033eba by fraser
[RISCV] Drop notion of "strict" vsetvli compatibility

With recent fixes to the dataflow in place, we now never pass
Strict=true to isCompatible, so remove the parameter completely.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D125748
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit ecaa4d9662c9a6ac013ac40a8ad72a2c75e3fd3b by sam.mccall
[clangd] Indexing of standard library

This provides a nice "warm start" with all headers indexed, not just
those included so far.

The standard library is indexed after a preamble is parsed, using that
file's configuration. The result is pushed into the dynamic index.
If we later see a higher language version, we reindex it.

It's configurable as Index.StandardLibrary, off by default for now.

Based on D105177 by @kuhnel

Fixes https://github.com/clangd/clangd/issues/618

Differential Revision: https://reviews.llvm.org/D115232
The file was addedclang-tools-extra/clangd/index/StdLib.h
The file was addedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was addedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
Commit c8cb644185f5459016a506a4d19a92b85b6b87c5 by llvmgnsyncbot
[gn build] Port ecaa4d9662c9
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 5b00d13c00712de5161935d3d6b7af55cb8f3eb5 by flo
[LV] Fetch vector loop region once and remember it (NFC).

This avoids an unnecessary lookup and makes the code slightly more
compact.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit f7709a059ac0ef1edaa2dc83321a4d972933e975 by fraser
[RISCV] Add a test showing incorrect RVV stack alignment

The RISC-V stack is assumed to be aligned to 16 bytes and can handle stack
realignment for larger objects, but the "RVV stack" is only ensured to be
aligned to 8 bytes. This means that objects specified at a larger alignment may
be misaligned, not only for 16-byte-aligned RVV objects that don't trigger
realignment, but also for 32-byte-and-larger-aligned objects which do.

The new test checks a variety of alignment configurations, showing the
misaligned cases.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D110933
The file was addedllvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
Commit f31d39c42c0e17ff9b9f65cae797ba5d66e78ec7 by spatel
[InstCombine] remove cast-of-signbit to shift transform

The transform was wrong in 3 ways:

1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
this and the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.

This is a reduced try of 3794cc0e9964 - that was reverted because
it could cause infinite loops by conflicting with the related
transforms in this block that create shifts.
The file was modifiedllvm/test/Transforms/PhaseOrdering/cmp-logic.ll
The file was modifiedllvm/test/Transforms/InstCombine/compare-signs.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit 76ddbb1ca747366417be64fdf79218df099a5973 by sam.mccall
Revert "[clangd] Indexing of standard library"

This reverts commit ecaa4d9662c9a6ac013ac40a8ad72a2c75e3fd3b.
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was removedclang-tools-extra/clangd/index/StdLib.h
The file was removedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was removedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/Config.h
Commit f032690a7c0b221b27bfb79ffec85147f23d520f by llvmgnsyncbot
[gn build] Port 76ddbb1ca747
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
Commit 7afd257ff8a45a348767b4432abc6f4f105fc376 by jingham
Fix the std::string formatter to report errors in the case where the
string points to unaccessible memory.

The formatter tries to get the data field of the std::string, and to
check whether that fails it just checks that the ValueObjectSP
returned is not empty. But we never return empty ValueObjectSP's to
indicate failure, since doing so would lose the Error object that
tells you why fetching the ValueObject failed.

This patch adds a check for ValueObject::GetError().Success().

I also added a test case for this failure, and reworked the test case
a bit (to use run_to_source_breakpoint). I also renamed a couple of
single letter locals which don't follow the lldb coding conventions.

Differential Revision: https://reviews.llvm.org/D108228
The file was modifiedlldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string/TestDataFormatterLibcxxString.py
The file was modifiedlldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
The file was modifiedlldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string/main.cpp
Commit d2be4f95494e642b72852cc33e69a47016fe4a23 by aeubanks
[OpaquePtr][LLParser] Explicitly turn off opaque pointers if we see a star

If we turn on --opaque-pointers, tests with '*' would use opaque pointers.

Can't really test this without flipping the default value for --opaque-pointers.

Reviewed By: #opaque-pointers, nikic

Differential Revision: https://reviews.llvm.org/D125735
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
Commit 470910c4ad8af2555c49aec16409630d2a3246b6 by aeubanks
[OpaquePtr][BitcodeReader] Explicitly turn off opaque pointers if we see a typed pointer

Followup to D125735 on the bitcode reader side.

Reviewed By: #opaque-pointers, nikic

Differential Revision: https://reviews.llvm.org/D125736
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
Commit 627928c58bd4f06fff394e8c2e595791f35b17ed by keithbsmiley
Revert "[llvm-objcopy][test] Add cmp after copy"

This reverts commit 0d863b5b90a2f11e58b0b54d7183cb1577fd3a0b.

Broke a test https://reviews.llvm.org/D125478#3519509
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/universal-object.test
Commit be738c9d1c1612f5cb0a84227f5ced2726ae609e by walter erquinigo
[lldb-vscode] Fix data race in lldb-vscode when running with ThreadSanitizer

This patch fixes https://github.com/llvm/llvm-project/issues/54768. A ProgressEventReporter creates a dedicated thread that keeps checking whether there are new events that need to be sent to IDE as long as m_thread_should_exit is true. When the VSCode instance is destructed, it will set m_thread_should_exit to false, which caused a data race because at the same time its ProgressEventReporter is reading this value to determine whether it should quit. This fix simply uses mutex to ensure they cannot read and write this value at the same time.

Committed on behalf of PRESIDENT810

Reviewed By: clayborg, wallace

Differential Revision: https://reviews.llvm.org/D125073
The file was modifiedlldb/tools/lldb-vscode/ProgressEvent.h
Commit d8f4f1027a92883067ecd4b01030484cffeb24d3 by walter erquinigo
[llvm][json] Fix UINT64 json parsing

https://reviews.llvm.org/D109347 added support for UINT64 json numeric
types. However, it seems that it didn't properly test uint64_t numbers
larger than the int64_t because the number parsing logic doesn't
have any special handling for these large numbers.

This diffs adds a handler for large numbers, and besides that, fixes the
parsing of signed types by checking for errno ERANGE, which is the
recommended way to check if parsing fails because of out of bounds
errors. Before this diff, strtoll was always returning a number within
the bounds of an int64_t and the bounds check it was doing was completely
superfluous.

As an interesting fact about the old implementation, when calling strtoll
with "18446744073709551615", the largest uint64_t, End was S.end(), even
though it didn't use all digits. Which means that this check can only be
used to identify if the numeric string is malformed or not.

This patch also adds additional tests for extreme cases.

Differential Revision: https://reviews.llvm.org/D125322
The file was modifiedllvm/lib/Support/JSON.cpp
The file was modifiedllvm/unittests/Support/JSONTest.cpp
Commit f84741d8bf3b382dba8c37bb9bff1f5c5576af15 by jay.foad
[AMDGPU] Add a MIR test for D125567
The file was addedllvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
Commit 366e57de23ed20ac95201e1623dfffed215e98f8 by pzheng
[clang-cl] Add /Zc:wchar_t- option

Map /Zc:wchar_t- to the cc1 flag -fno-wchar which is already supported.

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D125513
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/test/Driver/cl-zc.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit d92cec4c96eb85096cc64643764e1370fc08eafc by flo
[LV] Regenerate check lines for some tests.

Make sure the auto-generated check lines are up-to-date for some files,
to reduce the test diff in upcoming changes
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
Commit bd93df937a6441db4aff67191ca0bb486554c34b by llvm-project
[Polly] Mark classes as final by default. NFC.

This make is obivious that a class was not intended to be derived from.

NPM analysis pass can unfortunately not marked as final because they are
derived from a llvm::Checker<T> template internally by the NPM.

Also normalize the use of classes/structs
* NPM passes are structs
* Legacy passes are classes
* structs that have methods and are not a visitor pattern are classes
* structs have public inheritance by default, remove "public" keyword
* Use typedef'ed type instead of inline forward declaration
The file was modifiedpolly/lib/Support/ScopHelper.cpp
The file was modifiedpolly/lib/Analysis/ScopGraphPrinter.cpp
The file was modifiedpolly/include/polly/DeadCodeElimination.h
The file was modifiedpolly/include/polly/ScopDetectionDiagnostic.h
The file was modifiedpolly/include/polly/MatmulOptimizer.h
The file was modifiedpolly/include/polly/CodeGen/IRBuilder.h
The file was modifiedpolly/lib/Transform/ScopInliner.cpp
The file was modifiedpolly/include/polly/ScheduleTreeTransform.h
The file was modifiedpolly/lib/Transform/Simplify.cpp
The file was modifiedpolly/include/polly/Support/DumpFunctionPass.h
The file was modifiedpolly/include/polly/ManualOptimizer.h
The file was modifiedpolly/lib/Analysis/ScopDetection.cpp
The file was modifiedpolly/lib/CodeGen/PPCGCodeGeneration.cpp
The file was modifiedpolly/include/polly/CodeGen/IslExprBuilder.h
The file was modifiedpolly/lib/Analysis/PruneUnprofitable.cpp
The file was modifiedpolly/lib/Support/RegisterPasses.cpp
The file was modifiedpolly/lib/Transform/ScheduleOptimizer.cpp
The file was modifiedpolly/include/polly/CodeGen/LoopGeneratorsGOMP.h
The file was modifiedpolly/lib/Exchange/JSONExporter.cpp
The file was modifiedpolly/lib/Transform/ManualOptimizer.cpp
The file was modifiedpolly/lib/Transform/ScheduleTreeTransform.cpp
The file was modifiedpolly/include/polly/Support/SCEVAffinator.h
The file was modifiedpolly/include/polly/Support/VirtualInstruction.h
The file was modifiedpolly/include/polly/Simplify.h
The file was modifiedpolly/lib/CodeGen/IslAst.cpp
The file was modifiedpolly/lib/Transform/Canonicalization.cpp
The file was modifiedpolly/lib/Transform/MatmulOptimizer.cpp
The file was modifiedpolly/lib/Support/DumpFunctionPass.cpp
The file was modifiedpolly/include/polly/Support/GICHelper.h
The file was modifiedpolly/include/polly/Support/ISLTools.h
The file was modifiedpolly/lib/Analysis/PolyhedralInfo.cpp
The file was modifiedpolly/lib/Transform/FlattenSchedule.cpp
The file was modifiedpolly/include/polly/Support/ScopHelper.h
The file was modifiedpolly/include/polly/ForwardOpTree.h
The file was modifiedpolly/lib/Analysis/ScopInfo.cpp
The file was modifiedpolly/include/polly/DependenceInfo.h
The file was modifiedpolly/include/polly/CodeGen/CodeGeneration.h
The file was modifiedpolly/include/polly/ScopPass.h
The file was modifiedpolly/lib/Analysis/DependenceInfo.cpp
The file was modifiedpolly/lib/CodeGen/IslNodeBuilder.cpp
The file was modifiedllvm/include/llvm/Analysis/DOTGraphTraitsPass.h
The file was modifiedpolly/lib/Transform/CodePreparation.cpp
The file was modifiedpolly/include/polly/DeLICM.h
The file was modifiedpolly/lib/Transform/ForwardOpTree.cpp
The file was modifiedpolly/include/polly/PruneUnprofitable.h
The file was modifiedpolly/include/polly/CodeGen/LoopGeneratorsKMP.h
The file was modifiedpolly/include/polly/CodeGen/BlockGenerators.h
The file was modifiedpolly/include/polly/Support/DumpModulePass.h
The file was modifiedpolly/include/polly/CodeGen/PerfMonitor.h
The file was modifiedpolly/include/polly/JSONExporter.h
The file was modifiedpolly/include/polly/PolyhedralInfo.h
The file was modifiedpolly/lib/Support/SCEVValidator.cpp
The file was modifiedpolly/lib/Transform/MaximalStaticExpansion.cpp
The file was modifiedpolly/lib/CodeGen/ManagedMemoryRewrite.cpp
The file was modifiedpolly/lib/CodeGen/CodegenCleanup.cpp
The file was modifiedpolly/lib/Transform/DeadCodeElimination.cpp
The file was modifiedpolly/lib/Transform/DeLICM.cpp
The file was modifiedpolly/include/polly/ScopInfo.h
The file was modifiedpolly/include/polly/CodeGen/IslAst.h
The file was modifiedpolly/lib/Support/DumpModulePass.cpp
The file was modifiedpolly/include/polly/CodePreparation.h
The file was modifiedpolly/include/polly/ScopBuilder.h
The file was modifiedpolly/include/polly/ScopGraphPrinter.h
The file was modifiedpolly/include/polly/ScopDetection.h
The file was modifiedpolly/lib/CodeGen/CodeGeneration.cpp
The file was modifiedpolly/include/polly/ScheduleOptimizer.h
Commit 4c6a070a2ce1722f53da8164b6d50d5d54fdc1d2 by david.green
[AArch64] Teach perfect shuffles tables about D-lane movs

Similar to D123386, this adds D-Movs to the AArch64 perfect shuffle
tables, slightly lowering the costs a little more. This is a rough
improvement in general, especially if you ignore mov v0.16b, v2.16b type
moves that are often artefacts of the calling convention.

The D register movs are encoded as (0x4 | LaneIdx), and to generate a D
register move we are required to bitcast into a higher type, but it is
otherwise very similar to the S-lane mov's already supported.

Differential Revision: https://reviews.llvm.org/D125477
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/reduce-shuffle.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64PerfectShuffle.h
The file was modifiedllvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
The file was modifiedllvm/utils/PerfectShuffle/PerfectShuffle.cpp
The file was modifiedllvm/test/CodeGen/AArch64/shuffle-tbl34.ll
The file was modifiedllvm/test/CodeGen/AArch64/shuffles.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedclang/test/CodeGen/aarch64-neon-vcmla.c
The file was modifiedllvm/test/CodeGen/AArch64/arm64-dup.ll
Commit e1cf702a02bc35b934cc2f8ada2a2bf12e74888f by hanruobing
fix typo error in DivergenceAnalysis.h

Fix a typo error in the comment in DivergenceAnalysis.h

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D125808
The file was modifiedllvm/include/llvm/Analysis/DivergenceAnalysis.h
Commit 0b168a49bf584ddd9aae4be8b1907aee8ed65615 by minyihh
[mlir][LLVMIR] Use a new way to verify GEPOp indices

Previously, GEPOp relies on `findKnownStructIndices` to check if a GEP
index should be static. The truth is, `findKnownStructIndices` can only
tell you a GEP index _might_ be indexing into a struct (which should use
a static GEP index). But GEPOp::build and GEPOp::verify are falsely
taking this information as a certain answer, which creates many false
alarms like the one depicted in
`test/Target/LLVMIR/Import/dynamic-gep-index.ll`.

The solution presented here adopts a new verification scheme: When we're
recursively checking the child element types of a struct type, instead
of checking every child types, we only check the one dictated by the
(static) GEP index value. We also combine "refinement" logics --
refine/promote struct index mlir::Value into constants -- into the very
verification process since they have lots of logics in common. The
resulting code is more concise and less brittle.

We also hide GEPOp::findKnownStructIndices since most of the
aforementioned logics are already encapsulated within GEPOp::build and
GEPOp::verify, we found little reason for findKnownStructIndices (or the
new findStructIndices) to be public.

Differential Revision: https://reviews.llvm.org/D124935
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was addedmlir/test/Target/LLVMIR/Import/dynamic-gep-index.ll
The file was addedmlir/test/Dialect/LLVMIR/dynamic-gep-index.mlir
Commit 791ec1c68e3bbf017ace434a162e61806fc03b47 by Stanislav.Mekhanoshin
[AMDGPU] Add intrinsics llvm.amdgcn.{raw|struct}.buffer.load.lds

Differential Revision: https://reviews.llvm.org/D124884
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
Commit 320545b577777f12df5f6d562bad0e6df0d52861 by llvm-dev
[X86] Rename combineCONCAT_VECTORS\INSERT_SUBVECTOR\EXTRACT_SUBVECTOR to match Opcode name. NFCI.

Its a lot easier to quickly search for the combine when it actually contains the name of the opcode it combines.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2e2f3e33dff4917df055b7dba2860a64f8060db2 by Stanislav.Mekhanoshin
[AMDGPU] Add test for no waitcnt before issuing LDS DMA. NFC.

A wait is only needed after the DMA before LDS can be read.
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
Commit d21b9b4946cd4e5f784077691e273ee6acc92d3e by Joseph.Nash
[AMDGPU] gfx11 scalar alu instructions

MC layer support for SOP(scalar alu operations) including encoding
support for s_delay_alu and s_sendmsg_rtn.

Contributors:
Jay Foad <jay.foad@amd.com>

Patch 7/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125319

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125498
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/test/MC/AMDGPU/sopk.s
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was addedllvm/test/MC/AMDGPU/gfx11_err.s
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_scalar.s
The file was modifiedllvm/test/MC/AMDGPU/sopp-err.s
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
The file was addedllvm/test/MC/AMDGPU/sopp-gfx11.s
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/test/MC/AMDGPU/sopk-err.s
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was addedllvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit 26d83a431ecbc79d227b0f3b92b0fb2166a7c7d7 by walter erquinigo
[NFC][lldb][trace] Use uint64_t when decoding and enconding json

llvm's json parser supports uint64_t, so let's better use it for the
packets being sent between lldb and lldb-server instead of using int64_t
as an intermediate type, which might be error-prone.
The file was modifiedlldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
The file was modifiedlldb/include/lldb/Utility/TraceIntelPTGDBRemotePackets.h
The file was modifiedlldb/source/Utility/TraceGDBRemotePackets.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.cpp
The file was modifiedlldb/source/Target/Trace.cpp
The file was modifiedlldb/include/lldb/Utility/TraceGDBRemotePackets.h
The file was modifiedlldb/source/Utility/TraceIntelPTGDBRemotePackets.cpp
Commit 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea by preames
[RISCV] Enable strict assertions in InsertVSETVLI data flow

These asserts are believed to hold after several recent miscompiles have been fixed.  If you see an assertion failure on this change, please toggle the default back and make sure you file a bug with a reproducer.  We may have as yet uncaught miscompiles lurking in this code.

Differential Revision: https://reviews.llvm.org/D125271
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 127a1492d72902e2b2cd8905c1198743761f52fb by sam.mccall
[clangd] Add command-line flag to set background indexing thread priority.

This is a followup to D124715, which changed the default, and it anticipates
future patches raising the priority of Low (which is currently equal to
Background on Windows & Linux).
The main point is to allow users to restore the old behavior, which e.g.
allows efficiency cores to remain idle.

I did consider making this a config setting, this is a more complicated change:
- needs to touch queue priorities as well as thread priorities
- we don't know the priority until evaluating the config inside the task
- users would want the ability to prioritize background indexing tasks relative
   to each other without necessarily affecting thread priority, so using one
   option for both may be confusing
I don't really have a use case, so I prefer the simpler thing.

Differential Revision: https://reviews.llvm.org/D125673
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/index/Background.cpp
The file was modifiedclang-tools-extra/clangd/index/Background.h
Commit 5c3b20520b5716d61833c8ce45d19faa48ce8db7 by jeffniu22
[mlir] Update LLVMIR Fastmath flags use of MLIR BitEnum functionality

This diff updates the LLVMIR dialect Fastmath flags attribute to use recently
added features of `BitEnum` attributes. Specifically, this diff uses the bit
enum "group" case to represent the `fast` value as an alias for a combination
of other values (`ninf`, `nnan`, ...), instead of using a separate integer
value. (This is in line with LLVM's fastmath flags representation.) This diff
also leverages the `printBitEnumPrimaryGroups` `tblgen` field for concise
enum printing.

The `BitEnum` features were developed for an upcoming diff that adds `fastmath`
support to the arithmetic dialect. This diff simply applies some of the relevant
new features to the LLVM dialect attribute.

Reviewed By: ftynse, Mogball

Differential Revision: https://reviews.llvm.org/D124720
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
The file was modifiedmlir/test/IR/attribute.mlir
The file was modifiedmlir/tools/mlir-tblgen/EnumsGen.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/include/mlir/IR/EnumAttr.td
The file was modifiedmlir/unittests/TableGen/enums.td
The file was modifiedmlir/test/Dialect/LLVMIR/roundtrip.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/unittests/TableGen/EnumsGenTest.cpp
Commit e8e00e342c4fadc8355d1dfb8de86fb0a3dcd5f7 by sam.mccall
[pseudo] benchmark cleanups. NFC

- add missing benchmark for lex/preprocess steps
- name benchmarks after the function they're benchmarking, when appropriate
- remove unergonomic "run" prefixes from benchmark names
- give a useful error message if --grammar or --source are missing
- Use realistic example of how to run, run all benchmarks by default.
  (for someone who doesn't know the commands, this is the most useful action)
- Improve typos/wording in comment
- clean up unused vars
- avoid "parseable stream" name, which isn't a great name & not one I expected
  to escape from ClangPseudoMain

Differential Revision: https://reviews.llvm.org/D125312
The file was modifiedclang-tools-extra/pseudo/benchmarks/Benchmark.cpp
Commit dbf3b5f114553e4d5a446cd9ef57e98a8d04354e by spatel
[InstCombine] fold more shuffles with FP<->Int cast operands

shuffle (cast X), (cast Y), Mask --> cast (shuffle X, Y, Mask)

This extends the transform added with 0353c2c996c5.

If the casts are to a larger element type, the transform
reduces shuffle bit width, so that should be a win for
most codegen (if not, it can be inverted).
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit ff6fe39eca705186fab1f06376cc4b648ff9711b by michaelrj
[libc] add sprintf

This adds the sprintf entrypoint, as well as unit tests. Currently
sprintf only supports %%, %s, and %c, but the other conversions are on
the way.

Reviewed By: sivachandra, lntue

Differential Revision: https://reviews.llvm.org/D125573
The file was modifiedlibc/test/src/stdio/CMakeLists.txt
The file was modifiedlibc/src/stdio/printf_core/string_converter.h
The file was addedlibc/src/stdio/sprintf.cpp
The file was modifiedlibc/spec/stdc.td
The file was modifiedlibc/src/stdio/printf_core/converter.cpp
The file was modifiedlibc/test/src/stdio/printf_core/parser_test.cpp
The file was modifiedlibc/src/stdio/CMakeLists.txt
The file was modifiedlibc/src/stdio/printf_core/converter.h
The file was modifiedlibc/src/stdio/printf_core/char_converter.h
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was modifiedlibc/src/stdio/printf_core/CMakeLists.txt
The file was modifiedlibc/src/stdio/printf_core/printf_main.h
The file was addedlibc/src/stdio/sprintf.h
The file was addedlibc/test/src/stdio/sprintf_test.cpp
Commit 11a7e77c95ddcb51779d9e9d804222eb45a1da92 by preames
[RISCV] Canonicalize AVL=setvli to AVL=Imm or AVL=VLMAX

This patch adds a transform to the local prepass in InsertVSETVLI which canonicalizes an AVL of a register from another vsetvli into immediate or VLMAX when VTYPE is the same. In this patch, I chose to be conservative and avoid arbitrary vreg forwarding due to profitability concerns about possibility overlapping live ranges.

This has the effect of eliminating vsetvli instructions in loops which are walking either VLMAX or a constant number of lanes per iteration.

Differential Revision: https://reviews.llvm.org/D125812
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 854c273cbb7ec6745dc63cfe1951b51e9092e8ee by li.zhe.hua
[clang][dataflow] Weaken guard to only check for storage location

Weaken the guard for whether a sub-expression has been evaluated to
only check for the storage location, instead of checking for the
value. It should be sufficient to check for the storage location, as
we don't necessarily guarantee that a value will be set for the
location (although this is currently true right now).

Differential Revision: https://reviews.llvm.org/D125823
The file was modifiedclang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp
Commit ccdb56ac10eef3048135169a67d239328c2b1de6 by sam.mccall
Reland "[clangd] Indexing of standard library"

This reverts commit 76ddbb1ca747366417be64fdf79218df099a5973.
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was addedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was addedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was addedclang-tools-extra/clangd/index/StdLib.h
Commit 118c5d1c97b4191678663bf2a938eee7dec6f0b1 by preames
[RISCV] Minor reorganization of VSETVLIInfo::operator== for readability [NFC]
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit d910508a65a6f523197665dd27abc05f5285ad70 by llvmgnsyncbot
[gn build] Port ccdb56ac10ee
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit a09af8669396aebe280d959af695dc68307217cd by Stanislav.Mekhanoshin
[AMDGPU] Enable FLAT LDS DMA on gfx9/10 before gfx940

We always had global and scratch loads to LDS in the gfx9,
but did not handle it. These were available via the 'lds'
encoding bit. In gfx940 this bit was reused as 'svs' which
resulted in new '_lds' opcodes effectively pushing this
bit into the opcode, but functionally it is the same. These
instructions are also available on gfx10.

Differential Revision: https://reviews.llvm.org/D125126
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx8_unsupported.s
The file was modifiedllvm/test/MC/AMDGPU/gfx9-asm-err.s
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx1030_new.s
The file was modifiedllvm/test/MC/AMDGPU/gfx9_asm_flat.s
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_flat.s
The file was modifiedllvm/test/MC/AMDGPU/gfx90a_err.s
The file was modifiedllvm/test/MC/AMDGPU/gfx940_err.s
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Commit 6aabf60f2fb7589430c0ecc8fe95913c973fa248 by sam.mccall
Revert "Reland "[clangd] Indexing of standard library""

This reverts commit ccdb56ac10eef3048135169a67d239328c2b1de6.

Still seeing windows failures on GN bots: http://45.33.8.238/win/58316/step_9.txt

Unfortunately I can't debug these at all - it's a bare unsymbolized
stacktrace, and I can't reproduce the failure.
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was removedclang-tools-extra/clangd/index/StdLib.h
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was removedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was removedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/Config.h
Commit dee3190293fef40d08105936295a26f25d86755a by Stanislav.Mekhanoshin
[AMDGPU] Add llvm.amdgcn.global.load.lds intrinsic

Differential Revision: https://reviews.llvm.org/D125279
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
Commit 8d53f2fc0d9f7cf428905524fe85c459f755741c by llvmgnsyncbot
[gn build] Port 6aabf60f2fb7
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
Commit 1f49714d3e19502753fcea7ad8378a194222328f by walter erquinigo
[trace][intelpt] Support system-wide tracing [4] - Support per core tracing on lldb-server

This diffs implements per-core tracing on lldb-server. It also includes tests that ensure that tracing can be initiated from the client and that the jLLDBGetState ppacket returns the list of trace buffers per core.

This doesn't include any decoder changes.

Finally, this makes some little changes here and there improving the existing code.

A specific piece of code that can't reliably be tested is when tracing
per core fails due to permissions. In this case we add a
troubleshooting message and this is the manual test:

```
/proc/sys/kernel/perf_event_paranoid set to 1

(lldb) process trace start --per-core-tracing                                         error: perf event syscall failed: Permission denied
You might need that /proc/sys/kernel/perf_event_paranoid has a value of 0 or -1.
``

Differential Revision: https://reviews.llvm.org/D124858
The file was addedlldb/source/Plugins/Process/Linux/IntelPTMultiCoreTrace.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Perf.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Perf.cpp
The file was modifiedlldb/docs/lldb-gdb-remote.txt
The file was modifiedlldb/source/Plugins/Trace/intel-pt/TraceIntelPT.cpp
The file was modifiedlldb/source/Target/Trace.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Procfs.cpp
The file was modifiedlldb/include/lldb/Utility/TraceIntelPTGDBRemotePackets.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTSingleBufferTrace.cpp
The file was modifiedlldb/source/Plugins/Trace/intel-pt/TraceIntelPTOptions.td
The file was modifiedlldb/include/lldb/lldb-types.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTSingleBufferTrace.h
The file was modifiedlldb/source/Plugins/Process/Linux/CMakeLists.txt
The file was modifiedlldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
The file was modifiedlldb/include/lldb/Utility/TraceGDBRemotePackets.h
The file was modifiedlldb/unittests/Process/Linux/ProcfsTests.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Procfs.h
The file was modifiedlldb/test/API/commands/trace/multiple-threads/TestTraceStartStopMultipleThreads.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/intelpt/intelpt_testcase.py
The file was modifiedlldb/source/Utility/TraceIntelPTGDBRemotePackets.cpp
The file was addedlldb/source/Plugins/Process/Linux/IntelPTMultiCoreTrace.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.h
The file was modifiedlldb/source/Utility/TraceGDBRemotePackets.cpp
Commit 1637545f689b8c4ef888ca385de75982a6a932e3 by walter erquinigo
[trace][intelpt] Support system-wide tracing [5] - Disable/enable per-core tracing based on the process state

When tracing on per-core mode, we are tracing all processes, which means
that after hitting a breakpoint, our process will stop running (thus
producing no more tracing data) but other processes will continue
writing to our trace buffers. This causes a big data loss for our trace.
As a way to remediate this, I'm adding some logic to pause and unpause
tracing based on the target's state. The earlier we do it the better,
however, I'm not adding the trigger at the earliest possible point for
simplicity of this diff. Later we can improve that part.

Differential Revision: https://reviews.llvm.org/D124962
The file was modifiedlldb/include/lldb/Host/common/NativeProcessProtocol.h
The file was modifiedlldb/source/Host/common/NativeProcessProtocol.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTSingleBufferTrace.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Perf.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTMultiCoreTrace.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/Perf.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTMultiCoreTrace.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeProcessLinux.h
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTSingleBufferTrace.h
Commit 1188faa7ab4b005e3ee28f30055de2f76e210eb8 by walter erquinigo
[trace][intelpt] Support system-wide tracing [6] - Break IntelPTCollector into smaller files and minor refactor

IntelPTCollector is very big and has 3 classes in it. It's actually cleaner if each one has its own file. This also gives more visibility to the developer about the different kinds of "tracers" that we have.

Besides that, I'm now restricting the creation of the BinaryData chunks to GetState() instead of having it in different places, which is not very clean, because the gdb-remote protocol should be as restricted as possible.

Differential Revision: https://reviews.llvm.org/D125047
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/CMakeLists.txt
The file was modifiedlldb/source/Plugins/Process/Linux/IntelPTCollector.h
The file was addedlldb/source/Plugins/Process/Linux/IntelPTThreadTraceCollection.h
The file was addedlldb/source/Plugins/Process/Linux/IntelPTPerThreadProcessTrace.h
The file was modifiedlldb/include/lldb/Utility/TraceGDBRemotePackets.h
The file was addedlldb/source/Plugins/Process/Linux/IntelPTPerThreadProcessTrace.cpp
The file was addedlldb/source/Plugins/Process/Linux/IntelPTThreadTraceCollection.cpp
Commit 6f803caa6dea44aa861113cc1e6dcfba1564541b by llvmgnsyncbot
[gn build] Port 1188faa7ab4b
The file was modifiedllvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
Commit 6947945080081a23f7cd63203263b31d987f82f0 by llvmgnsyncbot
[gn build] Port 1f49714d3e19
The file was modifiedllvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
Commit 5bbef2e3fff123293ed9c2037e2662e352bf37af by li.zhe.hua
[clang][dataflow] Fix double visitation of nested logical operators

Sub-expressions that are logical operators are not spelled out
separately in basic blocks, so we need to manually visit them when we
encounter them. We do this in both the `TerminatorVisitor`
(conditionally) and the `TransferVisitor` (unconditionally), which can
cause cause an expression to be visited twice when the binary
operators are nested 2+ times.

This changes the visit in `TransferVisitor` to check if it has been
evaluated before trying to visit the sub-expression.

Differential Revision: https://reviews.llvm.org/D125821
The file was modifiedclang/unittests/Analysis/FlowSensitive/TransferTest.cpp
The file was modifiedclang/lib/Analysis/FlowSensitive/Transfer.cpp
Commit 9f1d905f39ac7f32b1965b8062c0803955ccbd0f by michaelrj
[libc] add snprintf

After adding sprintf, snprintf is simple. The functions are very
similar. The tests only cover the behavior of the max length since the
sprintf tests should cover the other behavior.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D125826
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was modifiedlibc/spec/stdc.td
The file was modifiedlibc/src/stdio/sprintf.cpp
The file was modifiedlibc/test/src/stdio/CMakeLists.txt
The file was addedlibc/src/stdio/snprintf.cpp
The file was modifiedlibc/src/stdio/CMakeLists.txt
The file was addedlibc/src/stdio/snprintf.h
The file was addedlibc/test/src/stdio/snprintf_test.cpp
Commit 5a8e755101320955b4a86b034dec6e30bcc2b9f4 by github
[docs][LangRef] Fix typo in llvm.smul.fix example
The file was modifiedllvm/docs/LangRef.rst
Commit a5983e57af0954394f74fe4ad6ab0c076837f558 by preames
[RISCV] Add additional test coverage of 11a7e77c and related transforms
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Commit a7b69dbdd10fd8a022bf68b00e6d094fb5b0b9c2 by aaupov
[BOLT][NFC] Move BinaryDominatorTree out of BinaryLoop header

Split up the BinaryLoop header and move BinaryDominatorTree into its own header,
preparing it for a standalone use.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D125664
The file was modifiedbolt/lib/Core/BinaryFunction.cpp
The file was modifiedbolt/include/bolt/Core/BinaryLoop.h
The file was addedbolt/include/bolt/Core/BinaryDomTree.h
Commit c907d6e0e9fd8fafd49e4d0f9e584f58bbac5ead by aaupov
[BOLT][NFC] Suppress unused variable warnings

Addresses the warnings emitted by Apple Clang 13.1.6 (Xcode 13.3.1).
Tip @tschuett issue #55404.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D125733
The file was modifiedbolt/lib/Rewrite/RewriteInstance.cpp
The file was modifiedbolt/lib/Core/BinaryContext.cpp
The file was modifiedbolt/lib/Core/BinaryBasicBlock.cpp
Commit 0f4d9f9b71be8a95cd24534bf914fc9a6fb0ff30 by ashaposhnikov
[ConstantRange] Improve the implementation of binaryAnd

This diff adjusts binaryAnd to take advantage of the analysis
based on KnownBits.

Differential revision: https://reviews.llvm.org/D125603

Test plan:
1/ ninja check-llvm
2/ ninja check-llvm-unit
The file was modifiedllvm/test/Transforms/SCCP/range-and.ll
The file was modifiedllvm/lib/IR/ConstantRange.cpp
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
Commit 79ca4ed3e782e505e8964a3c968de5fd4f09ca7a by sam.mccall
[pseudo] Design notes from discussion today. NFC
The file was addedclang-tools-extra/pseudo/DesignNotes.md
Commit 996834e6813ab5481a58e42e7a11f57d243a3a99 by springerm
[mlir][SCF] Fix scf.while bufferization

Before this fix, the bufferization implementation made the incorrect assumption that the values yielded from the "before" region must match with the values yielded from the "after" region.

Differential Revision: https://reviews.llvm.org/D125835
The file was modifiedmlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
The file was modifiedmlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
The file was modifiedmlir/test/Dialect/SCF/one-shot-bufferize.mlir
The file was modifiedmlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
The file was modifiedmlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
Commit d4545e6fa0366718c2416d3578dd4e1f26855c29 by preames
Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow"

This reverts commit 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea.

The stronger asserts served their purpose; I stumbled across another bug.  Will reapply once this one is also fixed.

The bug appears to be a variant of a previous one:
* We mutate an instruction in one block.
* That mutation changes the phase3 results of another block.

This is very similiar to a previous issue, except cross block instead of within a single block.
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 9294a1e9a8ab8fed60ee1b0737e944077b5339cd by suderman
[mlir][tosa] Rework tosa.apply_scale lowering for 32-bit

Added handling rounding behavior in 32-bits for when possible. This
avoids kernel compilation generating scalarized code on platforms where
64-bit vectors are not available.

As the 48-bit lowering requires 64-bit anyway, we added a full 64-bit
solution simplifying the old path.

Reviewed By: dcaballe, mravishankar

Differential Revision: https://reviews.llvm.org/D125583
The file was modifiedmlir/include/mlir/Conversion/TosaToArith/TosaToArith.h
The file was modifiedmlir/lib/Conversion/TosaToArith/TosaToArith.cpp
The file was modifiedmlir/test/Conversion/TosaToArith/tosa-to-arith.mlir
The file was modifiedmlir/lib/Conversion/TosaToArith/TosaToArithPass.cpp
The file was modifiedmlir/include/mlir/Conversion/Passes.td
Commit 8527f32f0a16a77edb0b53a5ab8074e518eeff54 by ben.shi
[lld][ELF] Support BFD name elf32-avr

Reviewed By: MaskRay

differential Revision: https://reviews.llvm.org/D125544
The file was modifiedlld/ELF/ScriptParser.cpp
The file was addedlld/test/ELF/linkerscript/avr5.test
Commit 85fb9ccfa387f78eb77bdfdfd5f0d18d43bcebeb by aqjune
Precommit a test file for D84941
The file was addedllvm/test/Transforms/JumpThreading/freeze-impliescond.ll
Commit 3adcf96b4faa06ff6d82a8bdf92d2a3f4917c433 by aqjune
[JumpThreading] Let ProcessImpliedCondition look into freeze instructions

This patch makes JumpThreading's ProcessImpliedCondition deal with frozen
conditions.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D84941
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
The file was modifiedllvm/test/Transforms/JumpThreading/freeze-impliescond.ll
Commit d5c7d4b5224b6fbdfd35b9a81bb0ca80a35189b6 by Chenbing.Zheng
[InstCombine] add tests for icmp-fsh
The file was modifiedllvm/test/Transforms/InstCombine/icmp-fsh.ll
Commit 25af3afa676191b2af328b6f03ee869d82a97f58 by sunshaoce
[NFC][AMDGPU][CodeGen] Use ArrayRef in TargetLowering functions

Based on D123467.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D124508
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Commit dca37af061fbe6590399dfb4e3fd3dda16d63144 by zixuan.wu
[NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

CSKY is always in 4-byte align, no matter it's long long type.
For global aggregate variable, it's 4-byte align if its size is bigger than or equal to 4 bytes.

Differential Revision: https://reviews.llvm.org/D124977
The file was modifiedclang/test/CodeGen/c-strings.c
The file was modifiedclang/test/Sema/builtin-alloca-with-align.c
Commit 9b1e00738c5ddba681e17e5cb7c260d9afc4c3a7 by preames
[BasicAA] Remove unneeded special case for malloc/calloc

This code pre-exists the generic handling for inaccessiblememonly.  If we remove it and update one test with inaccessiblememonly, nothing else changes.  Note that simply running O1 on that test would annotate malloc with the missing inaccessiblememonly.
The file was modifiedllvm/test/Transforms/GVN/nonescaping-malloc.ll
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
Commit 862b5a52335fef9e29013b00506e49342ac473f1 by groverkss
[MLIR][Presburger] Attach values only to non-local identifiers in FAVC

This patch changes `FlatAffineValueConstraints` to only allow attaching
values to non-local identifiers.

The reasoning for this change is:
1. Information attached to local identifiers can be lost since local identifiers
  can be removed for output size optimizations.
2. There are no current use cases for attaching values to Local identifiers.
3. Attaching a value to a local identifier does not make sense since a local
  identifier represents existential quantification.

This patch also adds some additional asserts to the affected functions.

Reviewed By: arjunp, bondhugula

Differential Revision: https://reviews.llvm.org/D125613
The file was modifiedmlir/include/mlir/Dialect/Affine/Analysis/AffineStructures.h
The file was modifiedmlir/lib/Dialect/Affine/Analysis/AffineStructures.cpp
Commit e00cbbec06c08dc616a0d52a20f678b8fbd4e304 by groverkss
[MLIR][Presburger] Cleanup getMaybeValues in FACV

This patch cleans up multiple getMaybeValue functions to take an IdKind instead
of special functions.

Reviewed By: arjunp

Differential Revision: https://reviews.llvm.org/D125617
The file was modifiedmlir/lib/Dialect/Affine/Analysis/AffineStructures.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/Analysis/AffineStructures.h
The file was modifiedmlir/lib/Dialect/SCF/Utils/AffineCanonicalizationUtils.cpp
Commit 573a5b58001d6dd86d404832b7b1c45a1b4f4c55 by marek.kurdej+llvm.org
Revert "[clang-format] Fix WhitespaceSensitiveMacros not being honoured when macro closing parenthesis is followed by a newline."

This reverts commit 50cd52d9357224cce66a9e00c9a0417c658a5655.

It provoked regressions in C++ and ObjectiveC as described in https://reviews.llvm.org/D123676#3515949.

Reproducers:
```
MACRO_BEGIN
#if A
int f();
#else
int f();
#endif
```

```
NS_SWIFT_NAME(A)
@interface B : C
@property(readonly) D value;
@end
```
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit d81064949f41b95a5a2122889f07c9ffcc875834 by samolisov
[ArgPromotion] Add unused-argument.ll test (NFC)

If a pointer argument is unused within the callee, this argument should
be removed from the function's signature while all used pointer
arguments should be promoted as it is expected. The ArgumentPromotion
pass doesn't touch unused non-pointer arguments at all.
The file was addedllvm/test/Transforms/ArgumentPromotion/unused-argument.ll
Commit 92f1028ceb30dc8e7eda3f06a8c7aa8e8082ff65 by martin
[llvm-readobj] Fix printing of Windows ARM unwind opcodes, add tests

The existing code was essentially untested; in some cases, it used
too narrow variable types to fit all the bits, in some cases the
bit manipulation operations were incorrect.

For the "ldr lr, [sp], #x" opcode, there's nothing in the documentation
that says it cannot be used in a prologue. (In practice, it would
probably seldom be used there, but technically there's nothing
stopping it from being used.) The documentation only specifies the
operation to replay for unwinding it, but the corresponding mirror
instruction to be printed for a prologue is "str lr, [sp, #-x]!".

Also improve printing of register masks, by aggregating registers
into ranges where possible, and make the printing of the terminating
branches clearer, as "bx <reg>" and "b.w <target>".

Differential Revision: https://reviews.llvm.org/D125643
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
The file was addedllvm/test/tools/llvm-readobj/COFF/arm-unwind-opcodes.s
Commit e213e5a999dbaa3c1aa97a6f81b77a3358b00b2a by riddleriver
[mlir:PDLL] Drop space as a completion commit character

This causes annoyances when attempting to use space as
a trigger character (to start a different completion).
The file was modifiedmlir/lib/Tools/mlir-pdll-lsp-server/LSPServer.cpp
Commit 6d4471efb0b94c066e5e93c99278397691869dbc by riddleriver
[mlir:PDLL] Improve the location ranges of several expressions during parsing

This allows for the range to encompass more of the source associated
with the full expression, making diagnostics easier to see/tooling easier/etc.
The file was modifiedmlir/lib/Tools/PDLL/Parser/Parser.cpp
Commit 17e2e7b7885c0afe688bcd4d6b198aab6ea8f58a by riddleriver
[mlir:PDLL] Don't append / for directory code completion

This allows for properly using / as a trigger character, i.e.
more easily allows chaining include directory completions.
The file was modifiedmlir/lib/Tools/mlir-pdll-lsp-server/PDLLServer.cpp
Commit ebad5fb309570765e8f121c441dcd90b5aa0536a by riddleriver
[mlir][Canonicalize] Fix command-line options

The canonicalize command-line options currently have no effect, as the pass is
reading the pass options in its constructor, before they're actually
initialized. This results in the default values of the options always being used.

The change here moves the initialization of the `GreedyRewriteConfig` out of the
constructor, so that it runs after the pass options have been parsed.

Fixes #55466

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125621
The file was modifiedmlir/lib/Transforms/Canonicalizer.cpp
The file was modifiedmlir/test/Transforms/test-canonicalize.mlir
Commit c4c01e4e4e388a1e3cefc9e3982ac15fb94d4f40 by npopov
[llvm-nm] Always use opaque pointers (PR55506)

Always enable opaque pointers in llvm-nm, because the tool doesn't
actually care, and this allows us to read both typed pointer and
opaque pointer bitcode files in one archive. Previously this
depended on the order inside the archive (it would work with an
opaque pointer bitcode file first, but fail with a typed pointer
bitcode file first).

Fixes https://github.com/llvm/llvm-project/issues/55506.

Differential Revision: https://reviews.llvm.org/D125751
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
The file was addedllvm/test/tools/llvm-nm/opaque-pointers.ll
Commit 323514de58aba8c073faa37335345338ae57173c by npopov
[LoopUnroll] Avoid branch on poison for runtime unroll with multiple exits

When performing runtime unrolling with multiple exits, one of the
earlier (non-latch) exits may exit the loop on the first iteration,
such that we never branch on the latch exit condition. As such, we
need to freeze the condition of the new branch that is introduced
before the loop, as it now executes unconditionally.

Differential Revision: https://reviews.llvm.org/D125754
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
Commit e9a1c82d695472820c93af40cbf3d9fde2a149c6 by npopov
[SCEVExpander] Expand umin_seq using freeze

%x umin_seq %y is currently expanded to %x == 0 ? 0 : umin(%x, %y).
This patch changes the expansion to umin(%x, freeze %y) instead
(https://alive2.llvm.org/ce/z/wujUhp).

The motivation for this change are the test cases affected by
D124910, where the freeze expansion ultimately produces better
optimization results. This is largely because
`(%x umin_seq %y) == %x` is a common expansion pattern, which
reliably optimizes in freeze representation, but only sometimes
with the zero comparison (in particular, if %x == 0 can fold to
something else, we generally won't be able to cover reasonable
code from this.)

Differential Revision: https://reviews.llvm.org/D125372
The file was modifiedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/test/Transforms/IndVarSimplify/exit-count-select.ll
Commit 7814b559bd5e1dbb3c016b393068698bc5781cc5 by riddleriver
[GreedyPatternRewriter] Avoid reversing constant order

The previous fix from af371f9f98da only applied when using a bottom-up
traversal. The change here applies the constant preprocessing logic to the
top-down case as well. This resolves the issue with the canonicalizer pass still
reordering constants, since it uses a top-down traversal by default.

Fixes #51892

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125623
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
The file was modifiedmlir/test/Dialect/Arithmetic/canonicalize.mlir
The file was modifiedmlir/test/Dialect/SCF/canonicalize.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestPatterns.cpp
The file was modifiedmlir/test/Transforms/test-operation-folder.mlir
The file was modifiedflang/test/Lower/Intrinsics/achar.f90
Commit d9d15af7873fe16d7a0dde4def30f40fa9901777 by qiucofan
[PowerPC] Treat llvm.fmuladd intrinsic as using CTR

This fixes bug 55463, similar to D78668. This is a temporary fix since
we will switch to post-isel CTR loop determination in the future.

Reviewed By: dim, shchenz

Differential Revision: https://reviews.llvm.org/D125746
The file was addedllvm/test/CodeGen/PowerPC/pr55463.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Commit 6bcafce103a4d759fd9acdc472bb2c8d0b2c859c by diana.picus
[flang][Runtime] Use proper prototypes in Fortran_main. NFCI

This is compiled as C code, so it's a good idea to be explicit about the
prototype. Clang complains about this when -Wstrict-prototypes is used.

Differential Revision: https://reviews.llvm.org/D125672
The file was modifiedflang/runtime/FortranMain/Fortran_main.c
The file was modifiedflang/include/flang/Runtime/main.h
Commit 00999fb6e14231de14db292510c854e1bf3baded by yeting.kuo
[SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes.

The patch does not pass math flags to float VPCmpIntrinsics because LLParser
could not identify float VPCmpIntrinsics as FPMathOperators.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125600
The file was addedllvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 1c0b03f6e706978f2e87408f7fd5e4c846d6c9a8 by diana.picus
[flang][driver] Support parsing response files

Add support for reading response files in the flang driver. Response
files contain command line arguments and are used whenever a command
becomes longer than the shell/environment limit. Response files are
recognized via the special "@path/to/response/file.rsp" syntax, which
distinguishes them from other file inputs.

This patch hardcodes GNU tokenization, since we don't have a CL mode for
the driver. In the future we might want to add a --rsp-quoting command
line option, like clang has, to accommodate Windows platforms.

Differential Revision: https://reviews.llvm.org/D124846
The file was addedflang/test/Driver/response-file.f90
The file was modifiedflang/tools/flang-driver/driver.cpp
Commit 7e65ffaa8bb65adc0324ccbea1fef56cab6eafe1 by thomasp
[test, x86] Fix spurious x86-target-features.c failure

x86-target-features.c can spuriously fail when checking for absence of
the string "lvi" in the compiler output due to the temporary path used
for the output file. For example:
"-o" "/tmp/lit-tmp-981j7lvi/x86-target-features-670b86.o"
will make the test fail. This commit checks specifically for lvi as a
target feature, in a similar way to the positive CHECK directive just
above.

Test Plan: fails when using -mlvi-hardening and pass otherwise

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D125084
The file was modifiedclang/test/Driver/x86-target-features.c
Commit fcfb86483b29df124c0b4a61ff65b0c6800f64b7 by flo
[LV] set Header earlier, use variable instead of repeated access (NFC).
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 25ac078a961de91522e5b5afaa6d4ffdd0dd05c4 by gabor.marton
[clang][ASTImporter] Add isNewDecl

Summary:
Add a new function with which we can query if a Decl had been newly
created during the import process. This feature is a must if we want to
have a different static analysis strategy for such newly created
declarations.

This is a dependent patch that is needed for the new CTU implementation
discribed at
https://discourse.llvm.org/t/rfc-much-faster-cross-translation-unit-ctu-analysis-implementation/61728

Differential Revision:
https://reviews.llvm.org/D123685
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/include/clang/AST/ASTImporterSharedState.h
The file was modifiedclang/unittests/AST/ASTImporterTest.cpp
Commit 56b9b97c1ef594f218eb06d2e62daa85cc238500 by gabor.marton
[clang][analyzer][ctu] Make CTU a two phase analysis

This new CTU implementation is the natural extension of the normal single TU
analysis. The approach consists of two analysis phases. During the first phase,
we do a normal single TU analysis. During this phase, if we find a foreign
function (that could be inlined from another TU) then we don’t inline that
immediately, we rather mark that to be analysed later.
When the first phase is finished then we start the second phase, the CTU phase.
In this phase, we continue the analysis from that point (exploded node)
which had been enqueued during the first phase. We gradually extend the
exploded graph of the single TU analysis with the new node that was
created by the inlining of the foreign function.

We count the number of analysis steps of the first phase and we limit the
second (ctu) phase with this number.

This new implementation makes it convenient for the users to run the
single-TU and the CTU analysis in one go, they don't need to run the two
analysis separately. Thus, we name this new implementation as "onego" CTU.

Discussion:
https://discourse.llvm.org/t/rfc-much-faster-cross-translation-unit-ctu-analysis-implementation/61728

Differential Revision: https://reviews.llvm.org/D123773
The file was modifiedclang/test/Analysis/ctu-main.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/CoreEngine.cpp
The file was modifiedclang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
The file was addedclang/test/Analysis/Inputs/ctu-onego-existingdef-other.cpp.externalDefMap.ast-dump.txt
The file was modifiedclang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
The file was modifiedclang/lib/CrossTU/CrossTranslationUnit.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngine.cpp
The file was modifiedclang/test/Analysis/ctu-on-demand-parsing.cpp
The file was modifiedclang/test/Analysis/ctu-on-demand-parsing.c
The file was addedclang/test/Analysis/Inputs/ctu-onego-small-other.cpp
The file was modifiedclang/test/Analysis/ctu-implicit.c
The file was modifiedclang/test/Analysis/ctu-main.c
The file was addedclang/test/Analysis/ctu-onego-indirect.cpp
The file was modifiedclang/include/clang/CrossTU/CrossTranslationUnit.h
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/CallEvent.cpp
The file was addedclang/test/Analysis/ctu-onego-existingdef.cpp
The file was modifiedclang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
The file was addedclang/test/Analysis/ctu-onego-small.cpp
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h
The file was modifiedclang/lib/StaticAnalyzer/Core/AnalyzerOptions.cpp
The file was modifiedclang/test/Analysis/analyzer-config.c
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
The file was addedclang/test/Analysis/Inputs/ctu-onego-small-other.cpp.externalDefMap.ast-dump.txt
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
The file was addedclang/test/Analysis/Inputs/ctu-onego-toplevel-other.cpp
The file was addedclang/test/Analysis/Inputs/ctu-onego-toplevel-other.cpp.externalDefMap.ast-dump.txt
The file was addedclang/test/Analysis/Inputs/ctu-onego-existingdef-other.cpp
The file was addedclang/test/Analysis/Inputs/ctu-onego-indirect-other.cpp
The file was addedclang/test/Analysis/ctu-onego-toplevel.cpp
The file was addedclang/test/Analysis/Inputs/ctu-onego-indirect-other.cpp.externalDefMap.ast-dump.txt
Commit d4cdf013c76419140c6bdfb460088b5f09d6472f by npopov
[JumpThreading] Use common code to skip freeze (NFC)

There are multiple places that want to look through freeze, so
store condition without freeze in a separate variable.
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
Commit 7d8ec4dc4461102bafed8063977a66e40562bbb3 by david.spickett
[lldb] const a couple of getters on MemoryRegionInfo

GetDirtyPageList was being assigned to const & in most places anyway.
If you wanted to change the list you'd make a new one and call
SetDirtyPageList.

GetPageSize is just an int so no issues being const.

Differential Revision: https://reviews.llvm.org/D125786
The file was modifiedlldb/include/lldb/Target/MemoryRegionInfo.h
The file was modifiedlldb/source/API/SBMemoryRegionInfo.cpp
Commit dd12c3433ee9b4ef15c633bd325ab5a0c9c5e03b by jay.foad
[AMDGPU] Shrink F16 MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10

Differential Revision: https://reviews.llvm.org/D125803
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Commit aa568e082b4c0aa1cfbc8d1937544af8adbde552 by riddleriver
[mlir:GreedyDriver] Return WalkResult::skip after deleting a known constant

This avoids use-after-free when trying to access the regions after visiting
the operation.
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Commit 3eb2281bc067688dc701cf94e267395680892cf0 by jay.foad
[AMDGPU] Aggressively fold immediates in SIFoldOperands

Previously SIFoldOperands::foldInstOperand would only fold a
non-inlinable immediate into a single user, so as not to increase code
size by adding the same 32-bit literal operand to many instructions.

This patch removes that restriction, so that a non-inlinable immediate
will be folded into any number of users. The rationale is:
- It reduces the number of registers used for holding constant values,
  which might increase occupancy. (On the other hand, many of these
  registers are SGPRs which no longer affect occupancy on GFX10+.)
- It reduces ALU stalls between the instruction that loads a constant
  into a register, and the instruction that uses it.
- The above benefits are expected to outweigh any increase in code size.

Differential Revision: https://reviews.llvm.org/D114643
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/usubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/and.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/or.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/v_pack.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/add.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ctlz.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/packed-fp32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmed3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fexp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-global-i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/xor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bypass-div.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scratch-buffer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shift-i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/max.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/zero_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/madak.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/salu-to-valu.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uaddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/immv216.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idiv-licm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/s_addk_i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sub.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udivrem24.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cttz.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-constant-i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8u.ll
Commit 18c70a7bd932d1259cd28b82f946bec5dc77bfc2 by npopov
[JumpThreading] Simplify getPredicateAt() based folding

It's sufficient to just fold the icmp to true/false here, and then
let constant terminator folding take care of the rest.

It should be noted that while replaceFoldableUses() may not replace
all uses of the icmp, at least the use in the terminator we're
working on is always replaceable, so terminator constant folding
should be reliably enabled as a subsequent step.
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
Commit 6d36cfed3b5db3e2d73c3ff1cc669464ef502e3d by frgossen
[MLIR] Make `parseDimensionListRanked` configurable wrt parsing a trailing `x`

Differential Revision: https://reviews.llvm.org/D125797
The file was modifiedmlir/lib/Parser/Parser.h
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Parser/AsmParserImpl.h
The file was modifiedmlir/lib/Parser/TypeParser.cpp
Commit 242961f23b4abaca999611fd364e93a8d2186371 by Tim Northover
[llvm][fix-irreducible] ensure that loop subtree under child is correctly reconnected to new loop

The modified function was incorrectly (not unnecessarily) ignoring grandchild
loops, and this change fixes the bug. In particular, this fixes the handling of
the loop { inner, body }. The TODO in the same function is talking about the b1
self loop, which may be "unnecessarily" lost, but that is a different issue.
The file was modifiedllvm/lib/Transforms/Utils/FixIrreducible.cpp
Commit e1d47d86d84588d7e49dbb5172403d17c44467f7 by npopov
[IR] Report whether replaceUsesOfWith() changed something (NFC)

With change reporting in transformation passes in mind.
The file was modifiedllvm/lib/IR/User.cpp
The file was modifiedllvm/include/llvm/IR/User.h
The file was modifiedllvm/unittests/IR/UserTest.cpp
Commit bdf25477f6f24621ceba2fb0a8ff1e7c0e181144 by npopov
[JumpThreading] Add additional freeze tests (NFC)

These are for the getPredicateAt() codepath.
The file was modifiedllvm/test/Transforms/JumpThreading/freeze.ll
Commit e2926501d886ce8c1cd08db1d3a02c314c2f412d by jay.foad
[AMDGPU] Aggressively fold immediates in SIShrinkInstructions

Fold immediates regardless of how many uses they have. This is expected
to increase overall code size, but decrease register usage.

Differential Revision: https://reviews.llvm.org/D114644
The file was modifiedllvm/test/CodeGen/AMDGPU/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_uint.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/operand-folding.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uaddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/and.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/s_movk_i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sra.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/usubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ssubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/madmk.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-global-i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/packed-fp32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/add.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-combines.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sub.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fexp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ctpop16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
Commit c9e7049754ac94a952de8ac6962c36f844e43b3c by npopov
[JumpThreading] Look through freeze in getPredicateAt() fold

This code is valid for any icmp, so we can safely look through a
freeze when trying to find one.

A caveat here is that replaceFoldableUses() may not end up replacing
any uses in this case. It might make sense to use the freeze as the
context instruction (rather than the terminator) if there is a
freeze, to ensure that it always gets folded. This would require
some changes to how replaceFoldedUses() works though, as it
currently assumes that the value is valid at the end of the block.
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
The file was modifiedllvm/test/Transforms/JumpThreading/select-unfold-freeze.ll
The file was modifiedllvm/test/Transforms/JumpThreading/freeze.ll
Commit 140ad30b24fa3154808311f2ea4e52167dda378a by ivan.kosarev
[AMDGPU][MC][GFX10] Add missing s_scratch_load tests.

Completes
https://reviews.llvm.org/D125117

Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D125753
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_smem.s
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
Commit 8e648f195c3d57e573fdd8023edcfd80e0516c61 by david.spickett
[lldb] Add --all option to "memory region"

This adds an option to the memory region command
to print all regions at once. Like you can do by
starting at address 0 and repeating the command
manually.

memory region [-a] [<address-expression>]

(lldb) memory region --all
[0x0000000000000000-0x0000000000400000) ---
[0x0000000000400000-0x0000000000401000) r-x <...>/a.out PT_LOAD[0]
<...>
[0x0000fffffffdf000-0x0001000000000000) rw- [stack]
[0x0001000000000000-0xffffffffffffffff) ---

The output matches exactly what you'd get from
repeating the command. Including that it shows
unmapped areas between the mapped regions.

(this is why Process GetMemoryRegions is not
used, that skips unmapped areas)

Help text has been updated to show that you can have
an address or --all but not both.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D111791
The file was modifiedlldb/source/Commands/Options.td
The file was modifiedlldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 04e5b7fd17748bd10ae0f30cb571103e5da0dde5 by Tim Northover
AArch64: fall back to DWARF instead of crashing on weird .cfi directives

CodeGen will only produce fixed formwat prologues, but hand-written assembly
can have .cfi directives in any combination they want. This should cause a
fallback to DWARF rather than an assertion failure (or an incorrect compact
unwind if assertions are disabled).
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
The file was modifiedllvm/test/MC/AArch64/arm64-compact-unwind-fallback.s
Commit 3f7fc0964e827a6f9900714ee47fa5f8f75b46d1 by llvm-dev
[X86] Regenerate select-ext.ll test for D125604

GlobalISel tests are barely supported on X86, so just regenerate for now to avoid a blocker
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-ext.mir
Commit 5a0b7e875f169a77b9ced81c406accbceced8012 by llvm-dev
[X86] coalesce-dead-lanes.mir - fix CHECK-LABEL typo identified in D125604
The file was modifiedllvm/test/CodeGen/X86/coalesce-dead-lanes.mir
Commit 27942499ec20697c347a74a1374350e90a0c17ad by llvm-dev
[X86] copy-propagation.ll - fix CHECK-NEXT typo identified in D125604
The file was modifiedllvm/test/CodeGen/X86/copy-propagation.ll
Commit ec3bb17870a4097a7fa3482defd77724f864b667 by llvm-dev
[X86] lvi-hardening-indirectbr.ll - fix X64-NOT typo identified in D125604
The file was modifiedllvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll
Commit bf84ab7684a39cabd63a039591809e13719996b0 by llvm-dev
[X86] statepoint-vreg-details.ll - fix CHECK-VREG-LABEL typo identified in D125604
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-details.ll
Commit f718664866ab4c4e6fe8cc8f319798c800f1916d by llvm-dev
[DebugInfo][X86] debug-info-template-parameter.ll - fix broken DW_AT_default_value checks identified in D125604
The file was modifiedllvm/test/DebugInfo/X86/debug-info-template-parameter.ll
Commit 1584b2c74e4c804a2c85d760a1a2c10b33465f2e by llvm-dev
[AArch64] fp16-v8-instructions.ll - remove some old defunct CHECKS identified in D125604

Typos meant that the update script never removed them
The file was modifiedllvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
Commit 3e928c4b9dfb01efd2cb968795e605760828e873 by david.spickett
Revert "[lldb] Add --all option to "memory region""

This reverts commit 8e648f195c3d57e573fdd8023edcfd80e0516c61
due to test failures on Windows:
https://lab.llvm.org/buildbot/#/builders/83/builds/19094
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedlldb/source/Commands/Options.td
The file was modifiedlldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
Commit d9398a91e2a6b8837a47a5fda2164c9160e86199 by david.spickett
[lldb] Remove non-address bits from read/write addresses in lldb

Non-address bits are not part of the virtual address in a pointer.
So they must be removed before passing to interfaces like ptrace.

Some of them we get way with not removing, like AArch64's top byte.
However this is only because of a hardware feature that ignores them.

This change updates all the Process/Target Read/Write memory methods
to remove non-address bits before using addresses.

Doing it in this way keeps lldb-server simple and also fixes the
memory caching when differently tagged pointers for the same location
are read.

Removing the bits is done at the ReadMemory level not DoReadMemory
because particualrly for process, many subclasses override DoReadMemory.

Tests have been added for read/write at the command and API level,
for process and target. This includes variants like
Read<sometype>FromMemory. Commands are tested to make sure we remove
at the command and API level.

"memory find" is not included because:
* There is no API for it.
* It already has its own address handling tests.

Software breakpoints do use these methods but they are not tested
here because there are bigger issues to fix with those. This will
happen in another change.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D118794
The file was modifiedlldb/source/Target/ProcessTrace.cpp
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/source/Target/Process.cpp
The file was addedlldb/test/API/linux/aarch64/non_address_bit_memory_access/Makefile
The file was addedlldb/test/API/linux/aarch64/non_address_bit_memory_access/TestAArch64LinuxNonAddressBitMemoryAccess.py
The file was addedlldb/test/API/linux/aarch64/non_address_bit_memory_access/main.c
Commit 95a8af2750e43d60e5ce8c051b16dc396d3cd7f1 by d-pre
[AMDGPU][MC][NFC] MUBUF code cleanup

Removed code that is no longer used after https://reviews.llvm.org/D124485.

Differential Revision: https://reviews.llvm.org/D125811
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
Commit 21c29a8ae053cb436141ee636333c4f816cc20c4 by sven.vanhaastregt
[OpenCL] Add cl_khr_subgroup_rotate builtins

Differential Revision: https://reviews.llvm.org/D124256
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
The file was modifiedclang/test/Headers/opencl-c-header.cl
The file was modifiedclang/lib/Headers/opencl-c-base.h
The file was modifiedclang/lib/Headers/opencl-c.h
Commit e497871356f2f7a42a508973960bf4f68dd4f7b8 by benny.kra
[mlir][complex] Add pow/sqrt/tanh ops and lowering to libm

Lowering through libm gives us a baseline version, even though it's not
going to be particularly fast. This is similar to what we do for some
math dialect ops.

Differential Revision: https://reviews.llvm.org/D125550
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was addedmlir/lib/Conversion/ComplexToLibm/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/Complex/IR/ComplexOps.td
The file was addedmlir/include/mlir/Conversion/ComplexToLibm/ComplexToLibm.h
The file was addedmlir/lib/Conversion/ComplexToLibm/ComplexToLibm.cpp
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was addedmlir/test/Conversion/ComplexToLibm/convert-to-libm.mlir
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 2321c36fbf763e273ed78b4209168ce783b5cf96 by archibald.elliott
[ARM] Don't Enable AES Pass for Generic Cores

This brings clang/llvm into line with GCC. The Pass is still enabled for
the affected cores, but is now opt-in when using `-march=`.

I also took the opportunity to add release notes for this change.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D125775
The file was modifiedllvm/lib/Target/ARM/ARM.td
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 169416c64a39bb85541befc8f651fcd0ac3014c6 by d-pre
[AMDGPU][MC][GFX7] Disable cache policy modifiers with SMRD

Differential Revision: https://reviews.llvm.org/D125799
The file was modifiedllvm/test/MC/AMDGPU/smem.s
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/MC/AMDGPU/cpol-err.s
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
The file was modifiedllvm/test/MC/AMDGPU/gfx7_err_pos.s
Commit fdd019530680afeb308ab39731d4e6f2e2ffa221 by kristof.beyls
[Security Group] Update representative for Rust.

Steve Klabnik recently left the Rust project. Josh Stone (the other member of
the Rust Security Response WG) replaces him as one of the vendor contacts for
Rust.

Differential Revision: https://reviews.llvm.org/D119137
The file was modifiedllvm/docs/Security.rst
Commit 939affc67d4534c75d240180575dd9484ae8c691 by llvm-dev
[AArch64] neon-vmull-high-p64.ll - fix name/check mismatch identified in D125604

Typos meant that we weren't actually checking the function name, which wasn't accounting for mangling
The file was modifiedllvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
Commit 4e198377f68085f866c516e635a35e4c3c3582cf by llvm-dev
[X86] addcarry.ll - add nounwind to prevent cfi noise on tests
The file was modifiedllvm/test/CodeGen/X86/addcarry.ll
Commit 89cacb9ee72cadd324d38c6b147854eba2b9b415 by benny.kra
[libcxx] [test] Add missing header for std::numeric_limits

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D122571
The file was modifiedlibcxx/test/std/iterators/iterator.container/ssize.pass.cpp
Commit 46d9a6ebd6155900e26cf036fcc312d1e1e10d3f by benny.kra
[libcxx] [test] Include header for strverscmp

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D122570
The file was modifiedlibcxx/test/support/platform_support.h
Commit 32ca9bd7b5b83a4bc84ed611e3744f20cf62dba6 by d-pre
[AMDGPU][MC][GFX940] Correct tied operand decoding for smfmac opcodes

Differential Revision: https://reviews.llvm.org/D125790
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/mai-gfx940.txt
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
Commit 128da94d38242c28e6bf23ad025e0cb2d6ce9e4f by npopov
[InstCombine] Remove disable-verify tests (NFC)

InstCombine is not required to do anything sensible if it receives
invalid IR.

These tests seem to be testing self-referential instructions that
may occur in unreachable code -- but InstCombine actually goes out
of the way to remove such instructions ahead of time so it doesn't
need to deal with them.
The file was removedllvm/test/Transforms/InstCombine/objsize-noverify.ll
The file was removedllvm/test/Transforms/InstCombine/select-crash-noverify.ll
Commit 00a12585933ef63ff1204bf5cd265f0071d04642 by david.spickett
[lldb][AArch64] Fix corefile memory reads when there are non-address bits

Previously if you read a code/data mask before there was a valid thread
you would get the top byte mask. This meant the value was "valid" as in,
don't read it again.

When using a corefile we ask for the data mask very early on and this
meant that later once you did have a thread it wouldn't read the
register to get the rest of the mask.

This fixes that and adds a corefile test generated from the same program
as in my previous change on this theme.

Depends on D118794

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D122411
The file was modifiedlldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
The file was modifiedlldb/test/API/linux/aarch64/non_address_bit_memory_access/main.c
The file was modifiedlldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp
The file was modifiedlldb/test/API/linux/aarch64/non_address_bit_memory_access/TestAArch64LinuxNonAddressBitMemoryAccess.py
The file was addedlldb/test/API/linux/aarch64/non_address_bit_memory_access/corefile
Commit be6d7cc93c45fff4c891c4b4952a7acca2439bc2 by spatel
[InstCombine] reduce code duplication for checking types; NFC
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 990cc49ca0ca216b3901beb015e5c00d2da40bf2 by spatel
[InstCombine] avoid crash on fold of icmp with cast operand

We could do better by inserting a bitcast from scalar int
to vector int or using an insertelement (the alternate test
does not crash because there's an independent fold like that).

But this doesn't seem like a likely pattern, so just bail out
for now.

Fixes issue #55516.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/cast-int-icmp-eq-0.ll
Commit ca875539f788c8063e243ce9ceb877a0d2ad9115 by sam.mccall
Reland(2) "[clangd] Indexing of standard library"

This reverts commit 6aabf60f2fb7589430c0ecc8fe95913c973fa248.
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was addedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was addedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was addedclang-tools-extra/clangd/index/StdLib.h
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
Commit 1236b66a98197109ed40141329d6056dfbe25967 by sam.mccall
[lit] pass LLVM_SYMBOLIZER_PATH through to tests.

Currently several buildbots give unsymbolized traces on crash.
I suspect these are configuring the symbolizer in this way and regressed in
D122251 or thereabouts.

Trying this coupled with a reland of patch that failed on a couple of bots with
no useful stacktrace...
The file was modifiedllvm/utils/lit/lit/TestingConfig.py
Commit 8e4c5d9902139b900c702721f087f46befef72e8 by npopov
[CGP] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/cttz-ctlz.ll
Commit 8c975eac34347aec1911a90ca07926f1d6325d8a by thomasp
Assert on polymorphic pointer intrinsic param

Opaque pointers cannot be polymorphic on the pointed type given their
lack thereof. However they are currently accepted by tablegen but the
intrinsic signature verifier trips when verifying any further
polymorphic type because the opaque pointer codepath for pointers will
not push the pointed type in ArgTys.

This commit adds an assert to easily catch such cases instead of having
the generic signature match failure.

Reviewed By: #opaque-pointers, nikic

Differential Revision: https://reviews.llvm.org/D125764
The file was modifiedllvm/lib/IR/Function.cpp
Commit 0990d5b549ee3fbd4d4c6b00c9df0909072fa668 by llvmgnsyncbot
[gn build] Port ca875539f788
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
Commit 47258ffc5c7aa9ae2017bdde58a88e0f928d8f07 by chris.bieneman
[NFC] correcting a code comment.
The file was modifiedllvm/lib/Object/DXContainer.cpp
Commit 6ca7eb2c6d7da2264f410f270633bf698ab5d87d by geek4civic
[SCEV] Part 1, Serialize function calls in function arguments.

Evaluation odering in function call arguments is implementation-dependent.
In fact, gcc evaluates bottom-top and clang does top-bottom.

Fixes #55283 partially.

Part of https://reviews.llvm.org/D125627
The file was modifiedllvm/lib/Transforms/Utils/SimplifyIndVar.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 4273e616e573f4854e9c659c2e6d8a31f3e3c595 by paulsson
[SystemZ] Bugfix in SystemZTargetLowering::combineINT_TO_FP()

Make sure to also handle extended value types to avoid crashing.

Resulting integers greater than 64 bits are not optimized (i128 is not a
legal type), and vectorizing seems to result in libcalls instead of just
scalarization.

Other extended vector types like <10 x float> are however now handled and
should result in vectorized conversions.

Reviewed By: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D125881
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/vec-move-23.ll
Commit f7988d08a8bf11e551e720ba72c90c42d6756ece by listmail
Revert "[BasicAA] Remove unneeded special case for malloc/calloc"

This reverts commit 9b1e00738c5ddba681e17e5cb7c260d9afc4c3a7.

Nikic reported in commit thread that I had forgotten history here, and that a) we'd tried this before, and b) had to revert due to an unexpected codegen impact.  Current measurements confirm the same issue still exists.
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/test/Transforms/GVN/nonescaping-malloc.ll
Commit d39928e2cc393a21c8367ef318019166124f4b56 by thakis
clang-cl: Move /Zc: tests from cl-options.c to cl-zc.cpp

Since we already have a dedicated file for testing the /Zc: flags,
let's be consistent about putting /Zc: tests there.

No behavior change.

Differential Revision: https://reviews.llvm.org/D125889
The file was modifiedclang/test/Driver/cl-zc.cpp
The file was modifiedclang/test/Driver/cl-options.c
Commit c44ba01de7f050f126a8a7b2ddeb6286237bb384 by jonathan.l.peyton
[OpenMP] libomp: honor passive wait policy requested with tasking

Currently the library ignores requested wait policy in the presence
of tasking. Threads always actively spin. The patch fixes this problem
making the wait policy passive if this explicitly requested by user.

Differential Revision: https://reviews.llvm.org/D123044
The file was modifiedopenmp/runtime/src/kmp_wait_release.h
The file was modifiedopenmp/runtime/src/kmp_tasking.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_settings.cpp
The file was modifiedopenmp/runtime/src/kmp_global.cpp
Commit fc0229fd6bfd1fb57409c284de5e5a8ac7349b69 by david.green
[ARM] Clean up a test check from D125604. NFC

The Arm test had a incorrect check line with the wrong offset. From the
look of the code it should be -400*4 = 0xFFFFF9C0 = 4294965696
The file was modifiedllvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll
Commit 1467e01f8f699fa2a69937dd07e51325ba71a93b by kito.cheng
[RISCV][NFC] Rename variable in RISCVVEmitter.cpp

- Use `Overloaded` rather than `Mangled`.
- Use `Prototype` or `Desc` rather than `Seq`, it's not just a string sequence.
  - `Prototype` for those PrototypeDescriptor will used to evaluate as argument type.
  - `Desc` for those PrototypeDescriptor will used to evaluate as part of function name.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D125886
The file was modifiedclang/utils/TableGen/RISCVVEmitter.cpp
Commit 6381d4845b06a6d45d5fc237b360fac2979f1193 by listmail
[tests] Add test coverage for issue causing revert f7988d0

As theorized, it does look like opnew is not getting inferred inaccessiblemmemonly.
The file was addedllvm/test/Transforms/GVN/nonescaping.ll
Commit e44fe27251953c4d878688b06b5f6d26f39cd6ed by npopov
[LoopUnroll] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/LoopUnroll/tripcount-overflow.ll
Commit 77533ea443aca6e9978d7c8a6822420f8345f6af by sam.mccall
Revert "Reland(2) "[clangd] Indexing of standard library""

This reverts commit ca875539f788c8063e243ce9ceb877a0d2ad9115.
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was removedclang-tools-extra/clangd/index/StdLib.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was removedclang-tools-extra/clangd/unittests/StdLibTests.cpp
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was removedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
Commit a74e075908585896b40b8f176e51f8832026b32d by flo
[AArch64] Add tests showing reassoc breaks (s|u)ml(a|s)l selection.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vmul.ll
Commit ca302f07b453cc79e56ff4834930697a6be52707 by llvmgnsyncbot
[gn build] Port 77533ea443ac
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 29e556fc2ba93028f0dc45c4c2636da6283e9c28 by david.spickett
[lldb] Change implementation of memory read --show-tags option

This does 2 things:
* Moves it after the short options. Which makes sense given it's
  a niche, default off option.
  (if 2 files for one option seems a bit much, I am going to reuse
  them for "memory find" later)
* Fixes the use of repeated commands. For example:
    memory read buf --show-tags
    <shows tags>
    memory read
    <shows tags>

Added tests for the repetition and updated existing help tests.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D125089
The file was modifiedlldb/test/API/commands/help/TestHelp.py
The file was addedlldb/source/Interpreter/OptionGroupMemoryTag.cpp
The file was modifiedlldb/test/API/linux/aarch64/mte_tag_access/TestAArch64LinuxMTEMemoryTagAccess.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
The file was modifiedlldb/source/Commands/Options.td
The file was modifiedlldb/source/Interpreter/CMakeLists.txt
The file was addedlldb/include/lldb/Interpreter/OptionGroupMemoryTag.h
Commit 66dfa36e7d00faf524ed7e6652162393065cfa3f by llvmgnsyncbot
[gn build] Port 29e556fc2ba9
The file was modifiedllvm/utils/gn/secondary/lldb/source/Interpreter/BUILD.gn
Commit 69edacbcf0c232de6213297cb600b0f0313c6397 by bixia
[mlir][sparse] Add support for complex.im and complex.re to the sparse compiler.

Add a test.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125834
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
Commit c218fd3d7d3764eb123c8429bbcd33bacfe2e633 by daniel.kiss
[libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE.

Program may set the RA_SIGN_STATE pseudo register by expressions.
Libunwind expected only the DW_CFA_AARCH64_negate_ra_state could change the value
of the register which leads to runtime errors on PAC enabled systems.
In the recent version of the aadwarf64[1] a limitation is added[2] to forbid the mixing the
DW_CFA_AARCH64_negate_ra_state with other DWARF Register Rule Instructions.

[1] https://github.com/ARM-software/abi-aa/releases/tag/2022Q1
[2] https://github.com/ARM-software/abi-aa/pull/129

Reviewed By: #libunwind, MaskRay

Differential Revision: https://reviews.llvm.org/D123692
Reland: test moved because it depends on exceptions.
The file was addedlibcxxabi/test/native/AArch64/ra_sign_state.pass.cpp
The file was modifiedlibunwind/src/DwarfInstructions.hpp
Commit e1ff449ec9272bf9af6a0eab5240775b9a8a09fc by joker.eph
Apply clang-tidy fixes for performance-for-range-copy in LinalgOps.cpp (NFC)
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 302158df6a694c051b46d28ff589c6fad8d81f5c by joker.eph
Apply clang-tidy fixes for llvm-else-after-return in OpenMPDialect.cpp (NFC)
The file was modifiedmlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
Commit 46eef7687639eca1319a93d93d9e588ee0219f8c by craig.topper
[DAGCombiner] Fix bug in MatchBSwapHWordLow.

This function tries to match (a >> 8) | (a << 8) as (bswap a) >> 16.

If the SRL isn't masked and the high bits aren't demanded, we still
need to ensure that bits 23:16 are zero. After the right shift they
will be in bits 15:8 which is where the important bits from the SHL
end up. It's only a bswap if the OR on bits 15:8 only takes the bits
from the SHL.

Fixes PR55484.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D125641
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/RISCV/bswap-bitreverse.ll
The file was modifiedllvm/test/CodeGen/X86/bswap.ll
The file was modifiedllvm/test/CodeGen/ARM/rev.ll
The file was modifiedllvm/test/CodeGen/Thumb/rev.ll
Commit 4739176fd3047dfa13eae307c56c6dba7b605019 by n.james93
[clang-tidy] Fix readability-simplify-boolean-expr crash with implicit cast in return.

Fixes https://github.com/llvm/llvm-project/issues/55557

Reviewed By: LegalizeAdulthood

Differential Revision: https://reviews.llvm.org/D125877
The file was modifiedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.h
The file was modifiedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.cpp
The file was modifiedclang-tools-extra/unittests/clang-tidy/ReadabilityModuleTest.cpp
Commit 087ef34fffb27de8aacce4aa56d5c2deb53bdd0b by i
[ObjCopy][NFC] Remove unneeded zero initialization

getNewMemBuffer has called memset.

Reviewed By: alexander-shaposhnikov

Differential Revision: https://reviews.llvm.org/D125833
The file was modifiedllvm/lib/ObjCopy/MachO/MachOWriter.cpp
Commit 47b8424a533d5c02fd8b3517047cf93e533f00d0 by aaron
Correct the diagnostic behavior for unreachable _Generic associations in C++

New diagnostics were added for unreachable generic selection expression
associations in ca75ac5f04f269def97e6844c2f5c9596b29c84c, but it did
not account for a difference in behavior between C and C++ regarding
lvalue to rvalue conversions. So we would issue diagnostics about a
selection being unreachable and then reach it. This corrects the
diagnostic behavior in that case.

Differential Revision: https://reviews.llvm.org/D125882
The file was modifiedclang/test/SemaCXX/generic-selection.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/generic-selection.c
Commit eafa0530417e09755b94d0e94afc0f792b98c80d by dthorn
[Debuginfod] Add --debug-file-directory to llvm-debuginfod-find.

This allows llvm-debuginfod-find to locate binaries in local build ID
directories configured via --debug-file-directory, the same flag used
for this purpose by llvm-symbolizer. This provides a consistent lookup
semantics between the two tools when configured the same way, in
particular when debug binaries may be located either locally or
remotely.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125864
The file was addedllvm/test/tools/llvm-debuginfod-find/local.test
The file was modifiedllvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
Commit ececce1b5ec1a83434568591e4c18ac79e4f3631 by phosek
Partially revert "[CMake] Passthrough OSX CMake options to builtins and runtimes"

This partially reverts commit 9cddfe3085c4c500e64350b56c37ae2ed1cbe3f6,
specifically passthrough for CMAKE_OSX_* since this can lead to build
passing through internal variables when it's not intended.
The file was modifiedllvm/runtimes/CMakeLists.txt
Commit bff4673b41781ec5bff6b96b52cf321d2271726c by jingham
Add a darwin platform setting to specify which exceptions debugserver
should not receive as exceptions (some will get converted to BSD
signals instead).  This is really the only stable way to ensure that
a Mach exception gets converted to it's equivalent BSD signal.  For
programs that rely on BSD signal handlers, this has to happen or you
can't even get the program to invoke the signal handler when under
the debugger.

This builds on a previous solution to this problem which required you
start debugserver with the -U flag.  This was not very discoverable
and required lldb be the one to launch debugserver, which is not always
the case.

Differential Revision: https://reviews.llvm.org/D125434
The file was modifiedlldb/include/lldb/Interpreter/OptionValueString.h
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformMacOSXProperties.td
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.mm
The file was modifiedlldb/source/Utility/StringExtractorGDBRemote.cpp
The file was addedlldb/test/API/macosx/ignore_exceptions/TestIgnoredExceptions.py
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachTask.mm
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachException.cpp
The file was modifiedlldb/tools/debugserver/source/DNB.cpp
The file was modifiedlldb/tools/debugserver/source/DNB.h
The file was modifiedlldb/include/lldb/Target/Platform.h
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachException.h
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was addedlldb/test/API/macosx/ignore_exceptions/Makefile
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
The file was addedlldb/test/API/macosx/ignore_exceptions/main.c
The file was modifiedlldb/tools/debugserver/source/RNBRemote.h
The file was modifiedlldb/tools/debugserver/source/RNBContext.h
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachTask.h
The file was modifiedlldb/tools/debugserver/source/RNBRemote.cpp
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
The file was modifiedlldb/source/Target/Platform.cpp
The file was modifiedlldb/include/lldb/Utility/StringExtractorGDBRemote.h
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.h
The file was modifiedlldb/tools/debugserver/source/debugserver.cpp
The file was modifiedlldb/tools/debugserver/source/RNBContext.cpp
Commit 91a8caa831ae9c0050ff6cd6f2104f6769932895 by thakis
[gn build] port 6694491affa18

Needed to link llvm-debuginfod-find after eafa0530417e.
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Debuginfod/BUILD.gn
Commit 4957518ef57f35e64d0b9716b745c654efa91d36 by jeffniu22
[mlir][ods] Simplify useDefaultType/AttributePrinterParser

The current behaviour of `useDefaultTypePrinterParser` and `useDefaultAttributePrinterParser` is that they are set by default, but the dialect generator only generates the declarations for the parsing and printing hooks if it sees dialect types and attributes. Same goes for the definitions generated by the AttrOrTypeDef generator.

This can lead to confusing and undesirable behaviour if the dialect generator doesn't see the definitions of the attributes and types, for example, if they are sensibly separated into different files: `Dialect.td`, `Ops.td`, `Attributes.td`, and `Types.td`.

Now, these bits are unset by default. Setting them will always result in the dialect generator emitting the declarations for the parsing hooks. And if the AttrOrTypeDef generator sees it set, it will generate the default implementations.

Reviewed By: rriddle, stellaraccident

Differential Revision: https://reviews.llvm.org/D125809
The file was modifiedmlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
The file was modifiedmlir/tools/mlir-tblgen/DialectGen.cpp
The file was modifiedmlir/examples/toy/Ch7/include/toy/Ops.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
The file was modifiedmlir/include/mlir/IR/DialectBase.td
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUBase.td
The file was modifiedmlir/include/mlir/Dialect/NVGPU/NVGPU.td
The file was modifiedmlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
The file was modifiedmlir/include/mlir/Dialect/DLTI/DLTIBase.td
The file was modifiedmlir/test/python/python_test_ops.td
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
The file was modifiedmlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
The file was modifiedmlir/include/mlir/Dialect/Quant/QuantOpsBase.td
The file was modifiedmlir/include/mlir/Dialect/Vector/IR/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
Commit e2f410feeab27a8bb2c015fc02bb8527702e401f by craig.topper
[RISCV] Add test cases showing failure to remove mask on rotate amounts.

If the masking AND has multiple users we fail to remove it.
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll
Commit 86f7d7074a0129955aa2f5c82fe8c383eb17a35a by craig.topper
[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates.

This will remove masks on the shift amount. We usually get this with
SimplifyDemandedBits in DAGCombine, but that's restricted to cases
where the AND has a single use. selectShiftMaskXLen does not have
that restriction.
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Commit bedf657d0f4c54ffe9ef4303382657a74296b544 by martin
[runtimes] Default LIB*_HERMETIC_STATIC_LIBRARY to ON on Windows

(In the case of libunwind, the cmake option is called
LIBUNWIND_HIDE_SYMBOLS, but it has the same effect as
LIBCXX_HERMETIC_STATIC_LIBRARY and
LIBCXXABI_HERMETIC_STATIC_LIBRARY.)

Previously, the same issue was dealt with by setting a project wide
define (_LIBUNWIND_HIDE_SYMBOLS,
_LIBCXXABI_DISABLE_VISIBILITY_ANNOTATIONS and
_LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS) if only building a static
library.  If building both static and shared at the same time, this
wasn't set, and the static library would contain dllexport directives.

The LIB*_HERMETIC_STATIC_LIBRARY and LIBUNWIND_HIDE_SYMBOLS cmake
options only apply the defines to the static library in the build,
even if building both static and shared at the same time.

(This could only be done use after the object libraries were
enabled, as a shared libcxx needs libcxxabi object files built
with dllexports included.)

This allows removing inelegant code for deciding how to build the
libcxxabi static library and a TODO comment that suggested that
users should need to start setting an option, which they shouldn't
need to. Finally, this gets rid of two XFAILs in tests.

Differential Revision: https://reviews.llvm.org/D125715
The file was modifiedlibcxx/src/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibcxx/test/libcxx/vendor/clang-cl/static-lib-exports.sh.cpp
The file was modifiedlibcxxabi/src/CMakeLists.txt
The file was modifiedlibcxx/test/libcxx/vendor/mingw/static-lib-exports.sh.cpp
The file was modifiedlibunwind/CMakeLists.txt
Commit 091a55c16ad4e87aa67a3c003fade1a226698734 by martin
[MC] [Win64EH] Remove an unused parameter to ARM64EmitUnwindCode. NFC.

Differential Revision: https://reviews.llvm.org/D125878
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
Commit 924defada9bc0e3c89b0c0e288d7cb4dd654e7d4 by martin
[MC] [Win64EH] Don't produce packed ARM64 unwind info with homed parameters

There's an inconsistency regarding the epilogs of packed ARM64
unwind info with homed parameters; according to the documentation
(and according to common sense), the epilog wouldn't have a series
of nop instructions matching the stp x0-x7 in the prolog - however
in practice, RtlVirtualUnwind still seems to behave as if the epilog
does have the mirrored nops from the prolog.

In practice, MSVC doesn't seem to produce packed unwind info with
homed parameters, which might be why this inconsistency hasn't
been noticed.

Thus, to play it safe, avoid creating such packed unwind info with
homed parameters. (LLVM's current behaviour matches the current
runtime behaviour of RtlVirtualUnwind, but if it later is bug fixed
to match the documentation, such unwind information would be
incorrect.)

See https://github.com/llvm/llvm-project/issues/54879 for further
discussion on the matter.

Differential Revision: https://reviews.llvm.org/D125876
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
The file was modifiedllvm/test/MC/AArch64/seh-packed-unwind.s
Commit fc2c8b2371d7c3ef7c0ed348598abadcfdfcd467 by abrachet
[libc] Add strlcpy

Differential Revision: https://reviews.llvm.org/D125806
The file was modifiedlibc/config/linux/api.td
The file was modifiedlibc/config/linux/aarch64/entrypoints.txt
The file was addedlibc/src/string/strlcpy.h
The file was modifiedlibc/test/src/string/CMakeLists.txt
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was addedlibc/test/src/string/strlcpy_test.cpp
The file was modifiedlibc/config/windows/entrypoints.txt
The file was modifiedlibc/src/string/CMakeLists.txt
The file was addedlibc/src/string/strlcpy.cpp
The file was modifiedlibc/config/darwin/arm/entrypoints.txt
The file was addedlibc/spec/bsd_ext.td
Commit 6adbcd2b102e25a613d8c2df74eddb1fb34e7216 by abrachet
[libc] Add String to bsd headers
The file was modifiedlibc/spec/bsd_ext.td
Commit 15c809e8e78083d59f1c0b09ca1d1644e0976961 by koraq
[libc++][format] Adds a formattable concept.

The concept is based on P2286R2 Formatting Ranges. It will be used to
optimise the storage of __format_arg_store as required by LWG-3473.

Depends on D120916

Reviewed By: #libc, Mordante

Differential Revision: https://reviews.llvm.org/D120921
The file was addedlibcxx/test/libcxx/utilities/format/format.formatter/format.formatter.spec/formattable.compile.pass.cpp
The file was addedlibcxx/include/__format/concepts.h
The file was modifiedlibcxx/include/module.modulemap
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/include/__format/format_fwd.h
The file was modifiedlibcxx/test/libcxx/private_headers.verify.cpp
The file was modifiedlibcxx/include/format
Commit d8de7244f261d450f40fc175b224d37acd751ec8 by llvmgnsyncbot
[gn build] Port 15c809e8e780
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit f0e61029506fd63bb300f2dbbd65ba792e4ef3a2 by koraq
[libc++][format] Adds formatter<charT[N], charT>.

This formatter isn't in the list of required formatters in

[format.formatter.spec]/2.2
  For each charT, the string type specializations
   template<> struct formatter<charT*, charT>;
  template<> struct formatter<const charT*, charT>;
  template<size_t N> struct formatter<const charT[N], charT>;
  template<class traits, class Allocator>
    struct formatter<basic_string<charT, traits, Allocator>, charT>;
  template<class traits>
    struct formatter<basic_string_view<charT, traits>, charT>;

Since remove_cvref_t<const charT[N]> is charT[N] the formatter is
required by

[format.functions]/25
  Preconditions: formatter<remove_cvref_t<Ti>, charT> meets the
  BasicFormatter requirements ([formatter.requirements]) for each Ti in
  Args.

Depends on D120921

Reviewed By: #libc, Mordante

Differential Revision: https://reviews.llvm.org/D121138
The file was modifiedlibcxx/include/__format/formatter_string.h
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/types.compile.pass.cpp
The file was addedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
The file was modifiedlibcxx/test/libcxx/utilities/format/format.formatter/format.formatter.spec/formattable.compile.pass.cpp
Commit 4d8268fbf4cd30d39530622b7f1dc487122b4f3c by koraq
[libc++][format] Improve format-arg-store.

This optimizes the __format_arg_store type to allow a more efficient
storage of the basic_format_args.

It stores the data in two arrays:
- A struct with the tag of the exposition only variant's type and the
  offset of the element in the data array. Since this array only depends
  on the type information it's calculated at compile time and can be
  shared by different instances of this class.
- The arguments converted to the types used in the exposition only
  variant of basic_format_arg. This means the packed data can be
  directly copied to an element of this variant.

The new code uses rvalue reference arguments in preparation for P2418.
The handle class also has some changes to prepare for P2418. The real
changed for P2418 will be done separately, but these parts make it
easier to implement that paper.

Some parts of existing test code are removed since they were no longer
valid after the changes, but new tests have been added.

Implements parts of:
- P2418 Add support for std::generator-like types to std::format

Completes:
- LWG3473 Normative encouragement in non-normative note

Depends on D121138

Reviewed By: #libc, vitaut, Mordante

Differential Revision: https://reviews.llvm.org/D121514
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/include/__format/format_args.h
The file was modifiedlibcxx/include/format
The file was addedlibcxx/include/__format/format_arg_store.h
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.context/format.context/ctor.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
The file was modifiedlibcxx/docs/Status/Cxx20Papers.csv
The file was modifiedlibcxx/include/module.modulemap
The file was modifiedlibcxx/test/std/utilities/format/format.functions/format_tests.h
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.context/format.context/arg.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
The file was modifiedlibcxx/include/__format/format_arg.h
The file was modifiedlibcxx/test/std/utilities/format/format.arguments/format.arg.store/make_wformat_args.pass.cpp
The file was modifiedlibcxx/include/__format/format_fwd.h
The file was modifiedlibcxx/docs/Status/Cxx2bIssues.csv
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
The file was modifiedlibcxx/test/libcxx/private_headers.verify.cpp
The file was removedlibcxx/test/std/utilities/format/format.arguments/format.arg.store/class.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.arguments/format.arg/operator_bool.pass.cpp
The file was modifiedlibcxx/test/libcxx/utilities/format/format.arguments/format.arg/visit_format_arg.pass.cpp
The file was modifiedlibcxx/test/std/utilities/format/format.formatter/format.context/format.context/locale.pass.cpp
Commit 5ac411aea802f5983b7979b9198ba7d8fb38f64d by yusra.syeda
[SystemZ][z/OS] Add the PPA1 to SystemZAsmPrinter

Differential Revision: https://reviews.llvm.org/D125725
The file was modifiedllvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
The file was modifiedllvm/lib/MC/MCContext.cpp
The file was addedllvm/include/llvm/BinaryFormat/GOFF.h
The file was modifiedllvm/include/llvm/MC/MCSectionGOFF.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/test/MC/GOFF/ppa1.ll
The file was modifiedllvm/include/llvm/MC/MCObjectFileInfo.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZAsmPrinter.h
The file was modifiedllvm/include/llvm/MC/MCContext.h
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
Commit f0c06c042040fd8e7f296a66f1253e571610e64b by koraq
[libc++][format][5/6] Improve format_to_n.

Use a specialized buffer wrapper to limit the number of insertions in the
buffer. After the limit has been reached the buffer only needs to count
the number of insertions to return the buffer size required to store the
entire output.

Depends on D110498

Reviewed By: #libc, Mordante

Differential Revision: https://reviews.llvm.org/D110499
The file was modifiedlibcxx/include/__format/buffer.h
The file was modifiedlibcxx/include/format
Commit e64722f686bd8a6d0c2c099ce6fb90e84f51341d by phosek
[CMake][Fuchsia] Build runtimes as universal libraries on OS X

We want to build libunwind, libc++abi and libc++ as universal libraries
supporting both x86_64 and arm64 architectures.

Differential Revision: https://reviews.llvm.org/D125908
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
The file was modifiedclang/cmake/caches/Fuchsia.cmake
Commit f8ae591fc985cc0ba397cbd60e227b21c045bb81 by michaelrj
[libc] fix missing semicolon in bsd_ext.td

Fix typo in previous commit

Differential Revision: https://reviews.llvm.org/D125913
The file was modifiedlibc/spec/bsd_ext.td
Commit e60c8c301ce64ae42dcb469d727d22833a31e17a by llvmgnsyncbot
[gn build] Port 4d8268fbf4cd
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit d4257fbbba234cdbb8d1973c508ee1aa1adcb4f2 by martin
[llvm-readobj] Improve printing of Windows ARM packed unwind info

Fix a couple minor details in the existing logic for calculating
saved registers and stack adjustment.

Synthesize the corresponding prologues and epilogues and print them.
(This supersedes the previous printout of one single list of stored
registers; as there's lots of minor nuance differences in how
registers are pushed/popped in various corner cases, it's better to
print the full prologue/epilogue instead of trying to condense it
into one single list.)

Print the raw values of the fields Reg, R, L (LinkRegister) and C
(Chaining) instead of only printing the derived values.

Differential Revision: https://reviews.llvm.org/D125644
The file was modifiedllvm/lib/Support/ARMWinEH.cpp
The file was modifiedllvm/include/llvm/Support/ARMWinEH.h
The file was addedllvm/test/tools/llvm-readobj/COFF/arm-unwind-packed.s
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.h
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
Commit a3b30d22da173446d1a2ccd49e442b3900b0027c by spatel
[InstCombine] add tests for bswap with shift op; NFC

issue #55327
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit ebbc37391f9d1de5e8c4bee14493fce20f9c6906 by spatel
[InstCombine] allow variable shift amount in bswap + shift fold

When shifting by a byte-multiple:
bswap (shl X, Y) --> lshr (bswap X), Y
bswap (lshr X, Y) --> shl (bswap X), Y

This was limited to constants as a first step in D122010 / 60820e53ec9d3be02 ,
but issue #55327 shows a source example (and there's a test based on that here)
where a variable shift amount is used in this pattern.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 29bebb0237965618b6c91fe32f63d13cf9ecabc5 by mkitzan
[GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM

I noticed https://reviews.llvm.org/D87415 added SDAG combines to fold
FMIN/MAX instrs with NaNs.

The patch implements the same NaN combines for GISel GMIR FMIN/MAX opcodes:
G_FMINNUM(X, NaN) -> X
G_FMAXNUM(X, NaN) -> X
G_FMINIMUM(X, NaN) -> NaN
G_FMAXIMUM(X, NaN) -> NaN

The patch adds AArch64 tests for these combines as well.

Reviewed by: arsenm

Differential revision: https://reviews.llvm.org/D125819
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit d8166e1900c05429abc726d379bc33281c4c98e4 by i
[Driver] Refactor /opt/rh detection

Check /opt/rh first to avoid `/opt/rh/*` newfstatat/etc calls on other
distributions.
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
Commit 42dac47e8708231795b59f09a1605124a4852369 by dblaikie
Fix some -Wstrict-prototypes issues in ORC examples
The file was modifiedllvm/examples/OrcV2Examples/OrcV2CBindingsReflectProcessSymbols/OrcV2CBindingsReflectProcessSymbols.c
The file was modifiedllvm/examples/OrcV2Examples/OrcV2CBindingsRemovableCode/OrcV2CBindingsRemovableCode.c
The file was modifiedllvm/examples/OrcV2Examples/OrcV2CBindingsBasicUsage/OrcV2CBindingsBasicUsage.c
Commit 4ac0589122830fc6d90e0ea091300c0b979a42dc by zhijian
[libc++][CI] fixed a return curr_symbol() for Russian in the libcxx/test/support/locale_helpers.h for AIX

Summary:

fixed a return curr_symbol() for Russian in the libcxx/test/support/locale_helpers.h for AIX

Reviewers:  David Tenty,Mark de Wever
Differential Revision: https://reviews.llvm.org/D125801
The file was modifiedlibcxx/test/support/locale_helpers.h
The file was modifiedlibcxx/test/std/localization/locale.categories/category.monetary/locale.moneypunct.byname/curr_symbol.pass.cpp
Commit 35660247dd9ce850dccd60cc55428a510dbdd1c8 by n.james93
[clang-tidy] Fix readability-simplify-boolean-expr when Ifs have an init statement or condition variable

Fixes https://github.com/llvm/llvm-project/issues/55553.

Reviewed By: LegalizeAdulthood

Differential Revision: https://reviews.llvm.org/D125874
The file was addedclang-tools-extra/test/clang-tidy/checkers/readability-simplify-bool-expr-cxx17.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/readability-simplify-bool-expr.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/SimplifyBooleanExprCheck.cpp
Commit 1e14b1a7977b0bdc725312f76ebe7173f6f1f62c by yusra.syeda
[SystemZ][z/OS] Add missing include to llvm/include/llvm/BinaryFormat/GOFF.h
Differential Revision: https://reviews.llvm.org/D125921
The file was modifiedllvm/include/llvm/BinaryFormat/GOFF.h
Commit 7d8060bc19e9b03c93d825a5a790e3c1f4978c52 by a.bataev
[SLP]Improve reductions vectorization.

The pattern matching and vectgorization for reductions was not very
effective. Some of of the possible reduction values were marked as
external arguments, SLP could not find some reduction patterns because
of too early attempt to vectorize pair of binops arguments, the cost of
consts reductions was not correct. Patch addresses these issues and
improves the analysis/cost estimation and vectorization of the
reductions.

The most significant changes in SLP.NumVectorInstructions:

Metric: SLP.NumVectorInstructions                                                                                                                                                                                                 [140/14396]

Program                                                                                        results  results0 diff
               test-suite :: SingleSource/Benchmarks/Adobe-C++/loop_unroll.test   920.00  3548.00 285.7%
                test-suite :: SingleSource/Benchmarks/BenchmarkGame/n-body.test    66.00   122.00  84.8%
      test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C/miniGMG/miniGMG.test   100.00   128.00  28.0%
test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test   664.00   810.00  22.0%
                 test-suite :: MultiSource/Benchmarks/mafft/pairlocalalign.test   592.00   687.00  16.0%
  test-suite :: MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame.test   402.00   426.00   6.0%
                   test-suite :: MultiSource/Applications/JM/lencod/lencod.test  1665.00  1745.00   4.8%
  test-suite :: External/SPEC/CINT2017rate/500.perlbench_r/500.perlbench_r.test   135.00   139.00   3.0%
test-suite :: External/SPEC/CINT2017speed/600.perlbench_s/600.perlbench_s.test   135.00   139.00   3.0%
                  test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test   388.00   397.00   2.3%
                   test-suite :: MultiSource/Applications/JM/ldecod/ldecod.test   895.00   914.00   2.1%
    test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test   240.00   244.00   1.7%
           test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test   240.00   244.00   1.7%
             test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test   820.00   832.00   1.5%
              test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test   820.00   832.00   1.5%
       test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 14804.00 14914.00   0.7%
                        test-suite :: MultiSource/Benchmarks/Bullet/bullet.test  8125.00  8183.00   0.7%
           test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test  1330.00  1338.00   0.6%
            test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test  1330.00  1338.00   0.6%
         test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test  9832.00  9880.00   0.5%
         test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test  5267.00  5291.00   0.5%
       test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test  4018.00  4024.00   0.1%
      test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test  4018.00  4024.00   0.1%
              test-suite :: External/SPEC/CFP2017speed/644.nab_s/644.nab_s.test   426.00   424.00  -0.5%
               test-suite :: External/SPEC/CFP2017rate/544.nab_r/544.nab_r.test   426.00   424.00  -0.5%
          test-suite :: External/SPEC/CINT2017rate/541.leela_r/541.leela_r.test   201.00   192.00  -4.5%
         test-suite :: External/SPEC/CINT2017speed/641.leela_s/641.leela_s.test   201.00   192.00  -4.5%

644.nab_s and 544.nab_r - reduced number of shuffles but increased number
of useful vectorized instructions.

641.leela_s and 541.leela_r - the function
`@_ZN9FastBoard25get_pattern3_augment_specEiib` is not inlined anymore
but its body gets vectorized successfully. Before, the function was
inlined twice and vectorized just after inlining, currently it is not
required. The vector code looks pretty similar, just like as it was before.

Differential Revision: https://reviews.llvm.org/D111574
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/crash_reordering_undefs.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
Commit 7aa1fa0a0a07f7949d2d77c099aab43cf9b75a91 by 31459023+hctim
Reland "[dwarf] Emit a DIGlobalVariable for constant strings."

An upcoming patch will extend llvm-symbolizer to provide the source line
information for global variables. The goal is to move AddressSanitizer
off of internal debug info for symbolization onto the DWARF standard
(and doing a clean-up in the process). Currently, ASan reports the line
information for constant strings if a memory safety bug happens around
them. We want to keep this behaviour, so we need to emit debuginfo for
these variables as well.

Reviewed By: dblaikie, rnk, aprantl

Differential Revision: https://reviews.llvm.org/D123534
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was addedllvm/test/DebugInfo/COFF/global-no-strings.ll
The file was addedclang/test/CodeGen/debug-info-variables.c
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/VFS/external-names.c
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
The file was removedllvm/test/Assembler/invalid-diglobalvariable-missing-name.ll
Commit e831ea6912d16a0afc270b35ba15a1535199fe41 by 31459023+hctim
[NFCI] clang-format scudo standalone
The file was modifiedcompiler-rt/lib/scudo/standalone/chunk.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/tsd_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/wrappers_cpp.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/checksum.h
The file was modifiedcompiler-rt/lib/scudo/standalone/crc32_hw.cpp
Commit 40e242eb625c7f2d3069ab97218725ae6ff83469 by jeffniu22
[mlir] Fix the error message for missing explicit TypeID

Summary:

The error message was incorrect

Reviewers: rriddle

Subscribers:
The file was modifiedmlir/lib/Support/TypeID.cpp
Commit f9a3c43eaa97d125595d83565a5d4aafd8dac734 by 31459023+hctim
[NFCI] clang-format gwp-asan files.
The file was modifiedcompiler-rt/lib/gwp_asan/tests/alignment.cpp
Commit 72f6dfb378751fd48bcd70fefd57e7a31bea501d by michaelrj
[libc][windows] fix strlcpy tests

Generally, size_t is an alias for unsigned long long. In the strlcpy
tests, the return value of strlcpy (a size_t) is compared to an unsigned
long. On Linux unsigned long and unsigned long long are both 64 bits,
but on windows unsigned long is 32 bits. Since the macros require
identical types for both sides, this caused a build failure on windows.
This patch changes the constants to be explicit size_t values.

Differential Revision: https://reviews.llvm.org/D125917
The file was modifiedlibc/test/src/string/strlcpy_test.cpp
Commit dd7233bc67e45106c4625df7d20391798f31d4a7 by Artem Dergachev
[Analyzer] Remove extra space from NSErrorChecker message.

Differential Revision: https://reviews.llvm.org/D125840
The file was modifiedclang/lib/StaticAnalyzer/Checkers/NSErrorChecker.cpp
The file was modifiedclang/test/Analysis/incorrect-checker-names.mm
The file was modifiedclang/test/Analysis/CheckNSError.m
Commit 77014b9a133409282c1ee2ee7b49089fe4f86834 by m_borsa
[Sanitizers][Darwin] Rename Apple macro  SANITIZER_MAC -> SANITIZER_APPLE

Initial introduction of the new macro before obsoleting the old one - the old name was really confusing.
Also moved SANITIZER_WATCHOS and SANITIZER_TVOS definitions under common #if defined(__APPLE__) block

Differential Revision: https://reviews.llvm.org/D125816
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
Commit 615255eb0969a192bebc8ba88dbeb674b5078ee7 by listmail
[RISCV] Add a test case where mutation still violates strict asserts in InsertVSETVLI

This is the test which triggered my disabling of the assert in d4545e6.  The
issue it reveals is basically the same as from cc0283a6, but in the cross
block case.

We visit block1, mutate the setvli (correctly), and then visit block two and
ask whether the vadd is compatible with the block state.  Before mutation, it
wasn't.  After mutation, it is.  And thus, we have our phase 1 vs 3 difference.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit 03ba8c83dd42292125fdbc74657a76388ab9558e by nemanja.i.ibm
[Debuginfod] Fix shared libs build break after eafa0530417e

The commit added a dependency on LLVMSymbolize but the
CMakeLists.txt file wasn't updated. This doesn't cause
issues for static libraries builds but breaks the shared
libraries build. This just adds the missing dependency.
The file was modifiedllvm/tools/llvm-debuginfod-find/CMakeLists.txt
Commit 797fabaab2a5e02d00de4755ef8f5a38127110df by llvm-project
[Analysis] Avoid virtual dtor. NFC.

Replace virtual destructor by a protected non-virtual one. Additionally also making derived structs as virtual avoids the warning from reappearing.

Also see the mailing list discussion: https://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20220516/1038290.html

Reviewed By: dblaikie, YangKeao

Differential Revision: https://reviews.llvm.org/D125830
The file was modifiedllvm/include/llvm/Analysis/DOTGraphTraitsPass.h
The file was modifiedllvm/include/llvm/Analysis/DomPrinter.h
Commit 1dcda06c97a6e9feb70753b8876b11bfa33417ce by andrey1.tretyakov
[SPIRV] Add simple tests to improve test coverage

Differential Revision: https://reviews.llvm.org/D125404
The file was addedllvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
The file was addedllvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i32.ll
The file was addedllvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll
The file was addedllvm/test/CodeGen/SPIRV/TruncToBool.ll
The file was addedllvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_v2i16.ll
The file was addedllvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll
The file was addedllvm/test/CodeGen/SPIRV/optnone.ll
The file was addedllvm/test/CodeGen/SPIRV/transcoding/DecorationMaxByteOffset.ll
Commit 6cc741bcbf5b840d5241fd15c8a7d747e42a0520 by rafaelauler
[BOLT] Testcase to repro R_X86_64_REX_GOTPCRELX bug

Add a new testcase that reproduces a bug when BOLTing current
trunk LLD bootstrapped with trunk clang. This makes it official
that we do not support this transformation but are working on
it. When the support is ready, XFAIL should be removed.

Reviewed By: maksfb, Amir, yota9

Differential Revision: https://reviews.llvm.org/D125843
The file was addedbolt/test/X86/gotpcrelx.s
Commit 8d03c49f498cb19358aacd28f57a852549d34ebd by Matthias Braun
Extend switch condition in optimizeSwitchPhiConst when free

In a case like:

    switch((i32)x) { case 42: phi((i64)42, ...); }

replace `(i64)42` with `zext(x)` when we can do so for free.

This fixes a part of https://github.com/llvm/llvm-project/issues/55153

Differential Revision: https://reviews.llvm.org/D124897
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/test/CodeGen/X86/switch-phi-const.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/switch-phi-const.ll
Commit 565f5dfa1f3ea52637fcfec4babd4a406d2e4c03 by rouson
[flang] test conforming & non-conforming lcobound

Add a test with standard-conforming  non-conforming lcobound()
intrinsic function invocations.  Also test that several
non-conforming lcobound() invocations generate the correct error
messages.

Differential Revision: https://reviews.llvm.org/DD123747
The file was addedflang/test/Semantics/lcobound.f90
Commit 3d869c88bb91d6e5a973a493068c1af689f13445 by brad
[Sparc] Make sure that we really don't emit quad-precision unless the "hard-quad-float" feature is available

Make sure that we really don't emit quad-precision unless the "hard-quad-float"
feature is available. Add missing replacement instruction patterns that are
needed to emit alternative code for conditional moves of quad-precision floats.

Test from koakuma.

Reviewed By: koakuma

Differential Revision: https://reviews.llvm.org/D119104
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was addedllvm/test/CodeGen/SPARC/hard-quad-float.ll
The file was modifiedllvm/lib/Target/Sparc/SparcInstrInfo.td
The file was modifiedllvm/lib/Target/Sparc/SparcInstr64Bit.td
Commit a5d618b393fe5027c0788fdb20b79d2d84c61067 by ox59616e
[M68k][Disassembler] Fix decoding conflict

This diff fixes decoding conflict between these pair of instructions:

ADD(16|32)dd / ADD(16|32)dr
SUB(16|32)dd / SUB(16|32)dr
AND(16|32)dd / AND(16|32)dr
OR(16|32)dd  / OR(16|32)dr

Reviewed By: ricky26

Differential Revision: https://reviews.llvm.org/D125861
The file was modifiedllvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
The file was modifiedllvm/lib/Target/M68k/M68kInstrArithmetic.td
The file was modifiedllvm/test/MC/Disassembler/M68k/arithmetic.txt
Commit b3718bc4672bcad45f155c6d2f9fce4ad409bb8e by medismail.bennani
[llvm/Support] Fallback to $TERM if terminfo has no "colors" capability

It can happen on macOS that terminal doesn't report the "colors"
capability in the terminfo database, in which case `tigetnum` returns -1.

This doesn't mean however that the terminal doesn't supports color, it
just means that the capability is absent from the terminal description.

In that case, we should still fallback to the checking the $TERM
environment variable to see if it supports ANSI escapes codes.

Differential Revision: https://reviews.llvm.org/D125914

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedllvm/lib/Support/Unix/Process.inc
Commit d71d1a947bee1247e952f22c13ad3ed3d041e36a by medismail.bennani
[lldb/Test] Add `use_colors` argument to the PExpect.launch wrapper

This patch adds a new `use_colors` argument to the PExpect.launch
method.

As the name suggests, it allows the user to conditionally enable color
support in the debugger, which can be helpful to test functionalities that
rely on that, like progress reporting. It defaults to False.

Differential Revision: https://reviews.llvm.org/D125915

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbpexpect.py
Commit 051a5ae99824fab879d9aade9d794e60ebc5c2e5 by medismail.bennani
[lldb/Core] Fix "sticky" long progress messages

When the terminal window is too small, lldb would wrap progress messages
accross multiple lines which would break the progress event handling
code that is supposed to clear the message once the progress is completed.

This causes the progress message to remain on the screen, sometimes partially,
which can be confusing for the user.

To fix this issue, this patch trims the progress message to the terminal
width taking into account the progress counter leading the message for
finite progress events and also the trailing `...`.

rdar://91993836

Differential Revision: https://reviews.llvm.org/D124785

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Core/Debugger.cpp
The file was modifiedlldb/include/lldb/Core/DebuggerEvents.h
The file was addedlldb/test/API/functionalities/progress_reporting/TestTrimmedProgressReporting.py
Commit 3e54ea0cfa3074e36ebee11848e072785437a8b9 by medismail.bennani
[lldb/crashlog] Fix line entries resolution in interactive mode

This patch subtracts 1 to the pc of any frame above frame 0 to get the
previous line entry and display the right line in the debugger.

This also rephrase some old comment from `48d157dd4`.

rdar://92686666

Differential Revision: https://reviews.llvm.org/D125928

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/examples/python/crashlog.py
The file was modifiedlldb/examples/python/scripted_process/crashlog_scripted_process.py
Commit 821ee172cdcd7196b6130321b53b6cc66bf1222b by medismail.bennani
dyld patch

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.h
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.h
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
Commit 80589f272c200798b57a5151680a993bc2cc00a7 by medismail.bennani
[lldb/test] Make some tests as XFAIL while I investigate the issue

This is very likely to be caused by d71d1a947bee1247e952f22c13ad3ed3d041e36a.

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/test/API/commands/gui/viewlarge/TestGuiViewLarge.py
The file was modifiedlldb/test/API/repl/clang/TestClangREPL.py
The file was modifiedlldb/test/API/iohandler/unicode/TestUnicode.py
The file was modifiedlldb/test/API/commands/expression/multiline-completion/TestMultilineCompletion.py
The file was modifiedlldb/test/API/iohandler/autosuggestion/TestAutosuggestion.py
Commit fd25ad51224e0558328cc9dfc6bf4533fd54403b by medismail.bennani
Revert 821ee172cdcd7196b6130321b53b6cc66bf1222b

This reverts commit 821ee172cdcd7196b6130321b53b6cc66bf1222b, that
landed by mistake.
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.h
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.h
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
The file was modifiedlldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
Commit d699e54ca291a7e58d997760481f246db32b506a by Jon Roelofs
Fix an or+and miscompile w/ GlobalISel

Fixes #55284
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit 51df77f36d8e769c17a4c3adab394911a770217e by Chenbing.Zheng
[InstCombine] Allow undef vectors when foldSelectToCopysign

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D125671
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
Commit ffaaf2498bda550beeedadb79060323b8d3b0188 by Chenbing.Zheng
[InstCombine] (rot X, ?) == 0/-1 --> X == 0/-1

In this patch we add a function foldICmpInstWithConstantAllowUndef
to fold integer comparisons with a constant operand: icmp Pred X, C
where X is some kind of instruction and C is AllowUndef.

We move this fold to the new function, so that it can solve undef elts in a vector.

Reviewed By: spatel, RKSimon

Differential Revision: https://reviews.llvm.org/D125220
The file was modifiedllvm/test/Transforms/InstCombine/icmp-fsh.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit fbf0c4229410fb17842cc0c0db882eeba6252ae8 by medismail.bennani
Revert "[lldb/test] Make some tests as XFAIL while I investigate the issue"

This reverts commit 80589f272c200798b57a5151680a993bc2cc00a7.
The file was modifiedlldb/test/API/iohandler/autosuggestion/TestAutosuggestion.py
The file was modifiedlldb/test/API/commands/expression/multiline-completion/TestMultilineCompletion.py
The file was modifiedlldb/test/API/repl/clang/TestClangREPL.py
The file was modifiedlldb/test/API/commands/gui/viewlarge/TestGuiViewLarge.py
The file was modifiedlldb/test/API/iohandler/unicode/TestUnicode.py
Commit 1351a9b19ecf48ebb2caad8ae6d8776a6dc1786d by medismail.bennani
[lldb/test] Fix failures caused by a previous PExpect.launch change

This should fix the issues introduced by d71d1a9, which skipped all the
test setup commands.

This also fixes the test failures happening in TestAutosuggestion.py.

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbpexpect.py
The file was modifiedlldb/test/API/iohandler/autosuggestion/TestAutosuggestion.py
Commit 861489af1b4947a107e501e39bafb4f2785456cb by zixuan.wu
[NFC][RISCV] Enable TuneNoDefaultUnroll feature to control targets which use default unroll preference

In RISCVTargetTransformInfo, enumerating the processor family is not a good way to predict.
Because it needs to enumerate many subtarget family and is hard to update if add new subtarget.
Instead, create a feature to distinguish whether targets want to use default unroll preference or not.

Keep TuneSiFive7 because it's flag to indicate subtarget family, which may used in other place.

Differential Revision: https://reviews.llvm.org/D125741
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Commit 90ea81fcb28e48c080e1a9016dd5262eeb33d0ce by zhongyunde
[LV] Widen freeze instead of scalarizing it

This patch changes the strategy for vectorizing freeze instrucion, from
replicating multiple times to widening according to selected VF.

Fixes #54992

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D125016
The file was addedllvm/test/Transforms/LoopVectorize/vector-freeze.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit b21c03854cee200c1ea9d693a4daf9cf06408f14 by apivovarov
Fix if statement in DebugInfo/GSYM/LookupResult.cpp
The file was modifiedllvm/lib/DebugInfo/GSYM/LookupResult.cpp
Commit 2bb252852c72a4563fd7cd36604a1698c34d22a8 by stellaraccident
[mlir] Add GlobalOp, GlobalLoadConstOp to ml_program.

The approach I took was to define a dialect 'extern' attribute that a GlobalOp can take as a value to signify external linkage. I think this approach should compose well and should also work with wherever the OpaqueElements work goes in the future (since that is just another kind of attribute). I special cased the GlobalOp parser/printer for this case because it is significantly easier on the eyes.

In the discussion, Jeff Niu had proposed an alternative syntax for GlobalOp that I ended up not taking. I did try to implement it but a) I don't think it made anything easier to read in the common case, and b) it made the parsing/printing logic a lot more complicated (I think I would need a completely custom parser/printer to do it well). Please have a look at the common cases where the global type and initial value type match: I don't think how I have it is too bad. The less common cases seem ok to me.

I chose to only implement the direct, constant load op since that is non side effecting and there was still discussion pending on that.

Differential Revision: https://reviews.llvm.org/D124318
The file was modifiedmlir/test/Dialect/MLProgram/ops.mlir
The file was addedmlir/include/mlir/Dialect/MLProgram/IR/MLProgramAttributes.td
The file was modifiedmlir/include/mlir/Dialect/MLProgram/IR/MLProgram.h
The file was addedmlir/include/mlir/Dialect/MLProgram/IR/MLProgramAttributes.h
The file was modifiedmlir/lib/Dialect/MLProgram/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
The file was modifiedmlir/lib/Dialect/MLProgram/IR/MLProgramDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/MLProgram/IR/CMakeLists.txt
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
The file was modifiedmlir/lib/Dialect/MLProgram/IR/MLProgramOps.cpp
The file was addedmlir/test/Dialect/MLProgram/attrs.mlir
The file was modifiedmlir/test/Dialect/MLProgram/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/MLProgram/IR/MLProgramOps.td
Commit 8b7e85f4f8403bd08e724178777df329aed6526e by stellaraccident
[mlir][python] Add Python bindings for ml_program dialect.

Differential Revision: https://reviews.llvm.org/D125852
The file was addedmlir/python/mlir/dialects/_ml_program_ops_ext.py
The file was addedmlir/test/python/dialects/ml_program.py
The file was addedmlir/python/mlir/dialects/MLProgramOps.td
The file was addedmlir/python/mlir/dialects/ml_program.py
The file was modifiedutils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
The file was modifiedmlir/python/CMakeLists.txt
Commit 03ea140b3a285c9a4400ee007b1790b110cbf984 by sam.mccall
Reland(3) "[clangd] Indexing of standard library"

Tracked down the crash, which was argument-evaluation-order UB
in the wrapping indexStandardLibrary().
Sorry for the churn!

This reverts commit 77533ea443aca6e9978d7c8a6822420f8345f6af.
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/unittests/TUSchedulerTests.cpp
The file was addedclang-tools-extra/clangd/index/StdLib.cpp
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.cpp
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.h
The file was modifiedclang-tools-extra/clangd/index/SymbolOrigin.h
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was addedclang-tools-extra/clangd/index/StdLib.h
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/TUScheduler.cpp
The file was addedclang-tools-extra/clangd/unittests/StdLibTests.cpp
Commit 07c663590114a7457a747653ad447c966c0e0cd1 by sam.mccall
[clang-tidy] Fix logic of assertion
The file was modifiedclang-tools-extra/clang-tidy/readability/ContainerContainsCheck.cpp
Commit dfd3a385d6aaf7f02396dc3684cefd00ab5963ee by llvmgnsyncbot
[gn build] Port 03ea140b3a28
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit cd387e43bf89438a83352d47e3d33bc34b697761 by sam.mccall
[pseudo] Squash some warnings. NFC

Explicitly sizing Kind enum suggests that too-large values are allowed,
and that putting it in a bitfield is dangerous.

GCC doesn't like condition ? integer : enum.
The file was modifiedclang-tools-extra/pseudo/lib/LRTable.cpp
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/Forest.h
Commit 4f35ca59d0fe1f0955d9e085e2c8ebd1bf27e421 by sam.mccall
[clangd] Suppress warning: control reaches end of function
The file was modifiedclang-tools-extra/clangd/index/StdLib.cpp
Commit 993070d11f1612e1fc6b2ac120064d7ecf4a00c4 by Lian.Wang
[LegalizeTypes][VP][NFC] Use an if and two returns instead of ?: operator

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125858
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Commit bbc6834e2635a60230cd410d3f32b7c6d11ad208 by Lian.Wang
[LegalizeTypes][VP] Add integer promotions support for VP_TRUNCATE

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125739
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
Commit 4df795bff75289941508d07bbe9105b93b098105 by sam.mccall
[Serialization] Delta-encode consecutive SourceLocations in TypeLoc

Much of the size of PCH/PCM files comes from stored SourceLocations.
These are encoded using (almost) their raw value, VBR-encoded. Absolute
SourceLocations can be relatively large numbers, so this commonly takes
20-30 bits per location.

We can reduce this by exploiting redundancy: many "nearby" SourceLocations are
stored differing only slightly and can be delta-encoded.
Randam-access loading of AST nodes constrains how long these sequences
can be, but we can do it at least within a node that always gets
deserialized as an atomic unit.

TypeLoc is implemented in this patch as it's a relatively small change
that shows most of the API.
This saves ~3.5% of PCH size, I have local changes applying this technique
further that save another 3%, I think it's possible to get to 10% total.

Differential Revision: https://reviews.llvm.org/D125403
The file was modifiedclang/include/clang/Serialization/ASTRecordReader.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was addedclang/unittests/Serialization/SourceLocationEncodingTest.cpp
The file was modifiedclang/include/clang/Serialization/ASTRecordWriter.h
The file was modifiedclang/include/clang/Serialization/ASTWriter.h
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/include/clang/Serialization/ASTReader.h
The file was addedclang/include/clang/Serialization/SourceLocationEncoding.h
The file was modifiedclang/unittests/Serialization/CMakeLists.txt
Commit d3a6f5739130409602edac1b6588613c458d7321 by daniel.kiss
[libunwind] Remove -Wsign-conversion warning

Reland after dependent change reland.
The file was modifiedlibunwind/src/DwarfInstructions.hpp
Commit f035068bb3cf84976db955585afbb3b49cbea5a2 by Lian.Wang
[LegalizeVectorTypes][VP] Add widen and split support for VP_SETCC

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D125446
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit 481691572d1fa6ad56ab24c73000396fd8babef8 by sam.mccall
[Serialization] Add missing includes for CHAR_BIT
The file was modifiedclang/unittests/Serialization/SourceLocationEncodingTest.cpp
The file was modifiedclang/include/clang/Serialization/SourceLocationEncoding.h
Commit 3948962b454022c2c8de6f67942a9cbd1f0351a0 by llvmgnsyncbot
[gn build] Port 4df795bff752
The file was modifiedllvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Commit 4e8b2ac7c01982f05d10e100299dadb5d4c79c5e by asb
[WebAssembly] Fix bug where -no-type-check failed to completely disable the typechecker

Related to <https://github.com/llvm/llvm-project/issues/55566>.
Committing directly (per LLVM's code review policy) as this is a trivial
fix.
The file was modifiedllvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
The file was addedllvm/test/MC/WebAssembly/type-checker-disabled.s
Commit 94d6dd90576637fa0eb2c40ca92320ad4c1a6942 by gchatelet
[libc] Apply no-builtin everywhere, remove unnecessary flags

Some functions like `stpncpy` are implemented in terms of `memset` but are not
currently using `-fno-builtin-memset`. This is somewhat hidden by the fact that
we use `-ffreestanding` globally and that `-ffreestanding` implies
`-fno-builtin` for Clang.

This patch also removes `-mllvm -combiner-global-alias-analysis` that is Clang
specific and that does not bring substantial gains on modern processors.

Also we keep `-mllvm --tail-merge-threshold=0` for aarch64 in CMakeLists.txt
but we omit it in the Bazel config. This is because Bazel consumes the source
files directly and so it can use PGO to take optimal decisions locally.

Differential Revision: https://reviews.llvm.org/D125894
The file was modifiedutils/bazel/llvm-project-overlay/libc/BUILD.bazel
The file was modifiedlibc/src/string/CMakeLists.txt
The file was modifiedutils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
The file was modifiedlibc/cmake/modules/LLVMLibCObjectRules.cmake
Commit 2f8c067bef34bac2ecc8a9ab74e85fb4a442b614 by asb
[WebAssembly][NFC] Fix errant tabs in test case in last commit

[4e8b2ac](https://reviews.llvm.org/rG4e8b2ac7c019) contained unintended
tabs. This commit fixes that.
The file was modifiedllvm/test/MC/WebAssembly/type-checker-disabled.s
Commit c0f5beef2fb19c0444d14b96decdf6e13d7a0917 by kkleine
[release] Add cmake as an extra tarball and not bundle it

Revert "Add cmake/ to release tarballs via concatenation"

This reverts commit 3a33664e8838e8b77acd1bbb13b1cf5e580a1077.

Revert "Add cmake to source release tarballs"

This reverts commit 32a0482a65b86cf0d84ea7e784cca9852df5c67c.

Reviewed By: tstellar, aaronpuchert

Differential Revision: https://reviews.llvm.org/D125798
The file was modifiedllvm/utils/release/export.sh
Commit 530bab1f93da09b40608e957553bed980bc83652 by Lian.Wang
[RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation

Re-landed D125206

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125206
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
Commit 43c0f90dd6eb1d3481a4d5e384a33d0d99b7aa86 by kbobyrev
[clangd] NFC: Clarify the Include Cleaner warning
The file was modifiedclang-tools-extra/clangd/IncludeCleaner.cpp
Commit 4f5a4215bfc896362adab89abc69f0e69de200ef by kbobyrev
[clangd] Update the test after diagnostic message change
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
Commit 70ace420c1f09447a07f0d93d73284a15cfa198a by ivan.kosarev
[AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir.

Discovered with D125604.

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125900
The file was modifiedllvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
Commit 6bec3e9303d68b8b264de3a02ca943d9dd752004 by jay.foad
[APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

Most clients only used these methods because they wanted to be able to
extend or truncate to the same bit width (which is a no-op). Now that
the standard zext, sext and trunc allow this, there is no reason to use
the OrSelf versions.

The OrSelf versions additionally have the strange behaviour of allowing
extending to a *smaller* width, or truncating to a *larger* width, which
are also treated as no-ops. A small amount of client code relied on this
(ConstantRange::castOp and MicrosoftCXXNameMangler::mangleNumber) and
needed rewriting.

Differential Revision: https://reviews.llvm.org/D125557
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Analysis/ConstantFolding.cpp
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/IR/ConstantRange.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedllvm/lib/Support/APInt.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/lib/Support/APFixedPoint.cpp
The file was modifiedllvm/utils/TableGen/VarLenCodeEmitterGen.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedpolly/lib/CodeGen/IslExprBuilder.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/lib/Analysis/MemoryBuiltins.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
The file was modifiedllvm/test/TableGen/VarLenEncoder.td
Commit 4e432f1b7ce6af4b24e67ebd21d119b092427a03 by jay.foad
[APInt] Deprecate truncOrSelf, zextOrSelf and sextOrSelf

Differential Revision: https://reviews.llvm.org/D125558
The file was modifiedllvm/include/llvm/ADT/APInt.h
The file was modifiedllvm/unittests/ADT/APIntTest.cpp
Commit 44673278e029d7a6f56c8a3177247026b831720f by d-pre
[AMDGPU][MC][GFX940] Add SMFMAC aliases

Differential Revision: https://reviews.llvm.org/D125888
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/test/MC/AMDGPU/mai-gfx940.s
Commit f820625503744472be8312bb70ee0da197816067 by andrzej.warzynski
[flang][driver] Make driver accept `-module-dir<value>`

`-module-dir` is Flang's equivalent for `-J` from GFortran (in fact,
`-J` is an alias for `-module-dir` in Flang). Currently, only
`-module-dir <value>` is accepted. However, `-J` (and other options for
specifying various paths) accepts `-J<value>` as well as `-J <value>`.
This patch makes sure that `-module-dir` behaves consistently with other
such flags.

Differential Revision: https://reviews.llvm.org/D125957
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedflang/test/Driver/write-module.f90
Commit dd644ddf85be4abde554fc1c9af8ba63308bffa1 by david.green
[AArch64] Extend zero vector TBL codegen tests. NFC
The file was modifiedllvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
Commit 13e1cf806567bc4987817e14a774198c3e3f2709 by david.spickett
Reland "[lldb] Add --all option to "memory region""

This reverts commit 3e928c4b9dfb01efd2cb968795e605760828e873.

This fixes an issue seen on Windows where we did not properly
get the section names of regions if they overlapped. Windows
has regions like:
[0x00007fff928db000-0x00007fff949a0000) ---
[0x00007fff949a0000-0x00007fff949a1000) r-- PECOFF header
[0x00007fff949a0000-0x00007fff94a3d000) r-x .hexpthk
[0x00007fff949a0000-0x00007fff94a85000) r-- .rdata
[0x00007fff949a0000-0x00007fff94a88000) rw- .data
[0x00007fff949a0000-0x00007fff94a94000) r-- .pdata
[0x00007fff94a94000-0x00007fff95250000) ---

I assumed that you could just resolve the address and get the section
name using the start of the region but here you'd always get
"PECOFF header" because they all have the same start point.

The usual command repeating loop used the end address of the previous
region when requesting the next, or getting the section name.
So I've matched this in the --all scenario.

In the example above, somehow asking for the region at
0x00007fff949a1000 would get you a region that starts at
0x00007fff949a0000 but has a different end point. Using the load
address you get (what I assume is) the correct section name.
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py
The file was modifiedlldb/source/Commands/Options.td
The file was modifiedlldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 017c98276b07a0abd1204ff34ee2b8f761099fac by ox59616e
[NFC][M68k] Replace `APInt::zextOrSelf` with `APInt::zext`

This is a follow up to D125558
The file was modifiedllvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
Commit 602f81ec336330f97e22442b98035c6f007cac6d by david.green
[AArch64] Fix zero element TBL indices

A TBL instruction will fill out-of-range values with 0's, something used
in D121139 to turn tbl2 with a zero input into tbl1s. This works OK for
v16i8, but for v8i8 the input is still treated as a v16i8, so
out-of-range values (like a lane index of 8) would end up loading values
from the top half of the input register. Clean this up by detecting the
out of range values and making sure they really use out of range values.
There is a fix for swapped indices of 64bit input vectors too, which
could be incorrectly adjusted if the zerovector was the first operand.

Fixes #55545

Differential Revision: https://reviews.llvm.org/D125865
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
Commit df25f0d5202bbd9e2e909dccb1aa16f8ebad5e7b by ox59616e
[M68k] Fix a bug in disassembler

Sorry for my reckless patch. In some cases `RoundUp` is less than
the bit width of APInt. We need to check this before we do zext.
The file was modifiedllvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
Commit 068f14f1e4ec69d218df544487f9420f2b3ab29b by david.spickett
[lldb] Add --show-tags option to "memory find"

This is off by default. If you get a result and that
memory has memory tags, when --show-tags is given you'll
see the tags inline with the memory content.

```
(lldb) memory read mte_buf mte_buf+64 --show-tags
<...>
0xfffff7ff8020: 00 00 00 00 00 00 00 00 0d f0 fe ca 00 00 00 00 ................ (tag: 0x2)
<...>
(lldb) memory find -e 0xcafef00d mte_buf mte_buf+64 --show-tags
data found at location: 0xfffff7ff8028
0xfffff7ff8028: 0d f0 fe ca 00 00 00 00 00 00 00 00 00 00 00 00 ................ (tags: 0x2 0x3)
0xfffff7ff8038: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ (tags: 0x3 0x4)
```

The logic for handling alignments is the same as for memory read
so in the above example because the line starts misaligned to the
granule it covers 2 granules.

Depends on D125089

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D125090
The file was modifiedlldb/test/API/commands/help/TestHelp.py
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
The file was modifiedlldb/test/API/linux/aarch64/mte_tag_access/TestAArch64LinuxMTEMemoryTagAccess.py
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedlldb/include/lldb/Interpreter/OptionGroupMemoryTag.h
The file was modifiedlldb/test/API/linux/aarch64/mte_tag_access/main.c
The file was modifiedlldb/source/Interpreter/OptionGroupMemoryTag.cpp
Commit d633dbd195732fe2e343297c37afcb2c3be71d14 by william.schmidt
[SLP][NFC] Pre-commit test showing vectorization preventing FMA

When we generate a horizontal reduction of floating adds fed by a vectorized
tree rooted at floating multiplies, we should account for the cost of no
longer being able to generate scalar FMAs.  Similarly, if we vectorize a
list of floating multiplies that each feeds a single floating add, we should
again account for this cost.

The first test was reduced from a case where the vectorizable tree looked
barely profitable (cost -1) with a horizontal reduction, but produced
substantially worse code than allowing the FMAs to be generated.  The second
test was derived from the first: we again generate a horizontal reduction
here, but even if the horizontal reduction is forced to be unprofitable, we
try to vectorize the multiplies.  I have follow-up patches to address these
issues.

Differential Revision: https://reviews.llvm.org/D124867
The file was addedllvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Commit 5bbf6ad5b64c2b3cc669ce7698e1bbf5a7f09539 by usx
Add an option to fill container for ref

This allows index implementations to fill container details when required specially when computing containerID is expensive.

Differential Revision: https://reviews.llvm.org/D125925
The file was modifiedclang-tools-extra/clangd/index/remote/Index.proto
The file was modifiedclang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
The file was modifiedclang-tools-extra/clangd/index/Index.h
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
Commit 5f4541fefbfc3ea0ccfb5c19fba100ab6024d57b by bradley.smith
[AArch64][SVE] Convert SRSHL to LSL when the fed from an ABS intrinsic

Differential Revision: https://reviews.llvm.org/D125233
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
Commit 06cf0ce90a8f5862e9a7560a422ddea171ac3ca9 by nikolasklauser
[libc++] Enable move semantics for vector in C++03

We require move semantics in C++03 anyways, so let's enable them for the containers.

Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D123802
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/emplace_back.pass.cpp
The file was modifiedlibcxx/include/__iterator/move_iterator.h
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.pass.cpp
The file was modifiedlibcxx/test/support/MoveOnly.h
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.cons/move_alloc.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.cons/move.addressof.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.cons/copy.move_only.verify.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.addressof.compile.pass.cpp
The file was modifiedlibcxx/include/vector
The file was modifiedlibcxx/test/std/containers/sequences/array/array.creation/to_array.fail.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.pass.cpp
The file was modifiedlibcxx/include/__utility/move.h
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.cons/move.pass.cpp
The file was modifiedlibcxx/test/support/test_allocator.h
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.addressof.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/resize_not_move_insertable.fail.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.modifiers/push_back_rvalue.pass.cpp
The file was modifiedlibcxx/test/std/utilities/utility/forward/move_if_noexcept.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/vector.cons/assign_move.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iterator/types.pass.cpp
Commit b2f9bde2e0e0fb9a26c2809aed17213e0920cf0f by d.dudkin
[flang][NFC] Allow whitespaces before `ERROR`

This change allows to write whitespaces before the `ERROR` keyword
in semantic tests for consistency with other testing infrastructure.

Also, one test is changed in order to test if the change works
correctly.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D125884
The file was modifiedflang/test/Semantics/test_errors.py
The file was modifiedflang/test/Semantics/altreturn04.f90
Commit f94a4476791873a4af1986abcd13c18991a599ee by nikolasklauser
[libc++] Granularize algorithm benchmarks

Reviewed By: ldionne, #libc

Spies: libcxx-commits, mgorny, mgrang

Differential Revision: https://reviews.llvm.org/D124740
The file was addedlibcxx/benchmarks/algorithms/sort.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/make_heap.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/sort_heap.bench.cpp
The file was modifiedlibcxx/benchmarks/CMakeLists.txt
The file was removedlibcxx/benchmarks/algorithms.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/pop_heap.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/make_heap_then_sort_heap.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/push_heap.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/min_max_element.bench.cpp
The file was addedlibcxx/benchmarks/algorithms/common.h
The file was addedlibcxx/benchmarks/algorithms/stable_sort.bench.cpp
Commit 729467aceff8b5e47821f35697448b08c5379af8 by Joseph.Nash
[AMDGPU] gfx11 LDSDIR instructions MC support

Contributors:
Carl Ritson <carl.ritson@amd.com>

Patch 8/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125498

Reviewed By: critson, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D125820
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
The file was addedllvm/test/MC/AMDGPU/ldsdir.s
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
The file was modifiedllvm/test/MC/AMDGPU/gfx11_err.s
The file was addedllvm/lib/Target/AMDGPU/LDSDIRInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Commit 3b390a1682232a0d6921692f72fac65ec4374597 by mats.petersson
[flang][OpenMP] Support for Collapse

Convert Fortran parse-tree into MLIR for collapse-clause.

Includes simple Fortran to LLVM-IR test, with auto-generated
check-lines (some of which have been edited by hand).

Reviewed By: kiranchandramohan, shraiysh, peixin

Differential Revision: https://reviews.llvm.org/D125302
The file was modifiedflang/include/flang/Lower/OpenMP.h
The file was modifiedflang/lib/Lower/Bridge.cpp
The file was modifiedflang/lib/Lower/OpenMP.cpp
The file was addedflang/test/Lower/OpenMP/omp-wsloop-collapse.f90
Commit e601b2a1542710789395ab1121b1ccc7076e39d1 by andrzej.warzynski
[flang][driver] Add support for generating executables on MacOSX/Darwin

This patch basically extends https://reviews.llvm.org/D122008 with
support for MacOSX/Darwin.

To facilitate this, I've added `MacOSX` to the list of supported OSes in
Target.cpp. Flang already supports `Darwin` and it doesn't really do
anything OS-specific there (it could probably safely skip checking the
OS for now).

Note that generating executables remains hidden behind the
`-flang-experimental-exec` flag. Also, we don't need to add `-lm` on
MacOSX as `libm` is effectively included in `libSystem` (which is linked
in unconditionally).

Differential Revision: https://reviews.llvm.org/D125628
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
The file was modifiedflang/lib/Optimizer/CodeGen/Target.cpp
The file was modifiedflang/test/Driver/linker-flags.f90
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.h
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
Commit fa7ce8e685faa63f7ad1d0c7a640217286ec291b by Louis Dionne
[runtimes] Fix the build of merged ABI/unwinder libraries

Also, add a CI job that tests this configuration. The exact configuration
is that we build a shared libc++ and merge objects for the ABI library
and the unwinder library into it.

Differential Revision: https://reviews.llvm.org/D125903
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibcxxabi/src/CMakeLists.txt
The file was modifiedlibcxx/utils/ci/run-buildbot
The file was addedlibunwind/test/configs/llvm-libunwind-merged.cfg.in
The file was modifiedlibcxx/CMakeLists.txt
The file was addedlibcxxabi/test/configs/llvm-libc++abi-merged.cfg.in
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/src/CMakeLists.txt
The file was addedlibcxx/cmake/caches/Generic-merged.cmake
Commit ac2ff258d69bfc70d92391c26be2b38a0a72ab74 by Joseph.Nash
[AMDGPU] gfx11 scalar memory instructions

Contributors:
Mirko Brkusanin <Mirko.Brkusanin@amd.com>

Patch 9/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125820

Reviewed By: kosarev, #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125822
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_smem.s
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s
Commit a5f36259a20533d9c970ab6a5faab7cf341ca1c9 by Louis Dionne
[libunwind] Remove unused _LIBUNWIND_HAS_NO_THREADS macro in tests

The _LIBUNWIND_HAS_NO_THREADS macro is only picked up by libunwind
inside its sources, so it is only required when it builds. It doesn't
need to be defined when running the tests.
The file was modifiedlibunwind/test/configs/llvm-libunwind-static.cfg.in
The file was modifiedlibunwind/test/configs/llvm-libunwind-shared.cfg.in
The file was modifiedlibunwind/test/configs/llvm-libunwind-merged.cfg.in
Commit a094ad03f341427af6578661fbe19181f032795a by apostolakis
[NFC] Fix typos in X86CmovConversion
The file was modifiedllvm/lib/Target/X86/X86CmovConversion.cpp
Commit 4431e8c84e6290b6b6f28d471f7584f0d9ccbb7b by Louis Dionne
[libc++] Override the value of LIBCXX_CXX_ABI in the cache

This will allow us to remove this entirely once the commit has propagated
through all CI and hence changed the value in the cache.
The file was modifiedlibcxx/CMakeLists.txt
Commit df56fb44f5495a660ffd369355f1b7d9c5144232 by flo
[VPlan] Update VPWidenMemoryInstruction to not inherit from VPValue.

VPWidenMemoryInstruction also models stores which may not produce a value.
This can trip over analyses. Improve the modeling by only adding
VPValues for VPWidenMemoryInstructionRecipes modeling loads.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 94a2bd5a270bca1c539a71d0e1ca88c02a023ebd by chenmindong1
[LoopVectorize] Precommit a test for D122126
The file was addedllvm/test/Transforms/LoopVectorize/PowerPC/interleaved-pointer-runtime-check-unprofitable.ll
Commit 3ed9f603fd59cafe3ab864d8bb77349ed418d384 by chenmindong1
[LoopVectorize] Don't interleave when the number of runtime checks exceeds the threshold

The runtime check threshold should also restrict interleave count.
Otherwise, too many runtime checks will be generated for some cases.

Reviewed By: fhahn, dmgreen

Differential Revision: https://reviews.llvm.org/D122126
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/interleaved-pointer-runtime-check-unprofitable.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit cefe472c51fbcd1aed4d4a090709f25a12a8bc2c by Yaxun.Liu
[clang] Fix __has_builtin

Fix __has_builtin to return 1 only if the requested target features
of a builtin are enabled by refactoring the code for checking
required target features of a builtin and use it in evaluation
of __has_builtin.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D125829
The file was addedclang/lib/Basic/BuiltinTargetFeatures.h
The file was addedclang/test/Preprocessor/hash_builtin.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/Basic/Builtins.cpp
The file was modifiedclang/lib/Lex/PPMacroExpansion.cpp
The file was modifiedclang/unittests/CodeGen/CheckTargetFeaturesTest.cpp
The file was modifiedclang/include/clang/Basic/Builtins.h
The file was modifiedclang/test/Preprocessor/feature_tests.c
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
Commit a136a00eae065d48cc4872d848d452ac31768c72 by david.spickett
[lldb] Add non-address bit improvements to release notes

This summarises the changes made by d9398a91e2a6b8837a47a5fda2164c9160e86199.
Which forms the bulk of the fixes needed for non-address bit handling.

Note that in the previous releases we noted memory tagging support,
which is a subset of non-address bits. The recent changes enable
debugging of programs using memory tagging, pointer authentication
and top byte ignore (all at once) on AArch64.
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit d14f2a6359483730657b275d40822d1098e3ff51 by jay.foad
[AMDGPU] Allow multiple uses of the same literal in SOP2/SOPC

AMDGPUAsmParser::validateSOPLiteral already knew about this but
SIInstrInfo::verifyInstruction did not.

Differential Revision: https://reviews.llvm.org/D125976