Changes

Enabling ccache for all ppc64 buildbots

This changed turns on the cmake variable that makes buildbots
build with ccache. Its intent is to use ccache to improve the
build times of the PowerPC 64-bit Big Endian buildbots.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D125890

Force HAVE_LIB_RT to NO when building with Xcode toolchains

Fixes an issue revealed by https://reviews.llvm.org/D121343, causing several of
the test-suite-verify-machineinstrs* bots on GreenDragon to fail with:

  ld: library not found for -lrt

rdar://91014785

Differential revision: https://reviews.llvm.org/D125275

cherry-pick 33c34454f1 from llvm-test-suite

Add new worker debian-tritium-mips64el for Linux 64-bit MIPS LE

This adds a new builder called debian-tritium-mips64el which
will build LLVM and Clang on Debian unstable on mips64el.

Differential revision: https://reviews.llvm.org/D125872

[lldb] Enable libcxx(abi) and compiler-rt as runtimes

[clang-tidy] Restore test parameter operator<< function (NFC)

Clang erroneously flagged the function as "unused", but it is most
definitely used by gtest to pretty print the parameter value when
a test fails.

Make the pretty printing function a friend function in the parameter
class similar to other clang unit tests.

[libc++] Simplify the string structures a bit more

This simplifies the string structs a bit more and the normal layout should not contain any undefined behaviour anymore. I don't think there is a way to achieve this in the alternate string mode without breaking the ABI.

Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D125496

[libc++][ranges][NFC] Mark completed issues related to the One Ranges Proposal.

Quite a few C++20 LWG issues/papers related to the One Ranges Proposal
were already effectively implemented (or contain semantic-only wording
changes that don't affect the implementation), mark them as such.

Differential Revision: https://reviews.llvm.org/D125065

[RISCV] Remove unneeded check for ISD::VSCALE operand being a constant. NFC

ISD::VSCALE only allows constant operands.

[mlir][LLVMIR] Add support for translating insert/extractvalue

Add support for translating llvm::InsertValue and llvm::ExtractValue.

Differential Revision: https://reviews.llvm.org/D125028

[mlir][LLVMIR] Add support for translating shufflevector

Add support for translating llvm::ShuffleVectorInst

Differential Revision: https://reviews.llvm.org/D125030

Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`

The name `MCFixedLenDisassembler.h` is out of date after D120958.

Rename it as `MCDecoderOps.h` to reflect the change.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D124987

[M68k][Disassembler] Adopt the new variable length decoder

This is an example usage of D120958.

After these patches are landed, we can strip off the codebeads officially.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D120960

[LowerTypeTests][clang] Implement and allow -fsanitize=cfi-icall for RISCV

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D106888

fix typos to cycle bots

[TargetLowering] expandCTPOP don't create an used constant mask for i8 ctpop. NFC

Use early out for the i8 case.

I'm looking at avoiding MUL on targets that use libcalls for MUL.
So doing a little pre-refactoring.

[libc++][test] Verify std::views::drop and std::views::join are CPOs

`std::views::drops` and `std::views::join` have been implemented, but the tests
verifying the CPOs for them are still commented out. Uncomment the tests.

Differential Revision: https://reviews.llvm.org/D125618

[clang-format] Handle "if consteval { ... }" for RemoveBracesLLVM

Differential Revision: https://reviews.llvm.org/D125593

ARMFixCortexA57AES1742098Pass.cpp: Suppress a warning. [-Wunused-but-set-variable]

[clang][docs] Add escape code to fix missing '*' in reduction operation list

ScalarEvolution.cpp: Reformat.

[X86] Adjust tests for vector widening to use freeze(poison)

I incorrectly used freeze(undef) in rG1b07bd9034bd

[X86] Add shuffles showing failure to use PERMUTE(BLEND(X,Y))

One AVX2+ targets we have a immediate VPERMQ/PD cross-lane permute thats better than relying on a pair of VPERM2F128 cross-lanes to feed a blend.

Reported on discourse

[X86] lowerV4I64Shuffle - try harder to lower to PERMQ(BLENDD(V1,V2)) pattern

[X86] Pull out repeated isShuffleMaskInputInPlace calls. NFC.

[VPlan] Improve printing of VPReplicateRecipe with calls.

Suggested as part of D124718.

[X86] lowerShuffleAsLanePermuteAndSHUFP always succeeds, so just return the result. NFC.

[X86] Add checks to illegal-insert.ll

[X86] Add test coverage for PR44915 / Issue #44260

[RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC

Add more i8/16 tets.
Add ctlz_zero_undef tests.

[RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC

ctpop and cttz default expansion both end up using a multiply. This
can either use a mul instruction or libcall. Make sure we test both
cases.

[SLP] Fix misspelling of 'analyzed'. NFC

[flang][nfc] Fix driver method names overridden by the plugins

After the recent re-factoring of the driver code
(https://reviews.llvm.org/D125007), `ExecuteAction` was renamed as
`executeAction`. This patch updates the examples in Flang accordingly.

If you set `FLANG_BUILD_EXAMPLES` to `On` when building Flang, then the
refactoring from D125007 would have caused build failures for you. This
patch fixes that.

This is fairly straightforward and fixes buildbot failures, so I'm
sending this without a review.

Revert "[libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE."

This reverts commit f6366ef7f4f3cf1182fd70e0c50a9fa54374b612.

[DWARFLinker][NFC] cleanup AddressManager interface.

this review is extracted from D86539

1. delete areRelocationsResolved() method.
2. rename hasLiveMemoryLocation() -> isLiveVariable()
          hasLiveAddressRange() -> isLiveSubprogram().

Differential Revision: https://reviews.llvm.org/D125492

[X86] Adjust fadd costs to match SoG

znver1/2 models were incorrectly modelling these on fpupipe 0 instead of 2/3 and znver1 ymm variants also require double pumping.

Now matches AMD SoG, Agner and instlatx64 numbers.

Thanks to @fabian-r for the report

[LV] Set SCEVCheckCond to nullptr whenever it was used.

Under some circumstances, SCEVExpander will insert new instructions when
expanding a predicate, but the final result of the expansion can be a
false constant.

In those cases, the expanded instructions may later be used by other
expansions, e.g. the trip count. This may trigger an assertion during
SCEVExpander cleanup. To avoid this, always mark the result as used.

Fixes #55100.

[X86] Move combineAddOrSubToADCOrSBB earlier. NFC.

Make it easier to reuse in X86 ADD/SUB combines in an upcoming patch.

[mlir][bufferize] Infer memref types when possible

Instead of recomputing memref types from tensor types, try to infer them when possible. This results in more precise layout maps.

Differential Revision: https://reviews.llvm.org/D125614

[RISCV] Fix incorrect use of tail agnostic vslideup.

We need to use tail undisturbed for vslideup to implement
vector insert operation correctly.

Ideally, we cound use the tail agnostic when insert subvector
or element at the end of the vector. This will be in follow-up
patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125545

[Diagnostic] Warn if the size argument of memset is character literal
zero

Closing https://github.com/llvm/llvm-project/issues/55402

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D125521

[RISCV][NFC] Replace for-each with array argument call.

This patch replaces some for-each set with the new arrayref argument API, since it already used an array in defination, I think this change won't cause any ambiguity.

Differential Revision: https://reviews.llvm.org/D125455

[LLVM][Casting.h] Add trivial self-cast

Casting from a type to itself should always be possible. Make this simple for all users, and add tests to ensure we keep being able to do this. Ref: https://reviews.llvm.org/D125543

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125590

[clang] Prevent folding of non-const compound expr

When a non-const compound statement is used to initialize a constexpr pointer,
the pointed value is not const itself and cannot be folded at codegen time.

This matches GCC behavior for compound literal expr arrays.

Fix issue #39324.

Differential Revision: https://reviews.llvm.org/D124038

[DivRemPairs][Mips] Pre-commit test for Mips target

Copied from PowerPC.

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D124979

[Mips] Implement hasDivRemOp()

SDIVREM and UDIVREM can be customized lowered in MipsSE.

Fix https://github.com/llvm/llvm-project/issues/54991.

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D124980

[gn build] Port 0a0d6489ef2e

[RISCV][NFC] Refactor RISC-V vector intrinsic utils.

This patch is preparation for D111617, use class/struct/enum rather than char/StringRef to present internal information as possible, that provide more compact way to store those info and also easier to serialize/deserialize.

And also that improve readability of the code, e.g. "v" vs TypeProfile::Vector.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D124730

[clang-format] Fix PointerAlignment: Right not working with tab indentation.

Fixes https://github.com/llvm/llvm-project/issues/55407.

Given configuration:
```
UseTab: Always
PointerAlignment: Right
AlignConsecutiveDeclarations: true
```

Before, the pointer was misaligned in this code:
```
void f() {
	unsigned long long big;
	char	      *ptr; // misaligned
	int		   i;
}
```

That was due to the fact that when handling right-aligned pointers, the Spaces were changed but StartOfTokenColumn was not.

Also, a tab was used not only for indentation but for spacing too when using `UseTab: ForIndentation` config option:
```
void f() {
	unsigned long long big;
	char	      *ptr; // \t after char
	int                i;
}
```

Reviewed By: owenpan

Differential Revision: https://reviews.llvm.org/D125528

[RISCV][NFC] Fix build issue

Add ThreadPriority::Low, and use QoS class Utility on Mac

On Apple Silicon Macs, using a Darwin thread priority of PRIO_DARWIN_BG seems to
map directly to the QoS class Background. With this priority, the thread is
confined to efficiency cores only, which makes background indexing take forever.

Introduce a new ThreadPriority "Low" that sits in the middle between Background
and Default, and maps to QoS class "Utility" on Mac. Make this new priority the
default for indexing. This makes the thread run on all cores, but still lowers
priority enough to keep the machine responsive, and not interfere with
user-initiated actions.

I didn't change the implementations for Windows and Linux; on these systems,
both ThreadPriority::Background and ThreadPriority::Low map to the same thread
priority. This could be changed as a followup (e.g. by using SCHED_BATCH for Low
on Linux).

See also https://github.com/clangd/clangd/issues/1119.

Reviewed By: sammccall, dgoldman

Differential Revision: https://reviews.llvm.org/D124715

[clangd] Include Cleaner: ignore headers with IWYU export pragmas

Disable the warnings with `IWYU pragma: export` or `begin_exports` +
`end_exports` until we have support for these pragmas. There are too many
false-positive warnings for the headers that have the correct pragmas for now
and it makes the user experience very unpleasant.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D125468

[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors

When the loop vectoriser encounters a known low trip count it tries
to create a single predicated loop in order to get the benefit of
vectorisation and eliminate the scalar tail. However, until now the
vectoriser prevented the use of scalable vectors in this case due
to concerns in the past about stability. I believe that tail-folded
loops using scalable vectors are now sufficiently well tested that
we can enable this. For the same reason I've also enabled it when
optimising for code size too.

Tests added here:

  Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
  Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
  Transforms/LoopVectorize/RISCV/low-trip-count.ll

Differential Revision: https://reviews.llvm.org/D121595

[clangd] NFC: Rename field to be compatible with the function name

[clang-format] fix alignment w/o binpacked args

The combination of

- AlignConsecutiveAssignments.Enabled = true
- BinPackArguments = false

would result in the first continuation line of a braced-init-list being
improperly indented (missing a shift) when in a continued function call.
Indentation was also wrong for braced-init-lists continuing a
direct-list-initialization.  Check for opening braced lists in
continuation and ensure that the correct shift occurs.

Fixes https://github.com/llvm/llvm-project/issues/55360

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D125162

[FastISel] Fix load folding for registers with fixups

FastISel tries to fold loads into the single using instruction.
However, if the register has fixups, then there may be additional
uses through an alias of the register.

In particular, this fixes the problem reported at
https://reviews.llvm.org/D119432#3507087. The load register is
(at the time of load folding) only used in a single call instruction.
However, selection of the bitcast has added a fixup between the
load register and the cross-BB register of the bitcast result.
After fixups are applied, there would now be two uses of the load
register, so load folding is not legal.

Differential Revision: https://reviews.llvm.org/D125459

[flang] Install Fortran_main library

At the moment the Fortran_main library is not installed, so it cannot be
found by the driver when run from an install directory. This patch fixes
the issue by replacing llvm_add_library with add_flang_library, which
already contains all the proper incantations for installing a library.
It also enhances add_flang_library to support a STATIC arg which forces
the library to be static even when BUILD_SHARED_LIBS is on.

Differential Revision: https://reviews.llvm.org/D124759

Co-authored-by: Dan Palermo <Dan.Palermo@amd.com>

[ControlHeightReduction] Freeze condition when converting select to branch

While select conditions can be poison, branch on poison is
immediate UB. As such, we need to freeze the condition when
converting a select into a branch.

Differential Revision: https://reviews.llvm.org/D125398

[pseudo] Support parsing variant target symbols.

With this patch, we're able to parse smaller chunks of C++ code (statement,
declaration), rather than translation-unit.

The start symbol is listed in the grammar in a form of `_ :=
statement`, each start symbol has a dedicated state (`_ := • statement`).
We create and track all these separate states in the LRTable. When we
start parsing, we lookup the corresponding state to start the parser.

LR pasing table changes with this patch:
- number of states: 1467 -> 1471
- number of actions: 82891 -> 83578
- size of the table (bytes): 334248 -> 336996

Differential Revision: https://reviews.llvm.org/D125006

[AMDGPU] Extract SIInstrInfo::removeModOperands. NFC.

Make this an externally callable function for use in a future patch.

Differential Revision: https://reviews.llvm.org/D125565

[AMDGPU] SIShrinkInstructions: change static functions to methods

This is a mechanical change to avoid passing MRI and TII around
explicitly. NFC.

Differential Revision: https://reviews.llvm.org/D125566

[llvm-c] Add functions for enabling and creating opaque pointers

This is based on https://reviews.llvm.org/D125168 which adds a
wrapper to allow use of opaque pointers from the C API.

I added an opaque pointer mode test to echo.ll, and to fix assertions
that forbid the use of mixed typed and opaque pointers that were
triggering in it I had to also add wrappers for setOpaquePointers()
and isOpaquePointer().

I also changed echo.ll to remove a bitcast i32* %x to i8*, because
passing it through llvm-as and llvm-dis was generating a
%0 = bitcast ptr %x to ptr, but when building that same bitcast in
echo.cpp it was getting elided by IRBuilderBase::CreateCast
(https://github.com/llvm/llvm-project/blob/08ac66124874d70dab63c731da0244f9e29ef168/llvm/include/llvm/IR/IRBuilder.h#L1998-L1999).

Differential Revision: https://reviews.llvm.org/D125183

[clangd] parse all make_unique-like functions in preamble

I am working on support for forwarding parameter names in make_unique-like functions, first for inlay hints, later maybe for signature help.
For that to work generically, I'd like to parse all of these functions in the preamble. Not sure how this impacts performance on large codebases though.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D124688

[clang-format][NFC] Don't call mightFitOnOneLine() unnecessarily

Clean up UnwrappedLineParser for RemoveBracesLLVM to avoid calling
mightFitOnOneLine() as much as possible.

Differential Revision: https://reviews.llvm.org/D125626

[StatepointLowering] Properly handle local and non-local relocates of the same value.

FunctionLoweringInfo::StatepointRelocationMaps map is used to pass GC pointer
lowering information from statepoint to gc.relocate  which may appear ini
different block.
D124444 introduced different lowering for local and non-local relocates.
Local relocates use SDValue and non-local relocates use value exported to VReg.
But I overlooked the fact that StatepointRelocationMap is indexed not by
GCRelocate instruction, but by derived pointer. This works incorrectly when
we have two relocates (one local and another non-local) of the same value,
because they need different relocation records.

This patch fixes the problem by recording relocation information per relocate
instruction, not per derived pointer. This way, each gc.relocate can be lowered
differently.

Reviewed By: skatkov

Differential Revision: https://reviews.llvm.org/D125538

[AArch64] Handle 64bit vectors in tryCombineFixedPointConvert

Under some situations we can visit 64bit vector extract elements in
tryCombineFixedPointConvert, where an assert fires as they are expected
to have been converted to 128bit. Turn the assert into an if statement,
bailing out and letting the extract be handled first.

Also invert some ifs, using early exits to reduce indentation.

Fixes #55417

[SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags.

The patch make users not need to know getNode with SDNodeFlags argument may not
pass its flags.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125659

[X86][AVX] Add test showing poor expansion of bit-reversal permutation shuffles

Reported here: https://discourse.llvm.org/t/ir-alternatives-to-freeze-to-selectively-prevent-compiler-from-combining-shufflevectors/62521

[AMDGPU][GlobalISel] Pre-commit tests for D125516

Differential Revision: https://reviews.llvm.org/D125539

[GlobalISel] Handle constant splat in funnel shift combine

This change adds the constant splat versions of m_ICst() (by using
getBuildVectorConstantSplat()) and uses it in
matchOrShiftToFunnelShift(). The getBuildVectorConstantSplat() name is
shortened to getIConstantSplatVal() so that the *SExtVal() version would
have a more compact name.

Differential Revision: https://reviews.llvm.org/D125516

[ADT] Adopt the new casting infrastructure for PointerUnion

Reviewed By: lattner, bzcheeseman

Differential Revision: https://reviews.llvm.org/D125609

[lldb][NFC] Make cmd a reference in GenerateOptionUsage

Nowhere in lldb do we call this with a null pointer.
If we did, the first line of the function would fault anyway.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D125218

[lldb][NFC] Simplify GenerateOptionUsage

Once we get into the if block we know the value of only_print_args.
Move some variables closer to point of use.

Depends on D125218

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D125219

AArch64: support ISel for fence instructions

Only the most conservative of the DAG patterns matched, leaving GISel with "dmb
ish" everywhere which is inefficient.

[DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine

Differential Revision: https://reviews.llvm.org/D125367

[InstCombine] Combine instructions of type or/and where AND masks can be combined.

The patch simplifies some of the patterns as below

(A | (B & C0)) | (B & C1) -> A | (B & C0|C1)
((B & C0) | A) | (B & C1) -> (B & C0|C1) | A

In some scenarios like byte reverse on half word, we can see this pattern multiple times and this conversion can optimize these patterns.

Differential Revision: https://reviews.llvm.org/D124119

[AST] Cleanup on getting the underlying decl of using-shdow decl.

This should be a NFC cleanup. It removes a unnecessary loop to get the underlying
decl, and add an assertion.

The underlying decl of a using-shadow decl is always the original declaration
has been brought into the scope, clang never builds a nested using-shadow
decl (see Sema::BuildUsingShadowDecl).

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D123422

[clang][NFC] Cleanup some coroutine tests

I noticed these two tests emit a warning about a missing
unhandled_exception.  That's irrelevant to what is being tested, but
is unnecessary noise.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D125535

[runtimes] Introduce object libraries

This is a variant of D116689 rebased on top of the new (proposed) ABI
refactoring in D120727. It should conserve the basic properties of the
original patch by @phosek, except it also allows cleaning up the merging
of libc++abi into libc++ from the libc++ side.

Differential Revision: https://reviews.llvm.org/D125393

[RISCV] remove useless code

When legality check for vectoring reduction， hasVInstructions() check be unneeded. RISCV can only loop vectorization with hasVInstructions()

Reviewed By: kito-cheng, craig.topper

Differential Revision: https://reviews.llvm.org/D125460

[runtimes] Generalize how we reorder projects

This way, we could use it for LLVM_ENABLE_PROJECTS too if desired.

Differential Revision: https://reviews.llvm.org/D125121

[CodeGen] Use ArrayRef in TargetLowering functions

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123656

[clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVisitors

Reimplement the matching logic using Visitors instead of matchers.

Benchmarks from running the check over SemaCodeComplete.cpp
Before 0.20s, After 0.04s

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D125026

Apply clang-tidy fixes for performance-move-const-arg in SerializeToHsaco.cpp (NFC)

Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cpp (NFC)

[MSVC] Add support for pragma alloc_text

`#pragma alloc_text` is a MSVC pragma that names the code section where functions should be placed. It only
applies to functions with C linkage.

https://docs.microsoft.com/en-us/cpp/preprocessor/alloc-text?view=msvc-170

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D125011

[AMDGPU] gfx11 BUF Instructions

Includes MachineCode layer support and tests, and MIR tests not requiring
CodeGen pass changes.
Includes a small change in SMInstructions.td to correct encoded bits.

Contributors:
Petar Avramovic <Petar.Avramovic@amd.com>
Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>

Depends on D125316

Patch 6/N for upstreaming of AMDGPU gfx11 architecture.

Reviewed By: dp, Petar.Avramovic

Differential Revision: https://reviews.llvm.org/D125319

[ConstantRange] Add toKnownBits() method

Add toKnownBits() method to mirror fromKnownBits(). We know the
top bits that are constant between min and max.

The return value for an empty range is chosen to be conservative.

[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10

On GFX10 VOP3 instructions can have a literal operand, so the conversion
from VOP3 MAD/FMA to VOP2 MADAK/MADMK/FMAAK/FMAMK will not happen in
SIFoldOperands. The only benefit of the VOP2 form is code size, so do it
in SIShrinkInstructions instead.

Differential Revision: https://reviews.llvm.org/D125567

[AMDGPU] Mark sendmsg hasSideEffects. NFC

Address the FIXME by marking the sendmsg instructions with
hasSideEffects.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D125569

[LAA,LV] Add initial support for pointer-diff memory checks.

This patch adds initial support for a pointer diff based runtime check
scheme for vectorization. This scheme requires fewer computations and
checks than the existing full overlap checking, if it is applicable.

The main idea is to only check if source and sink of a dependency are
far enough apart so the accesses won't overlap in the vector loop. To do
so, it is sufficient to compute the difference and compare it to the
`VF * UF * AccessSize`. It is sufficient to check
`(Sink - Src) <u VF * UF * AccessSize` to rule out a backwards
dependence in the vector loop with the given VF and UF. If Src >=u Sink,
there is not dependence preventing vectorization, hence the overflow
should not matter and using the ULT should be sufficient.

Note that the initial version is restricted in multiple ways:

1. Pointers must only either be read or written, by a single
   instruction (this allows re-constructing source/sink for
   dependences with the available information)
 2. Source and sink pointers must be add-recs, with matching steps
 3. The step must be a constant.
 3. abs(step) == AccessSize.

Most of those restrictions can be relaxed in the future.

See https://github.com/llvm/llvm-project/issues/53590.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D119078

[ValueTracking] Handle and/or on RHS of isImpliedCondition()

isImpliedCondition() currently handles and/or on the LHS, but not
on the RHS, resulting in asymmetric behavior. This patch adds two
new implication rules:

 * LHS ==> (RHS1 || RHS2) if LHS ==> RHS1 or LHS ==> RHS2
 * LHS ==> !(RHS1 && RHS2) if LHS ==> !RHS1 or LHS ==> !RHS2

Differential Revision: https://reviews.llvm.org/D125551

[SLP]Check if the root of the buildvector has one use only.

The root of the buildvector can have only one use, otherwise it can be
treated only as a final element of the previous buildvector sequence.

[InstCombine] fix test name; NFC

The bug number was typo'd when it was added for D86243.

[PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC

The tests (see C++ source in #54692) have multiple potential
optimizations/canonicalizations, but we should be consistent
since they are logically identical.

[AArch64] Update check lines in arm64-scvt.ll. NFC

[polly] Remove 'using namespace llvm/polly' from ScopGraphPrinter.h header.

As mentioned on D123678 this appears to be causing namespace resolution issues on some versions of gcc.

[LiveIntervals] Add range accessors for value numbers [nfc]

[IR] create and use helper functions that test the signbit; NFCI

[InstrProf][NFC] Save profile bias to function map

Add a map from functions to load instructions that compute the profile bias. Previously we assumed that if the first instruction in the function was a load instruction, then it must be computing the bias. This was likely to work out because functions usually start with the `llvm.instrprof.increment` instruction, but optimizations could change this. For example, inlining into a non-profiled function.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D114319

[mlir][bufferize] Better user control of layout maps

This changes replaces the `fully-dynamic-layout-maps` options (which was badly named) with two new options:

* `unknown-type-conversion` controls the layout maps on buffer types for which no layout map can be inferred.
* `function-boundary-type-conversion` controls the layout maps on buffer types inside of function signatures.

Differential Revision: https://reviews.llvm.org/D125615

[llvm-profgen] Update callsite body samples by summing up all call target samples.

Current profile generation caculcates callsite body samples and call target samples separately. The former is done based on LBR range samples while the latter is done based on branch samples. Note that there's a subtle difference. LBR ranges is formed from two consecutive branch samples. Therefore the last entry in a LBR record will not be counted towards body samples while there's still a chance for it to be counted towards call targets if it is a function call. I'm making sense of the call body samples by updating it to the aggregation of call targets.

Reviewed By: wenlei

Differential Revision: https://reviews.llvm.org/D122609

[RISCV] Add further trace output to InsertVSETLVI

[DAGCombiner] Fix incorrect indentation. NFC

[TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift.

If we use multiply it would be with 0x0101 which is 1 more than a power
of 2. On some targets we would expand this to shl+add. By avoiding the
multiply earlier, we can generate better code.

Note, PowerPC doesn't do the shl+add expansion of multiply so one of
the tests increased in instruction count.

Limiting to scalars because it almost always increased the number of
instructions in vector tests.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D125638

[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

This bug is in generic DAG combine and easily reproducible on many
targets.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D125640

[InstCombine] add tests for zext-of-signbit test; NFC

[InstCombine] invert canonicalization for cast of signbit test

The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.

[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32

There have been some patterns in the AArch64 backend to optimize code of
the form:
  ldrsh w8, [x0]
  scvtf s0, w8
to:
  ldr h0, [x0]
  sshll v0.4s, v0.4h, #0
  scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.

This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.

Differential Revision: https://reviews.llvm.org/D125470

Remove stale file from modulemap

[llvm-objdump] Let --symbolize-operands symbolize basic block addresses based on the SHT_LLVM_BB_ADDR_MAP section.

`--symbolize-operands` already symbolizes branch targets based on the disassembly. When the object file is created with `-fbasic-block-sections=labels` (ELF-only) it will include a SHT_LLVM_BB_ADDR_MAP section which maps basic blocks to their addresses. In such case `llvm-objdump` can annotate the disassembly based on labels inferred on this section.

In contrast to the current labels, SHT_LLVM_BB_ADDR_MAP-based labels are created for every machine basic block including empty blocks and those which are not branched into (fallthrough blocks).

The old logic is still executed even when the SHT_LLVM_BB_ADDR_MAP section is present to handle functions which have not been received an entry in this section.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D124560

[docs] Re-generate ClangCommandLineReference.rst

[Driver] Change "zlib not installed" diagnostic to "zlib not enabled"

The former is a bit misleading and a user may try installing zlib which
will not help.

[mlir:toy][NFC] Remove unnecessary trailing return type

In this instance, the trailing return type does not improve readability
as it repeats what is returned in the same line.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125697

[WebAssembly][TableGen][NFCI] Use getValueAsBit rather than converting TableGen 'bit' to string

The logic around IsCanonical previously used getAsString and compared to
"1". Just using getValueAsBit is simpler.

Add documentHighlight in clangd check for performance measurements.

Differential Revision: https://reviews.llvm.org/D125682

[AMDGPU] Revert wide LDS DMA support.

This reverts ffbee7acdcaaf, see also bug 37653 which it was fixing.
The bug claims this is an undocumented feature which actually works.
In the reality it is documented as not working for a good reason.
It likely does something, but it is useless anyway. These instructions
write into the LDS. The LDS address is:

M0 + inst_offset + (TIDinWave * 4).

For a store wider than a DWORD neighboring lanes will overwrite each
other.

Differential Revision: https://reviews.llvm.org/D125409

[AIX] fixed llvm-ar can not read empty big archive correctly.

Summary:

llvm-ar can not read empty big archive correctly. it output error as
error: unable to load 'empty.a': truncated or malformed archive (characters in size field in archive member header are not all decimal numbers: '<bigaf>'

Reviewers: James Henderson
Differential Revision: https://reviews.llvm.org/D124017

[mlir][tosa] Use math.ctlz intrinsic for tosa.clz

We were custom counting per bit for the clz instruction. Math dialect
now has an intrinsic to do this in one instruction. Migrated to this
instruction and fixed a minor bug math-to-llvm for the intrinsic.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D125592

Optimise findRefs for XRefs and docHighlights

Reduces time spent in findRef by 66%.

Differential Revision: https://reviews.llvm.org/D125675

[sanitizer] Don't use newfstatat for Linux on SPARC

Linux on SPARC uses fstatat64 instead.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D125572

[libc++] Remove the legacy LIBCXX_LIBCPPABI_VERSION option

I think this notion of libc++abi's version was relevant a long time ago
on Apple platforms when we were using a Xcode project to build the library.
As part of moving Apple's build to CMake, D59489 made it possible to
specify the "ABI version" of libc++abi in use. However, it's not possible
to build libc++abi with that old ABI anymore and we don't need the ability
to link against that version from libc++ anymore.

Hence, we can clean this up and stop falsely pretending that libc++abi
has more than one ABI version.

Differential Revision: https://reviews.llvm.org/D125687

[libc++] Remove overly conservative error in <stdatomic.h>

As mentionned in D97044, it is fine if users include <atomic> and then
include <stdatomic.h> -- we don't need to error out for that case.

Differential Revision: https://reviews.llvm.org/D125579

[SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes.

During early gather/scatter enablement two different approaches
were taken to represent scaled indices:

* A Scale operand whereby byte_offsets = Index * Scale
* An IndexType whereby byte_offsets = Index * sizeof(MemVT.ElementType)

Having multiple representations is bad as shown by this patch which
fixes instances where the two are out of sync. The dedicated scale
operand is more flexible and pervasive so this patch removes the
UNSCALED values from IndexType. This means all indices are scaled
but the scale can be one, hence unscaled. SDNodes now use the scale
operand to answer the "isScaledIndex" question.

I toyed with the idea of keeping the UNSCALED enums and helper
functions but because they will have no uses and force SDNodes to
validate the set of supported values I figured it's best to remove
them. We can re-add them if there's a real need. For similar
reasons I've kept the IndexType enum when a bool could be used as I
think being explicitly looks better.

Depends On D123347

Differential Revision: https://reviews.llvm.org/D123381

[DomPrinter] Migrate -dot-dom to the new pass manager.

In D123677, @YangKeao provided an implementation of `DOTGraphTraits{Viewer,Printer}` in the new pass manager. This commit migrates the `DomPrinter` and `DomViewer` to the new pass manager.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D124904

[mlir][sparse] introduce complex type to sparse tensor support

This is the first implementation of complex (f64 and f32) support
in the sparse compiler, with complex add/mul as first operations.
Note that various features are still TBD, such as other ops, and
reading in complex values from file. Also, note that the
std::complex<float> had a bit of an ABI issue when passed as
single argument. It is still TBD if better solutions are possible.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D125596

[mlir][ods] Ignore AttributeSelfTypeParameter in assembly formats

The attribute self type parameter is currently treated like any other attribute parameter in the assembly format. The self type parameter should be handled by the operation parser and printer and play no role in the generated parsers and printers of attributes.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125724

[AIX] llvm-link support big archive.

Summary:
Use object::Archive::create so that the returned archive object has a dynamic type of either Archive or BigArchive.

Reviewers: James Henderson,Fangrui Song
Differential Revision: https://reviews.llvm.org/D124940

[mlir][transforms] Add a topological sort utility and pass

This patch adds a topological sort utility and pass. A topological sort reorders
the operations in a block without SSA dominance such that, as much as possible,
users of values come after their producers.

The utility function sorts topologically the operation range in a given block
with an optional user-provided callback that can be used to virtually break cycles.
The toposort pass itself recursively sorts graph regions under the target op.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D125063

[mlir] Remove the `type` keyword from type alias definitions

This was carry over from LLVM IR where the alias definition can
be ambiguous, but MLIR type aliases have no such problems.
Having the `type` keyword is superfluous and doesn't add anything.
This commit drops it, which also nicely aligns with the syntax for
attribute aliases (which doesn't have a keyword).

Differential Revision: https://reviews.llvm.org/D125501

[mlir][ods] Fix verification of attribute + colon type ambiguity

An attribute without a type builder followed by a colon in an assembly format is potentially ambiguous because the parser will read ahead to parse the colon-type and pass this as the type argument to the attribute's constructor.

However, the previous verifier that checks for this ambiguity erroneously produces an error in the case of

```
let assemblyFormat = "( `(` $attr `)` )? `:`";
```

This patch fixes the bug by implementing a checker that correctly handles all edge cases, including very strange assembly formats like:

```
let assemblyFormat = "( `(` $attr ) : (`>`)? attr-dict (`>` $a^) : (`<`)? `:`";
```

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125445

[mlir][bufferize] Better propagation of errors

Return immediately when an op bufferization patterns fails.

Differential Revision: https://reviews.llvm.org/D125087

[InstrProf] Fix promoter when using counter relocations

When using counter relocations, two instructions are emitted to compute
the address of the counter variable.

```
%BiasAdd = add i64 ptrtoint <__profc_>, <__llvm_profile_counter_bias>
%Addr = inttoptr i64 %BiasAdd to i64*
```

When promoting a counter, these instructions might not be available in
the block, so we need to copy these instructions.

This fixes https://github.com/llvm/llvm-project/issues/55125

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125710

[AArch64] Use ADDV for boolean xor reductions.

NEON does not have native support for xor reductions. However, when
reducing predicate vectors the operation is synonymous with an add
reduction that is supported.

Differential Revision: https://reviews.llvm.org/D125605

[compiler-rt builtins] Assert that atomic.c can be compiled correctly.

The spinlock requires that lock-free operations are available;
otherwise, the implementation just calls itself. As discussed in
D120026.

Differential Revision: https://reviews.llvm.org/D123080

[ARM] Rename the isARMAreaXRegister parameter isIOS to SplitFramePushPop. NFC.

In f8b0a7af52f8c4ec6b4ddcfe3a6fa75098c9507c in 2016, this parameter
was generalized on the caller side (previously passing
STI.isTargetMachO(), now passing STI.splitFramePushPop()). Rename
the parameter on the receiver side to match the generalization.

Differential Revision: https://reviews.llvm.org/D125681

[MC] [Win64EH] Try writing an ARM64 "packed epilog" even if the epilog doesn't share opcodes with the prolog

The "packed epilog" form only implies that the epilog is located
exactly at the end of the function (so the location of the epilog
is implicit from the epilog opcodes), but it doesn't have to share
opcodes with the prolog - as long as the total number of opcode
bytes and the offset to the epilog fit within the bitfields.

This avoids writing a 4 byte epilog scope in many cases. (I haven't
measured how much this shrinks actual xdata sections in practice
though.)

Differential Revision: https://reviews.llvm.org/D125536

[MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64

This allows sharing opcodes between prolog and epilog even when there
is more than one epilog.

I didn't make any handcrafted special MC level testcases for this (yet
at least), but it does seem to have the expected effect on two existing
CodeGen level testcases.

Differential Revision: https://reviews.llvm.org/D125619

Revert "[InstCombine] invert canonicalization for cast of signbit test"

This reverts commit 3794cc0e996481e10307b67c8436aa44e0d65d22.
This change is suspected of causing bots to hang at stage 2
compiles, so reverting to confirm and investigate.

[lldb] Prevent underflow in crashlog.py

Avoid a OverflowError (an underflow really) when the pc is zero. This
can happen for "unknown frames" where the crashlog generator reports a
zero pc. We could omit them altogether, but if they're part of the
crashlog it seems fair to display them in lldb as well.

rdar://92686666

Differential revision: https://reviews.llvm.org/D125716

[mlir] allow for re-registering extension ops

Op registration mechanism does not allow for ops with the same name to be
re-registered. This is okay to avoid name conflicts and debug
double-registration, but may be problematic for dialect extensions that may get
registered several times (unlike dialects that are deduplicated in the
registry). When registering ops through the Transform dialect extension
mechanism, check first if the ops are already registered and only complain in
the case of repeated registration with the same name but different TypeID.

Differential Revision: https://reviews.llvm.org/D125554

[Libomptarget] Don't build the device runtime without a new Clang

The OpenMP device offloading library is a bitcode library and thus only
expect to build and linked with the same version of clang that was used
to create it. This somewhat copmlicates the building process as we
require the Clang that was just built to be used to create the library.
This is either done with a two-step build, where OpenMP is built with
the Clang that was just installed, or through the
`-DLLLVM_ENABLE_RUNTIMES=openmp` option. This has always been the case,
but recent changes have caused this to make it difficult to build the
rest of OpenMP. This patchs adds a check to not build the OpenMP device
runtime if the current compiler is not Clang with the same version as
the LLVM installation. This should allow users to build OpenMP as a
project using any compiler without it erroring out due to the bitcode
library, but if users require it they will need to use the above methods
to compile it.

Reviewed By: jdoerfert, tianshilei1992, ye-luo

Differential Revision: https://reviews.llvm.org/D125698

[OpenMP] Don't build the offloading driver without a source input

The Clang driver additional stages to build a complete offloading
program for applications using CUDA or OpenMP offloading. This normally
requires either a source file input or a valid object file to be
handled. This would cause problems when trying to compile an assembly or
LLVM IR file through clang with flags that would enable offloading. This
patch simply adds a check to prevent the offloading toolchain from being
used if we don't have a valid source file.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D125705

[NFC] Don't bother with unstripped binary w/ dSYM, don't DebugSymbols twice

This patch addresses two perf issues when we find a dSYM on macOS
after calling into the DebugSymbols framework.  First, when we have
a local (probably stripped) binaary, we find the dSYM and we may
be told about the location of the symbol rich binary (probably
unstripped) which may be on a remote filesystem.  We don't need the
unstripped binary, use the local binary we already have.
Second, after we've found the path to the dSYM, save that in the Module
so we don't call into DebugSymbols a second time later on to
rediscover it.  If the user has a DBGShellCommands set, we need to
exec that process twice, serially, which can add up.

Differential Revision: https://reviews.llvm.org/D125616
rdar://84576917

[mlir] Restrict dialect doc gen to a single dialect

In the overwhelmingly majority of cases only one dialect is generated at a time
anyways, and this restriction more easily catches user error when multiple
dialects might be generated. We hit this semi-recently with the PDL dialect,
and circt+other downstream users are also actively hitting this as well.

Differential Revision: https://reviews.llvm.org/D125651

[mlir][sparse] Enhancing sparse=>sparse conversion.

Fixes: https://github.com/llvm/llvm-project/issues/51652

Depends On D122060

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D122061

[mlir][sparse] Adding "final" keyword wherever appropriate

This enables the compiler to perform devirtualization.  And benchmarks
indicate devirtualization can sometimes give considerable speedup.

Depends On D122061

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125428

[clang] Avoid suggesting typoed directives in `.S` files

This patch is itended to avoid suggesting typoed directives in `.S`
files to support the cases of `#` directives treated as comments or
various pseudo-ops. The feature is implemented in
https://reviews.llvm.org/D124726.

Fixes: https://reviews.llvm.org/D124726#3516346.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D125727

[mlir][Tablegen-LSP] Add support for a basic TableGen language server

This follows the same general structure of the MLIR and PDLL language
servers. This commits adds the basic functionality for setting up the server,
and initially only supports providing diagnostics. Followon commits will
build out more comprehensive behavior.

Realistically this should eventually live in llvm/, but building in MLIR is an easier
initial step given that:
* All of the necessary LSP functionality is already here
* It allows for proving out useful language features (e.g. compilation databases)
  without affecting wider scale tablegen users
* MLIR has a vscode extension that can immediately take advantage of it

Differential Revision: https://reviews.llvm.org/D125440

[llvm-objcopy][test] Add cmp after copy

All of the other tests here either check that the copy fails, or that
the resulting binary is the same, it seems like this check was omitted
for the universal object case.

Differential Revision: https://reviews.llvm.org/D125478

[mlir][NFC] Fix a few langref typos

[llvm-ar][NFC] Address post-commit comments on D125439.

Remove errant whitespace.

AIX uses big archive format so check for both !<arch> and <bigaf>.

Only the "gnu" format has thin archives; specify --format=gnu for
thin archive test-cases.

Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)

The existing redundant copy elimination required a virtual register source, but the same logic works for any physreg where we don't have to worry about clobbers.  On RISCV, this helps eliminate redundant CSR reads from VLENB.

Differential Revision: https://reviews.llvm.org/D125564

[mlir][sparse] Restyling macros in the runtime library

In addition to reducing code repetition, this also helps ensure that the various API functions follow the naming convention of mlir::sparse_tensor::primaryTypeFunctionSuffix (e.g., due to typos in the repetitious code).

Depends On D125428

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125431

[mlir][PDLL] Tweak the grammar to highlight partial code better

This commit enables proper highlighting when inner statements are
outside of a constraint/pattern/etc. This shouldn't really happen in
actual code, but can happen in documentation (which uses the same
syntax grammar).

[mlir][NFC] Fix the tags for various doc code blocks

[lld-macho] Demangle symbol names in export-symbol error messages when -demangle is specified.
PR/55512

Reviewed By: keith

Differential Revision: https://reviews.llvm.org/D125732

[dwarf] Emit a DIGlobalVariable for constant strings.

An upcoming patch will extend llvm-symbolizer to provide the source line
information for global variables. The goal is to move AddressSanitizer
off of internal debug info for symbolization onto the DWARF standard
(and doing a clean-up in the process). Currently, ASan reports the line
information for constant strings if a memory safety bug happens around
them. We want to keep this behaviour, so we need to emit debuginfo for
these variables as well.

Reviewed By: dblaikie, rnk, aprantl

Differential Revision: https://reviews.llvm.org/D123534

[test-suite][cmake] sort unit test targets

This patch sorts unit test targets into directories corresponding to the
test source file directories to improve target navigation.

Reviewed By: smeenai

Differential Revision: https://reviews.llvm.org/D124810

[RISCV] Fix missing vsetvli in transparent block case

We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible miscompiles. D119518 introduced a workaround, but failed to consider blocks which only contain load/stores compatible with their incoming state.

When I went to rebase and simplify D125232, it turned out that not all of the correctness issues had been fixed yet after all. This is the correctness fix accidentally embedded in the original more complicated version.

Note that the test changes here are mostly regressions. It's worth noting that the simplified version of D125232 exactly reverses all the non-functional diffs in the test caused here. D125232 should be the immediate following commit.

Differential Revision: https://reviews.llvm.org/D125703

[RISCV] Use classic dataflow for VSETVLI insertion

Our current implementation of the InsertVSETVLI dataflow allows phase 3 to arrive at a different block end state than the data flow in phase 1/2 computed. This arises because a block which contains instructions (e.g. load or stores) which don't consume all the incoming bits of the VL/VTYPE can be compatible with multiple incoming states. The algorithm effectively changes the SEW on such instructions, and propagates the prior state forward. As phase 3 uses the block input state for this propagation, but phase 1/2 doesn't, this can result in different block end states.

If we don't correct for it, this discrepancy can result in miscompiles. This was the source of multiple recent bugs. However, by now we have fixes for all known correctness issues.

The basic strategy we use is to insert a compensation vsetvli to bring the block state leaving the block back into consistency with the one computed. This is correct, but results in extra vsetvlis being placed at the end of blocks.

This change adjusts the phase 1/2 algorithm to propagate the incoming block state through the block, allowing the compatibility rules to modify the end state. The algorithm may need to run slightly more iterations, but the end result is consistent with what phase 3 does.

The benefit of doing this is two fold.

First, we reverse some of the code quality introductions introduced in the functional fixes.

Second, we simplify the invariants, and allow the strict assertions to be enabled. Several humans, myself included, have found it quite surprising that invariant didn't hold already, and arguably that confusion is the cause of several of our recent miscompiles in this code.

The downside to this patch is that the dataflow may require additional iterations to stabilize. In the worse case, we go from O(Edges) to O(E + UniquePaths) as the incoming state (and thus the outgoing one) can now change once for each path from the entry block.

Differential Revision: https://reviews.llvm.org/D125232

[lld-macho] Temporarily disable test on windows
The metadata seems to be demangled differently

[nfc][lld-macho] Fixed test from https://reviews.llvm.org/D125732

Details:
The test was incorrectly expecting the error messages for the export symbols to have a particular order.
It shouldn't because the export symbol list is processed concurrently.

[WebAssembly] Update relaxed SIMD opcodes and names

to reflect the latest state of the proposal:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format.
Moves code around to match the instruction order from the proposal, but the only
functional changes are to the names and opcodes.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D125726

[mlir][sparse] Moved _mlir_ciface_newSparseTensor closer to its macros

This is a followup to D125431, to keep from confusing the machinery that generates diffs (since combining these two changes into one would obfuscate the changes actually made in the previous differential).

Depends On D125431

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D125432

[nfc][lld-macho] Follow up fixes to bd9e46815d73e4236c207bad8b5c54e7188154d7

Need -DAG in the first expect statement too

Revert "[dwarf] Emit a DIGlobalVariable for constant strings."

This reverts commit 4680982b36a84770a1600fc438be8ec090671724.

Broke a fuchsia windows bot. More details in the review:
https://reviews.llvm.org/D123534

[Frontend] [Coroutines] Emit error when we found incompatible allocation
function in promise_type

According to https://cplusplus.github.io/CWG/issues/2585.html, this
fixes https://github.com/llvm/llvm-project/issues/54881

Simply, the clang tried to found (do lookup and overload resolution. Is
there any better word to use than found?) allocation function in
promise_type and global scope. However, this is not consistent with the
standard. The standard behavior would be that the compiler shouldn't
lookup in global scope in case we lookup the allocation function name in
promise_type. In other words, the program is ill-formed if there is
incompatible allocation function in promise type.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D125517

[mlir][LLVMIR] Add support for translating insertelement/extractelement.

Add support for translating llvm::InsertElement and llvm::ExtractElement.

Differential Revision: https://reviews.llvm.org/D125674

[RISCV] Support getHostCpuName for sifive-u74

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D123978

[flang][OpenMP] Support lowering to MLIR for ordered clause

This supports the lowering parse-tree to MLIR for ordered clause in
worksharing-loop directive. Also add the test case for operation
conversion.

Part of this patch is from the fir-dev branch of
https://github.com/flang-compiler/f18-llvm-project.

Co-authored-by: Sourabh Singh Tomar <SourabhSingh.Tomar@amd.com>

Reviewed By: kiranchandramohan, NimishMishra

Differential Revision: https://reviews.llvm.org/D125456

[flang] Add one semantic check for elemental call arguments

As Fortran 2018 15.8.1(3), in a reference to an elemental procedure, if
any argument is an array, each actual argument that corresponds to an
INTENT (OUT) or INTENT (INOUT) dummy argument shall be an array. Add
this semantic check.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D125685

[KnownBits] Add operator==

Checking whether two KnownBits are the same is somewhat common,
mainly in test code.

I don't think there is a lot of room for confusion with "determine
what the KnownBits for an icmp eq would be", as that has a
different result type (this is what the eq() method implements,
which returns Optional<bool>).

Differential Revision: https://reviews.llvm.org/D125692

[StackColoring] Don't merge slots with differing StackIDs

The documentation for this specifically mentions that this should not
happen. We could think about adding target hooks to permit it (and how
to merge IDs) in the future if that is desirable.

This specific test case was merging a scalable-vector slot into a
non-scalable one and dropping the notion of scalability, meaning we
failed to allocate enough stack space for the object.

Reviewed By: arsenm, MaskRay, sdesmalen

Differential Revision: https://reviews.llvm.org/D125699

[RISCV] Add a test w/ RVV stack objects misaligning non-RVV ones

This patch adds a simple test which demonstrates a miscompilation of
16-byte-aligned scalar (non-RVV) objects when combined with RVV stack
objects.

The RISCV stack is assumed to be aligned to 16 bytes, and this is
guaranteed/assumed to be true when setting up the stack. However, when
the stack contains RVV objects, we decrement the stack pointer by some
multiple of vlenb, which is only guaranteed to be aligned to 8 bytes.
This means that non-RVV objects specifically requiring 16-byte alignment
fall through the cracks and are misaligned. Objects requiring larger
alignment trigger stack realignment and thus should be okay.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125382

[ConstantRange] Implement binaryXor() using known bits

This allows us to compute known high bits. It's not optimal, but
better than nothing.

[CVP] Add test for xor (NFC)

[LVI] Compute range for xor

We do have a non-trivial implementation for binaryXor() now.

[XCOFF] support writing sections, relocations and symbols for XCOFF64.

This is the second patch to enable the XCOFF64 object writer.

Reviewed By: jhenderson, shchenz

Differential Revision: https://reviews.llvm.org/D122287

[llvm] Fix typo for libxml2 detection

This seems to be a copy-paste from the similar zlib detection code.

Patch By: sthibaul

Differential Revision: https://reviews.llvm.org/D117052

[InstCombine] precommit tests for foldSelectToCopysign

[RISCV][NFC] Fix comment typos in split SP adjustment

[SelectionDAG] Support more VP reduction mask operation.

This patch uses VP_REDUCE_AND and VP_REDUCE_OR to replace VP_REDUCE_SMAX,VP_REDUCE_SMIN,VP_REDUCE_UMAX and VP_REDUCE_UMIN for mask vector type.

Differential Revision: https://reviews.llvm.org/D125002

[mlir] support isa/cast/dyn_cast<Operation *>(operation) again

The support for this has been added by 946311b8938114a37db5c9d42fb9f5a1481ccae1
but then ignored by bc22b5c9a2f729460ffdf7627b3534a8d9f3f767.

This enables one to write generic code that can be instantiated for both
specific operation classes and the common base class without
specialization. Examples include functions that take/return ops, such
as:

```mlir
template <typename FnTy>
void applyIf(FnTy &&lambda, ...) {
  for (Operation *op : ...) {
    auto specific = dyn_cast<function_traits<FnTy>::template arg_t<0>>(op);
    if (specific)
      lambda(specific);
  }
}
```

that would otherwise need to rely on template specialization to support
lambdas that take specific operations and those that take `Operation *`.

Differential Revision: https://reviews.llvm.org/D125543

Reviewed by: rriddle

[RISCV][NFC] Reword split SP adjustment comments

[SROA] Precommit test for D124967

[SROA] Avoid postponing rewriting load/store by ignoring lifetime intrinsics in partition's promotability checking

This patch fixes a bug that generates unnecessary packing/unpacking structure code because of incorrectly handling lifetime intrinsic.
For example, a partition of an alloca may contain many slices:
```
Partition [0, 4):
  Slice0: [0, 4) used by: load i32 addr;
  Slice1: [0, 4) used by: store i32 v, addr;
  Slice2: [0, 16) used by lifetime.start(16, addr);
```
When SROA determines if the partition can be promoted, lifetime.start is currently treated as a whole alloca load/store, so Slice0 and Slice1 cannot be promoted at this attempt,
but the packing/unpacking code for Slice0 and Slice1 has been generated.
After rewrite lifetime.start/end intrinsic, SROA tries again with Slice0 and Slice1 and finally promotes them, but redundant packing/unpacking code remaining in the IRs.
This patch changes promotability checking to ignore lifetime intrinsic (they will be rewritten to correct sizes later), so we can promote the real users (load/store) at the first attempt with optimal code.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D124967

[DWARFLinker][NFC] Add None value to the DwarfLinkerAccelTableKind enum.

this review is extracted from D86539.

1. Rename AccelTableKind to DwarfLinkerAccelTableKind
   (to differentiate from AccelTableKind from CodeGen/AsmPrinter/DwarfDebug.h)

2. Add None value to the DwarfLinkerAccelTableKind.

3. added 'None' value for 'accelerator' option of dsymutil.

Differential Revision: https://reviews.llvm.org/D125474

[JumpThreading] Don't pass DT to isGuaranteedNotToBeUndefOrPoison()

JumpThreading intentionally does not force updating of the DT
during optimization, because this may be expensive when many CFG
updates and DT calculations are interleaved.

We shouldn't be fetching the DT just for the purpose of calling
isGuaranteedNotToBeUndefOrPoison(), especially as DT availability
doesn't even show benefit in tests.

[OpenCL] Do not guard vload/store_half builtins

The vload*_half* and vstore*_half* builtins do not require the
cl_khr_fp16 extension: pointers to `half` can be declared without the
extension and the _half variants of vload and vstore should be
available without the extension.

This aligns the guards for these builtins for
`-fdeclare-opencl-builtins` with `opencl-c.h`.

Fixes https://github.com/llvm/llvm-project/issues/55275

Differential Revision: https://reviews.llvm.org/D125401

[X86] Attempt to fold EFLAGS into X86ISD::ADD/SUB ops

We already use combineAddOrSubToADCOrSBB to fold extended EFLAGS results into ISD::ADD/SUB ops as X86ISD::ADC/SBB carry ops.

This patch extends this to also try to fold EFLAGS results with X86ISD::ADD/SUB ops

Differential Revision: https://reviews.llvm.org/D125642

[WebAssembly][NFC] Convert StackBased instruction field to 'bit' from string

This is (IMHO) cleaner and (objectively) more strongly typed than using strings.

A follow-on patch will do the same for IsWasm64.

Differential Revision: https://reviews.llvm.org/D125713

[WebAssembly][NFC] Convert IsWasm64 instruction field to 'bit' from string

Extends the cleanup in D125713 to IsWasm64.

Differential Revision: https://reviews.llvm.org/D125714

[JumpThreading] Regenerate test checks (NFC)

[AArch64] Extra tests useful for D-lane shuffles. NFC

[VPlan] Move usesScalars/onlyFirstLaneUsed to VPUser.

Those helpers model properties of a user and they should also be
available to non-recipe users. This will be used in D123537 for a new
exit value user.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D124936