Changes

Summary

  1. [MachineSink] replace MachineLoop with MachineCycle (details)
  2. [X86][AMX] Multiple configure for AMX register. (details)
  3. [gn build] Port 496156ac57da (details)
  4. [RISCV] Fix RVV stack frame alignment bugs (details)
  5. [RISCV] Ensure the entire stack is aligned to the RVV stack alignment (details)
  6. [LegalizeTypes][VP] Fix OpNo in WidenVecOp_VP_SCATTER (details)
  7. [LoopUnroll] Freeze tripcount rather than condition (details)
  8. llvm-reduce: improve basic-blocks removal pass (details)
  9. [InstCombine] Use different icmp pattern in test (NFC) (details)
  10. [InstCombine] Handle logical and/or in recursive and/or of icmps fold (details)
  11. [libc++] type_traits: use __is_core_convertible in __invokable_r. (details)
  12. [LegalizeTypes][NFC] Fix node name in assertion message (details)
  13. [libc++] Replace modulus operations in std::seed_seq::generate with conditional checks. (details)
  14. [libc++] Implement ranges::reverse (details)
  15. [gn build] Port 1d1a191edcfa (details)
  16. [InstCombine] Add splat vector test for asymmetric masked icmp fold (details)
  17. [InstCombine] Use m_APInt() in asymmetric masked icmp fold (details)
  18. [InstCombine] Add tests for masked icmps with bitwise+logical and (NFC) (details)
  19. [InstCombine] Support logical and in masked icmp fold (details)
  20. [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr (details)
  21. [TableGen] Remove code beads (details)
  22. [X86] Add test showing failure to expand <2 x float> fpow without widening to <4 x float> (details)
  23. [X86][AMX] Reduce the compiling time for non-amx code. (details)
  24. [Test] Add LICM test for PR55672 showing problem with freeze instruction (details)
  25. Fix comment in test. NFC (details)
  26. [OpenCL] Make -cl-ext a driver option. (details)
  27. [X86] scalar_widen_div.ll - remove non-generated CHECKs (details)
  28. Minutes for security group sync-ups have moved to Discourse. (details)
  29. [Clang][CodeGen] Fix the cmse-clear-return.c test. (details)
  30. Revert "[TableGen] Remove code beads" (details)
  31. [x86][DAG] Unroll vectorized FREMs that will become libcalls (details)
  32. [SLP][NFC]Make isFirstInsertElement a weak strict ordering comparator. (details)
  33. [OpenMP] Add `-Xoffload-linker` to forward input to the device linker (details)
  34. [pseudo] (trivial) bracket-matching (details)
  35. [InstCombine] Add tests for freeze of load with metadata (NFC) (details)
  36. [InstCombine] Use IRBuilder in freeze pushing transform (PR55619) (details)
  37. [libc++] Rename the generic-singlethreaded CI job to generic-no-threads for consistency (details)
  38. [InstCombine] Add test for GEP difference with bitcasts (NFC) (details)
  39. [InstCombine] Strip bitcasts in GEP diff fold (details)
  40. [AMDGPU][MC][GFX11] Support base+soffset+offset SMEM loads. (details)
  41. [CostModel][X86] getScalarizationOverhead - improve extraction costs for > 128-bit vectors (details)
  42. [mlir][vector] Add new lowering mode to vector.contractionOp (details)
  43. [TypePromotion] Avoid unnecessary trunc zext pairs (details)
  44. [libcxx] Add sort.bench.cpp to libcxx/benchmarks/CMakeLists.txt (details)
  45. [DAG] Unroll vectorized FPOW instructions before widening that will scalarize to libcalls anyway (details)
  46. Fix behavior of is_fp_class on empty class set (details)
  47. [flang][runtime] Clean up asynchronous I/O APIs (details)
  48. [mlir] Breakdown diagnostic string literals (details)
  49. [mlir] Rename mlir::SmallVector -> llvm::SmallVector (details)
  50. [libc++][NFC] Move definitions around in string.cpp to reduce _LIBCPP_HAS_NO_WIDE_CHARACTERS blocks (details)
  51. [libc++][NFC] Whitespace refactoring of string.cpp for consistency and legibility (details)
  52. [gn build] (semi-automatically) port 0360b9f1599b (details)
  53. [Clang] Avoid misleading 'conflicting types' diagnostic with no-prototype decls. (details)
  54. [flang] Extension: Accept Hollerith actual arguments as if they were BOZ (details)
  55. [gn build] Reformat all build files (details)
  56. [RISCV] Add test cases showing failure to remove mask on rotate amounts. (details)
  57. Recommit "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates." (details)
  58. [PS5] Verify defaults to -fno-stack-size-section (details)
  59. [flang][runtime] INQUIRE(UNIT=666,NUMBER=n) must set n=666 (details)
  60. NFC. Clang-formatting. (details)
  61. Revert "[PS5] Verify defaults to -fno-stack-size-section" (details)
  62. [libclang] add supporting for indexing/visiting C++ concepts (details)
  63. [AMDGPU] Enforce alignment of image vaddr on gfx90a (details)
  64. Reland "[PS5] Verify defaults to -fno-stack-size-section" (details)
  65. [clangd] Handle '--' in QueryDriverDatabase (details)
  66. [compiler-rt][lsan] Update CanBeAHeapPointer for AArch64 (details)
  67. [flang][runtime] Handle BACKSPACE after reading past EOF (details)
  68. [OpenMP] Add parsing/sema support for omp_all_memory reserved locator (details)
  69. [OpenMP] Fix file arguments for embedding bitcode in the linker wrapper (details)
  70. Sema: adjust assertion to account for deduced types (details)
  71. [compiler-rt][scudo] Simplify TBI checks (details)
  72. [AMDGPU] Disable newly added gfx90a global isel image tests. NFC. (details)
  73. [flang] Alternate entry points with unused arguments (details)
  74. [flang] Fix crash in semantics after PDT instantiation (details)
  75. Recommit "[SelectOpti][5/5] Optimize select-to-branch transformation" (details)
  76. [compiler-rt][scudo] Add missing preprocessor token (details)
  77. Revert "[compiler-rt][scudo] Add missing preprocessor token" and "[compiler-rt][scudo] Simplify TBI checks" (details)
  78. [InstCombine] fold more shuffles with FP<->Int cast operands (details)
  79. [SLP] Fix crash caused by reorderBottomToTop(). (details)
  80. [flang] Catch calls to assumed-length character functions (details)
  81. [Sanitizers][Darwin] Replace SANITIZER_MAC with SANITIZER_APPLE in source files (details)
  82. [clang][dataflow] Make limit on fixpoint-algorithm iterations proportional to size of CFG. (details)
  83. [flang] Don't prematurely resolve subprogram names (details)
  84. [clang][test] mark tests added in ee8524087c78 as unsupported on AIX (details)
  85. [flang] Fix purity testing for generic calls (details)
  86. [flang] Accept defined assignment with CLASS(*) RHS (details)
  87. [flang] Fix false error for multiple defined I/O subroutines (details)
  88. [clang][dataflow] Relax `Environment` comparison operation. (details)
  89. [flang] Process subprogram BIND(C,NAME=...) locally (details)
  90. [flang] Replace crash and improve a semantics TODO message (details)
  91. [flang][runtime] Catch decimal integer input overflow (details)
  92. Fix build failure revealed by c35ca3a1c78f693b749ad11742350b7fc6c5cd89 (details)
  93. [Flang][OpenMP] Fixes for unstructured OpenMP code (details)
  94. [SelectionDAG] Add support to widen ISD::STEP_VECTOR operations. (details)
  95. [RISCV] Hoist VSETVLI out of idiomatic fixed length vector loops (details)
  96. [riscv] Use getFirstInstrTerminator [nfc] (details)
  97. [RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt. (details)
  98. [mlir][sparse] add new complex ops to reduction recognition (details)
  99. [RISCV] Ensure the forwarded AVL register is alive (details)
  100. [OpenMP] Add codegen for 'omp_all_memory' reserved locator. (details)
  101. [libc] Add the pthread_mutex_t type. (details)
  102. [InstCombine] Fold memrchr calls with sequences of identical bytes. (details)
  103. [mlir][sparse] complex lowering (details)
  104. [LLVM][IR] Fix assert in ConstantExpr::getPtrToInt so all vector types are supported. (details)
  105. [DFSan] Add option to specify individual library files, and an option to exit with an error code if any library file was not found. (details)
  106. [clang-tidy] Fix #55134 (regression introduced by 5da7c04) (details)
  107. [lldb] Disable modules in Apple-lldb-base (details)
  108. [lldb] Improve TestAppleSimulatorOSType.py error message (details)
  109. [BOLT][NFC] Remove unused BF::computeLocalUDChain method definition (details)
  110. [BOLT][NFC] Use for_each to simplify printLoopInfo (details)
  111. [BOLT][NFC] Customize endline character for printInstruction(s) (details)
  112. [BOLT][NFC] Use ListSeparator in BinaryFunction print methods (details)
  113. [clang-format][NFC] Insert/remove braces in clang/lib/Format/ (details)
  114. [InstCombine] add test for trunc-shl-trunc ; NFC (details)
  115. [InstCombine] [NFC] Move transforms for truncated shifts into narrowBinOp (details)
  116. [C++20] [Coroutines] Conform the updates for CWG issue 2585 (details)
  117. Revert "[MachineSink] replace MachineLoop with MachineCycle" (details)
  118. [libc++][NFC] Add more tests to `move_{iterator,sentinel}`. (details)
  119. Move GCC-compatible pod-packing change to v15/old behavior available at v14 and below (details)
  120. [RISCV] Replace untested code with assert (details)
  121. [flang][MSVC] Fix building with `/permissive-` flag (details)
  122. [RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL. (details)
Commit 62a9b36fcf728b104ea87e6eb84c0be69b779df7 by czhengsz
[MachineSink] replace MachineLoop with MachineCycle

MachineCycle can handle irreducible loop. Natural loop
analysis (MachineLoop) can not return correct loop depth if
the loop is irreducible loop. And MachineSink is sensitive
to the loop depth, see MachineSinking::isProfitableToSinkTo().

This patch tries to use MachineCycle so that we can handle
irreducible loop better.

Reviewed By: sameerds, MatzeB

Differential Revision: https://reviews.llvm.org/D123995
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/switch-phi-const.ll
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/RISCV/O3-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineCycleAnalysis.h
The file was modifiedllvm/lib/CodeGen/MachineCycleAnalysis.cpp
The file was modifiedllvm/test/CodeGen/X86/pr38795.ll
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
The file was modifiedllvm/include/llvm/ADT/GenericCycleImpl.h
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/CodeGen/AArch64/loop-sink-limit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/x86-shrink-wrapping.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineSSAContext.h
The file was modifiedllvm/include/llvm/ADT/GenericCycleInfo.h
Commit 496156ac57da3abd9c8a6dc422852b7bdfaa448f by yuanke.luo
[X86][AMX] Multiple configure for AMX register.

The previous solution depends on variable name to record the shape
information. However it is not reliable, because in release build
compiler would not set the variable name. It can be accomplished with an
additional option `fno-discard-value-names`, but it is not acceptable
for users.
This patch is to preconfigure the tile register with machine
instruction. It follow the same way what sigle configure does. In the
future we can fall back to multiple configure when single configure
fails due to the shape dependency issue.
The algorithm to configure the tile register is simple in the patch. We
may improve it in the future. It configure tile register based on basic
block. Compiler would spill the tile register if it live out the basic
block. After the configure there should be no spill across tile
confgiure in the register alloction. Just like fast register allocation
the algorithm walk the instruction in reverse order. When the shape
dependency doesn't meet, it insert ldtilecfg after the last instruction
that define the shape.
In post configuration compiler also walk the basic block to collect the
physical tile register number and generate instruction to fill the stack
slot for the correponding shape information.
TODO: There is some following work in D125602. The risk is modifying the
fast RA may cause regression as fast RA is usded for different targets.
We may create an independent RA for tile register.

Differential Revision: https://reviews.llvm.org/D125075
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastconfig-phi2.mir
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-across-func.ll
The file was modifiedllvm/lib/Target/X86/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastconfig-phi.mir
The file was modifiedllvm/lib/Target/X86/X86.h
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastconfig-phi4.mir
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-zero-config.ll
The file was addedllvm/lib/Target/X86/X86FastPreTileConfig.cpp
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
The file was addedllvm/test/CodeGen/X86/AMX/amx-fastconfig-spill.mir
The file was modifiedllvm/lib/Target/X86/X86FastTileConfig.cpp
Commit 1868f3c17db971bde79f54530aa8686f04bff287 by llvmgnsyncbot
[gn build] Port 496156ac57da
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
Commit cb8681a2b3ad406f1215a17fd32989211c561e3e by fraser
[RISCV] Fix RVV stack frame alignment bugs

This patch addresses several alignment issues in the stack frame when
RVV objects are taken into account.

One bug is that the RVV stack was never guaranteed to keep the alignment
of the stack *as a whole*. We must maintain a 16-byte aligned stack at
all times, especially when calling other functions. With the standard V
extension, this is conveniently happening since VLEN is at least 128 and
always 16-byte aligned. However, we support Zvl64b which does not
guarantee this. To fix this, the RVV stack size is rounded up to be
aligned to 16 bytes. This in practice generally makes us allocate a
stack sized at least 2*VLEN in size, and a multiple of 2.

    |------------------------------| -- <-- FP
    | 8-byte callee-save           | |      |
    |------------------------------| |      |
    | one VLENB-sized RVV object   | |      |
    |------------------------------| |      |
    | 8-byte local variable        | |      |
    |------------------------------| -- <-- SP (must be aligned to 16)

In the example above, with Zvl64b we are decrementing SP by 12 bytes
which does not leave SP correctly aligned. We therefore introduce an
extra VLENB-sized amount used for alignment. This would therefore ensure
the total stack size was 16 bytes (48 for Zvl128b, 80 for Zvl256b, etc):

    |------------------------------| -- <-- FP
    | 8-byte callee-save           | |      |
    |------------------------------| |      |
    | one VLENB-sized padding obj  | |      |
    | one VLENB-sized RVV object   | |      |
    |------------------------------| |      |
    | 8-byte local variable        | |      |
    |------------------------------| -- <-- SP

A new RVV invariant has been introduced in this patch, which is that the
base of the RVV stack itself is now always aligned to 16 bytes, not 8 as
before. This keeps us more in line with the scalar stack and should be
easier to reason about. The calculation of the RVV padding has thus
changed to be the amount required to align the scalar local variable
section to the RVV section's alignment. This amount is further rounded
up when setting up the initial stack to keep everything aligned:

    |------------------------------| -- <-- FP
    | 8-byte callee-save           |
    |------------------------------|
    |                              |
    | RVV objects                  |
    | (aligned to at least 16)     |
    |                              |
    |------------------------------|
    | RVV padding of 8 bytes       |
    |------------------------------|
    | 8-byte local variable        |
    |------------------------------| -- <-- SP

In the example above, it's clear that we need 8 bytes of padding to keep
the RVV section aligned to 16 when using SP. But to keep SP *itself*
aligned to 16 we can't decrement the initial stack pointer by 24 - we
have to round up to 32.

With the RVV section correctly aligned, the second bug fixed by
this patch is that RVV objects themselves are now correctly aligned. We
were previously only guaranteeing an alignment of 8 bytes, even if they
required a higher alignment. This is relatively simple and in practice
we see more rounding up of VLEN amounts to account for alignment in
between objects:

    |------------------------------|
    | RVV object (aligned to 16)   |
    |------------------------------|
    | no padding necessary         |
    |------------------------------|
    | 2*VLENB RVV object (align 16)|
    |------------------------------|
    | VLENB alignment padding      |
    |------------------------------|
    | RVV object (align 32)        |
    |------------------------------|
    | 3*VLENB alignment padding    |
    |------------------------------|
    | VLENB RVV object (align 32)  |
    |------------------------------| -- <-- base of RVV section

Note that a lot of the regressions in codegen owing to the new alignment
rules are correct but actually only strictly necessary for Zvl64b (and
Zvl32b but that's not really supported). I plan a follow-up patch to
take the known VLEN into account when padding for alignment.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D125787
The file was modifiedllvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/memory-args.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/localvar.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
Commit 08c9fb8447108fd436bd342a573181c624485608 by fraser
[RISCV] Ensure the entire stack is aligned to the RVV stack alignment

This patch fixes another bug in the RVV frame lowering. While some frame
objects with non-default stack IDs (such scalable-vector alloca
instructions) are considered in the target-independent max alignment
calculations, others (for example, during calling-convention lowering)
are not. This means we'd occasionally align the base of the stack to
only 16 bytes, with no way to ensure that the RVV section contained
within that is aligned to anything higher.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D125973
The file was modifiedllvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
Commit be84f91f87a787ebfa8a346e936a5c88bc87b047 by Lian.Wang
[LegalizeTypes][VP] Fix OpNo in WidenVecOp_VP_SCATTER

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D126276
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit 81c648a3d909cf0c1c1c635309f35b93d07307d1 by npopov
[LoopUnroll] Freeze tripcount rather than condition

This is a followup to D125754. We introduce two branches, one
before the unrolled loop and one before the epilogue (and similar
for the prologue case). The previous patch only froze the
condition on the first branch.

Rather than independently freezing the second condition, this patch
instead freezes TripCount and bases BECount on it. These are the
two quantities involved in the conditions, and this ensures that
both work on a consistent, non-poisonous trip count.

Differential Revision: https://reviews.llvm.org/D125896
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-at-most-two-exits.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
Commit bb8e02325ffc96d4a3a21aa9eefabb8bd205b214 by markus.lavin
llvm-reduce: improve basic-blocks removal pass

When the single branch target of a block has been removed try updating
it to target a  block that is kept (by scanning forward in the sequence)
instead of replacing the branch with a return instruction. Doing so
reduces the risk of breaking loop structures meaning that when the loop
is 'interesting' these reductions should have more blocks eliminated.

Differential Revision: https://reviews.llvm.org/D125766
The file was addedllvm/test/tools/llvm-reduce/remove-bbs-sequence.py
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
The file was addedllvm/test/tools/llvm-reduce/remove-bbs-sequence.ll
Commit 973c7e0654b21c6ae7093b4ea0362c6096945c38 by npopov
[InstCombine] Use different icmp pattern in test (NFC)

Use an and/or of icmp pattern that produces different code
depending on whether it is part of a logical or bitwise and/or.
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
Commit c0e06c7448a2dd16796e210a66de68f269363e31 by npopov
[InstCombine] Handle logical and/or in recursive and/or of icmps fold

The and/or of icmps fold is also applied in reassociated form.
However, this currently only happens for bitwise and of bitwise
and, but not for bitwise and of logical and (or other combinations,
but this is the one being addressed here).

We can do this for bitwise+logical combinations as well, but need
to be a bit careful about which of the resulting ands are logical:
https://alive2.llvm.org/ce/z/WYSjGh
https://alive2.llvm.org/ce/z/guxYnz
https://alive2.llvm.org/ce/z/S5SYxY
https://alive2.llvm.org/ce/z/2rAWeW
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/and2.ll
Commit c3a24882903df5b25c011628162e82e47401f71f by nikolasklauser
[libc++] type_traits: use __is_core_convertible in __invokable_r.

This fixes incorrect handling of non-moveable types, adding tests for this case.
See [issue 55346](https://github.com/llvm/llvm-project/issues/55346).

The current implementation is based on is_convertible, which is
[defined](https://timsong-cpp.github.io/cppwp/n4659/meta.rel#5) in terms of
validity of the following function:

```
To test() {
  return declval<From>();
}
```

But this doesn't work if To and From are both some non-moveable type, which the
[definition](https://timsong-cpp.github.io/cppwp/n4659/conv#3) of implicit
conversions says should work due to guaranteed copy elision:

```
To to = E;  // E has type From
```

It is this latter definition that is used in the
[definition](https://timsong-cpp.github.io/cppwp/n4659/function.objects#func.require-2)
of INVOKE<R>. Make __invokable_r use __is_core_convertible, which
captures the ability to use guaranteed copy elision, making the
definition correct for non-moveable types.

Fixes llvm/llvm-project#55346.

Reviewed By: #libc, philnik, EricWF

Spies: EricWF, jloser, ldionne, philnik, libcxx-commits

Differential Revision: https://reviews.llvm.org/D125300
The file was modifiedlibcxx/test/std/utilities/meta/meta.rel/is_nothrow_invocable.pass.cpp
The file was addedlibcxx/test/std/utilities/meta/meta.rel/is_invocable_r.compile.pass.cpp
The file was modifiedlibcxx/include/type_traits
The file was addedlibcxx/test/std/utilities/meta/meta.rel/is_invocable_r_v.compile.pass.cpp
Commit 7f7ef0ed617ec4a51f10b82390cafb08433d03b5 by fraser
[LegalizeTypes][NFC] Fix node name in assertion message

This was probably copy/pasted from the MSCATTER widening.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit b07880454ba32e48a2e7f7be35516e0b76f60077 by nikolasklauser
[libc++] Replace modulus operations in std::seed_seq::generate with conditional checks.

Abseil benchmarks suggest that the conditional checks result in faster code (4-5x)
as they are compiled into conditional move instructions (cmov on x86).

Reviewed By: #libc, philnik, Mordante

Spies: pengfei, Mordante, philnik, libcxx-commits

Differential Revision: https://reviews.llvm.org/D125329
The file was addedlibcxx/benchmarks/random.bench.cpp
The file was modifiedlibcxx/include/__random/seed_seq.h
Commit 1d1a191edcfa87bf77331ffcc8fa29562b17f517 by nikolasklauser
[libc++] Implement ranges::reverse

Reviewed By: var-const, #libc

Spies: libcxx-commits, mgorny

Differential Revision: https://reviews.llvm.org/D125752
The file was modifiedlibcxx/docs/Status/RangesAlgorithms.csv
The file was addedlibcxx/test/std/algorithms/alg.modifying.operations/alg.reverse/ranges.reverse.pass.cpp
The file was modifiedlibcxx/test/std/library/description/conventions/customization.point.object/niebloid.compile.pass.cpp
The file was modifiedlibcxx/test/support/almost_satisfies_types.h
The file was modifiedlibcxx/test/libcxx/private_headers.verify.cpp
The file was addedlibcxx/include/__algorithm/ranges_reverse.h
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/include/module.modulemap
Commit 3245e2edd50c87fe9ceb98e8742566dd5f67dc44 by llvmgnsyncbot
[gn build] Port 1d1a191edcfa
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit e1fcf998dc95f832da440ce9227c83fa6af96011 by npopov
[InstCombine] Add splat vector test for asymmetric masked icmp fold
(NFC)
The file was modifiedllvm/test/Transforms/InstCombine/icmp-logical.ll
Commit 5abaabed22d749360d2c1d77907d927207de87b4 by npopov
[InstCombine] Use m_APInt() in asymmetric masked icmp fold

This is mostly intended as code cleanup, but it does also add
support for splat vectors to this fold.
The file was modifiedllvm/test/Transforms/InstCombine/icmp-logical.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 4aa32e1b17da4d29fe2db0fe1cfb0171243b4fed by npopov
[InstCombine] Add tests for masked icmps with bitwise+logical and (NFC)
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
Commit a7c079aaa227d55ad9cb6b916500d99b4fdf26d2 by npopov
[InstCombine] Support logical and in masked icmp fold

Most of the folds implemented in this function work fine with
logical operations. We only need to be careful for the cases that
work on non-constant masks, where the RHS operand shouldn't be
poison.

This is a conservative implementation that bails out of illegal
transforms, but we could also change these to insert freeze instead.
The file was modifiedllvm/test/Transforms/InstCombine/and-or-icmps.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit b166aa833e44a5af6d6f39c34b79fe21b443e424 by kito.cheng
[RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

This NFC patch is splited from D111617.

Using llvm::ArrayRef rather than llvm::SmallVector, ArrayRef is more generic
interface that could accept both llvm::ArrayRef and llvm::SmallVector.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D125893
The file was modifiedclang/lib/Support/RISCVVIntrinsicUtils.cpp
The file was modifiedclang/include/clang/Support/RISCVVIntrinsicUtils.h
Commit f50be3d21808ae113c40a68a9ac6581f203d92d2 by ox59616e
[TableGen] Remove code beads

Code beads is useless since the only user, M68k, has moved on to
a new encoding/decoding infrastructure.
The file was modifiedllvm/lib/Target/M68k/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
The file was modifiedllvm/utils/TableGen/TableGenBackends.h
The file was removedllvm/utils/TableGen/CodeBeadsGen.cpp
The file was modifiedllvm/utils/TableGen/TableGen.cpp
The file was modifiedllvm/utils/TableGen/CMakeLists.txt
Commit 64186e9b351a000123f253557f4f607c33405413 by llvm-dev
[X86] Add test showing failure to expand <2 x float> fpow without widening to <4 x float>

Similar to D125988 (and I have a pending follow up patch to handle fpow).
The file was addedllvm/test/CodeGen/X86/pow-libcall.ll
Commit 3b1de7ab6097adc92d5057bc9172c48806704e8c by yuanke.luo
[X86][AMX] Reduce the compiling time for non-amx code.

Differential Revision: https://reviews.llvm.org/D126280
The file was modifiedllvm/lib/Target/X86/X86FastPreTileConfig.cpp
Commit 1968f765c359304860b063ebe51cee2544433728 by mkazantsev
[Test] Add LICM test for PR55672 showing problem with freeze instruction
The file was addedllvm/test/Transforms/LICM/pr55672.ll
Commit 143ca151061d7266dd97ef6bda7b9db58fb5e4dc by mkazantsev
Fix comment in test. NFC
The file was modifiedllvm/test/Transforms/LICM/pr55672.ll
Commit d61ded1034bb9563c43d048ba0be4eff662e6144 by anastasia.stulova
[OpenCL] Make -cl-ext a driver option.

For generic targets such as SPIR-V clang sets all OpenCL
extensions/features as supported by default. However
concrete targets are unlikely to support all extensions
features, which creates a problem when such generic SPIR-V
binary is compiled for a specific target later on.

To allow compile time diagnostics for unsupported features
this flag is now being exposed in the clang driver.

Differential Revision: https://reviews.llvm.org/D125243
The file was modifiedclang/docs/OpenCLSupport.rst
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/opencl.cl
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/docs/UsersManual.rst
Commit 96323c9f4c10bef5cb5d527970cabc73eab8aa21 by llvm-dev
[X86] scalar_widen_div.ll - remove non-generated CHECKs

These were left over from when we converted to the update_llc_test_checks script and were just matching some asm/cfi directives - we have CHECK-LABEL to do this properly now.
The file was modifiedllvm/test/CodeGen/X86/scalar_widen_div.ll
Commit 8d2918750684fb54ba32efe410553f5e7711f503 by kristof.beyls
Minutes for security group sync-ups have moved to Discourse.
The file was modifiedllvm/docs/GettingInvolved.rst
Commit be4eaf10eef76869eb404f68703a1a09b344a7e5 by ivan.kosarev
[Clang][CodeGen] Fix the cmse-clear-return.c test.

Caught with D125604.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D126191
The file was modifiedclang/test/CodeGen/cmse-clear-return.c
Commit 1e2b746390e3c869d34a8651c35e68e26214e410 by sylvestre
Revert "[TableGen] Remove code beads"

It is breaking the build with:

/build/llvm-toolchain-snapshot-15~++20220524114008+96323c9f4c10/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp:478:10: fatal error: 'M68kGenMCCodeBeads.inc' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Remove the #include causes:
error: undefined reference to 'llvm::M68k::getMCInstrBeads(unsigned int)'

This reverts commit f50be3d21808ae113c40a68a9ac6581f203d92d2.
The file was modifiedllvm/utils/TableGen/TableGenBackends.h
The file was modifiedllvm/utils/TableGen/TableGen.cpp
The file was modifiedllvm/lib/Target/M68k/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
The file was modifiedllvm/utils/TableGen/CMakeLists.txt
The file was addedllvm/utils/TableGen/CodeBeadsGen.cpp
Commit 8b5d9cbbfedc7a91e3b462030e534c5982de674d by jeremy.morse
[x86][DAG] Unroll vectorized FREMs that will become libcalls

Currently, two element vectors produced as the result of a binary op are
widened to four element vectors on x86 by
DAGTypeLegalizer::WidenVecRes_BinaryCanTrap. If the op still isn't legal
after widening it is unrolled into 4 scalar ops in SelectionDAG before
being converted into a libcall. This way we end up with 4 libcalls (two of
them on known undef elements) instead of the original two libcalls.

This patch modifies DAGTypeLegalizer::WidenVectorResult to ensure that if
it is known that a binary op will be tunred into a libcall, it is unrolled
instead of being widened. This prevents the creation of the extra scalar
instructions on known undef elements and (eventually) libacalls with known
undef parameters which would otherwise be created when the op gets expanded
post widening.

Differential Revision: https://reviews.llvm.org/D125988
The file was modifiedllvm/test/CodeGen/X86/frem-libcall.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit f9c806ae5c53c990a935c46ba351cdcfb1271c58 by a.bataev
[SLP][NFC]Make isFirstInsertElement a weak strict ordering comparator.

To be used correctly in a sort-like function, isFirstInsertElement
function must follow weak strict ordering rule, i.e.
isFirstInsertElement(IE1, IE1) should return false.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit f37101983fc9fabbbde4b10f613ed248a424d71a by jhuber6
[OpenMP] Add `-Xoffload-linker` to forward input to the device linker

We use the clang-linker-wrapper to perform device linking of embedded
offloading object files. This is done by generating those jobs inside of
the linker-wrapper itself. This patch adds an argument in Clang and the
linker-wrapper that allows users to forward input to the device linking
phase. This can either be done for every device linker, or for a
specific target triple. We use the `-Xoffload-linker <arg>` and the
`-Xoffload-linker-<triple> <arg>` syntax to accomplish this.

Reviewed By: markdewing, tra

Differential Revision: https://reviews.llvm.org/D126226
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/openmp-offload-gpu-new.c
The file was modifiedclang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/linker-wrapper.c
Commit 0360b9f1599b0b13f164d8170a619b19f9cb8bb4 by sam.mccall
[pseudo] (trivial) bracket-matching

Error-tolerant bracket matching enables our error-tolerant parsing strategies.
The implementation here is *not* yet error tolerant: this patch sets up the APIs
and plumbing, and describes the planned approach.

Differential Revision: https://reviews.llvm.org/D125911
The file was modifiedclang-tools-extra/pseudo/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/pseudo/benchmarks/Benchmark.cpp
The file was addedclang-tools-extra/pseudo/include/clang-pseudo/Bracket.h
The file was modifiedclang-tools-extra/pseudo/tool/ClangPseudo.cpp
The file was addedclang-tools-extra/pseudo/lib/Bracket.cpp
The file was addedclang-tools-extra/pseudo/unittests/BracketTest.cpp
The file was modifiedclang-tools-extra/pseudo/lib/CMakeLists.txt
The file was modifiedclang-tools-extra/pseudo/include/clang-pseudo/Token.h
Commit e7ddb4f6b4e0b580f7a6f2fdc654aff0a82cffa9 by npopov
[InstCombine] Add tests for freeze of load with metadata (NFC)
The file was modifiedllvm/test/Transforms/InstCombine/freeze.ll
Commit b2a13d3e2ddb905a7340dae42a08b9fc985b1054 by npopov
[InstCombine] Use IRBuilder in freeze pushing transform (PR55619)

Use IRBuilder so that the newly created freeze instructions
automatically gets inserted back into the IC worklist.

The changed worklist processing order leads to some cosmetic
differences in tests.

Fixes https://github.com/llvm/llvm-project/issues/55619.
The file was modifiedllvm/test/Transforms/PGOProfile/chr.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/freeze.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
Commit a9a6e200125e39c7cf1d3d0724bbcebbd17212aa by Louis Dionne
[libc++] Rename the generic-singlethreaded CI job to generic-no-threads for consistency
The file was removedlibcxx/cmake/caches/Generic-singlethreaded.cmake
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was addedlibcxx/cmake/caches/Generic-no-threads.cmake
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 3eab6c5911415ce1f9b72738025f8f5051b55c34 by npopov
[InstCombine] Add test for GEP difference with bitcasts (NFC)
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
Commit e6e0eb3bc89d054889c1c663ccf600581ed77c7e by npopov
[InstCombine] Strip bitcasts in GEP diff fold

Bitcasts were stripped in one case, but not the other. Of course,
this no longer really matters with opaque pointers, but as I went
through the trouble of tracking this down, we may as well remove
one typed vs opaque pointer optimization discrepancy.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
The file was modifiedllvm/test/Transforms/InstCombine/getelementptr.ll
Commit 1586e1dc957677df0f37da603bb35586e1b6a172 by ivan.kosarev
[AMDGPU][MC][GFX11] Support base+soffset+offset SMEM loads.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D126207
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx11_asm_smem.s
Commit 6c80267d0ff445c0c47c6ddb283da5a8bc4feb64 by llvm-dev
[CostModel][X86] getScalarizationOverhead - improve extraction costs for > 128-bit vectors

We were using the default getScalarizationOverhead expansion for extraction costs, which adds up all the individual element extraction costs.

This is fine for 128-bit vectors, but for 256/512-bit vectors each element extraction also has to account for extracting the upper 128-bit subvector extraction before it can handle the element. For scalarization costs we only need to extract each demanded subvector once.

Differential Revision: https://reviews.llvm.org/D125527
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-replication-i16.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-store-i8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-replication-i32.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptosi.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/trunc.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoi_sat.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-replication-i8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-replication-i64.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fadd.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/sitofp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-store-i16.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoui.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll
Commit 89aaa2d033270d6eeeb82429c0bb88a78ae030fa by thomasraoux
[mlir][vector] Add new lowering mode to vector.contractionOp

Add lowering for cases where the reduction dimension is fully unrolled.
It is common to unroll the reduction dimension, therefore we would want
to lower the contractions to an elementwise vector op in this case.

Differential Revision: https://reviews.llvm.org/D126120
The file was modifiedmlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
The file was modifiedmlir/test/Dialect/Vector/vector-contract-transforms.mlir
The file was modifiedmlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Commit e0fe9785d35203d6b76670cb2b8c6449db4fa576 by sam.parker
[TypePromotion] Avoid unnecessary trunc zext pairs

Any zext 'sink' should already have an operand that is in the legal
value, so avoid using a trunc and just use the trunc operand instead.

Differential Revision: https://reviews.llvm.org/D118905
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
The file was modifiedllvm/test/Transforms/TypePromotion/ARM/casts.ll
Commit ebe2e4f5b773e73e3a0d50804e3c72aed6b90b9f by hans
[libcxx] Add sort.bench.cpp to libcxx/benchmarks/CMakeLists.txt

It was forgotten in D124740.

Differential revision: https://reviews.llvm.org/D126297
The file was modifiedlibcxx/benchmarks/CMakeLists.txt
Commit 11455e47588940bd397e72e0c50811001c09295e by llvm-dev
[DAG] Unroll vectorized FPOW instructions before widening that will scalarize to libcalls anyway

Followup to D125988 - FPOW is similar to FREM and will most likely scalarize to libcalls, so unroll before widening to prevent use making additional libcalls with UNDEF args.
The file was modifiedllvm/test/CodeGen/X86/pow-libcall.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit 6fc0bc5b0fa7b87960a8b326853643df503d76f7 by sepavloff
Fix behavior of is_fp_class on empty class set

The second argument to is_fp_class specifies the set of floating-point
class to test against. It can be zero, in this case the intrinsic is
expected to return zero value.

Differential Revision: https://reviews.llvm.org/D112025
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/is_fpclass.ll
Commit deb62f5ad64931c6d47ef3cbf9bb53f4f651b3ae by pklausler
[flang][runtime] Clean up asynchronous I/O APIs

Now that the requirements and implementation of asynchronous I/O are
better understood, adjust their I/O runtime APIs.  In particular:
1) Remove the BeginAsynchronousOutput/Input APIs; they're not needed,
   since any data transfer statement might have ASYNCHRONOUS= and
   (if ASYNCHRONOUS='YES') ID= control list specifiers that need to
   at least be checked.
2) Add implementations for BeginWait(All) to check for the error
   case of a bad unit number and nonzero ID=.
3) Rearrange and comment SetAsynchronous so that it's clear that
   it can be called for READ/WRITE as well as for OPEN.

The implementation remains completely synchronous, but should be conforming.
Where opportunities make sense for true asynchronous implementations of
some big block transfers without SIZE= in the future, we'll need to add
a GetAsynchronousId API to capture ID= on a READ or WRITE; add sourceFile
and sourceLine arguments to BeginWait(All) for good error reporting;
track pending operations in unit.h; and add code to force synchronization
to non-asynchronous I/O operations.

Lowering should call SetAsynchronous when ASYNCHRONOUS= appears as
a control list specifier.  It should also set ID=x variables to 0
until such time as we support asynchronous operations, if ever.
This patch only removes the removed APIs from lowering.

Differential Revision: https://reviews.llvm.org/D126143
The file was modifiedflang/runtime/io-api.cpp
The file was modifiedflang/runtime/iostat.cpp
The file was modifiedflang/include/flang/Runtime/io-api.h
The file was modifiedflang/lib/Lower/IO.cpp
The file was modifiedflang/runtime/io-stmt.h
The file was modifiedflang/runtime/unit.h
The file was modifiedflang/runtime/io-error.h
The file was modifiedflang/include/flang/Runtime/iostat.h
Commit 57d239e4ad110c052fe0c05fb25a588ec5a8de14 by tzuhsiang.chien
[mlir] Breakdown diagnostic string literals

This commit breaks down diagnostic string literals so that the attribute
name and enumurator names can be shared with the stringify utility
function and the "expected ", " to be one of ", and ", " can be shared
between different enum-related diagnostic.

Differential Revision: https://reviews.llvm.org/D125938
The file was modifiedmlir/include/mlir/IR/EnumAttr.td
Commit 96bbe1bd61c6ec8898e9157b921a7782ea09b158 by jeffniu22
[mlir] Rename mlir::SmallVector -> llvm::SmallVector
The file was modifiedmlir/include/mlir/Interfaces/InferTypeOpInterface.td
The file was modifiedmlir/include/mlir/Interfaces/SideEffectInterfaceBase.td
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Commit dc8a9a03ecdba4280ae15b890725ae30ad55ff60 by Louis Dionne
[libc++][NFC] Move definitions around in string.cpp to reduce _LIBCPP_HAS_NO_WIDE_CHARACTERS blocks
The file was modifiedlibcxx/src/string.cpp
Commit 63251840494216af0d063503faee21f58a915c3c by Louis Dionne
[libc++][NFC] Whitespace refactoring of string.cpp for consistency and legibility
The file was modifiedlibcxx/src/string.cpp
Commit 154f93ca90e088ae64fc215a6a98ec60892f1c8a by thakis
[gn build] (semi-automatically) port 0360b9f1599b
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/pseudo/lib/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/pseudo/unittests/BUILD.gn
Commit a1a14e817eeb5a0663b1342a125674348b8aac06 by Cyndy Ishida
[Clang] Avoid misleading 'conflicting types' diagnostic with no-prototype decls.

Clang has recently started diagnosing prototype redeclaration errors like [rG385e7df33046](https://reviews.llvm.org/rG385e7df33046d7292612ee1e3ac00a59d8bc0441)

This flagged legitimate issues in a codebase but was confusing to resolve because it actually conflicted with a function declaration from a system header and not from the one emitted with "note: ".

This patch updates the error handling to use the canonical declaration's source location instead to avoid misleading errors like the one described.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D126258
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/Sema/prototype-redecls.c
Commit 574f9dfee86a8084b8fca43c850f8a3387c6c68b by pklausler
[flang] Extension: Accept Hollerith actual arguments as if they were BOZ

When a Hollerith (or short character) literal is presented as an actual
argument that corresponds to a dummy argument for which a BOZ literal
would be acceptable, treat the Hollerith as if it had been a BOZ
literal in the same way -- and with the same code -- as f18 already
does for the similar extension in DATA statements.

Differential Revision: https://reviews.llvm.org/D126144
The file was modifiedflang/lib/Semantics/check-call.cpp
The file was modifiedflang/lib/Evaluate/tools.cpp
The file was modifiedflang/include/flang/Evaluate/tools.h
The file was modifiedflang/lib/Semantics/check-call.h
The file was modifiedflang/lib/Semantics/data-to-inits.cpp
Commit 1b976f2cb22fb022421380caec8254f20f6754b5 by thakis
[gn build] Reformat all build files

Ran:

    git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Support/BLAKE3/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/utils/llvm-lit/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/pseudo/tool/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/lldb/source/Plugins/Platform/gdb-server/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/tools/clang-offload-packager/BUILD.gn
Commit cddeb78e8d5b7b924c920fb702d3d883b2661b12 by craig.topper
[RISCV] Add test cases showing failure to remove mask on rotate amounts.

This is similar to tests I added in
e2f410feeab27a8bb2c015fc02bb8527702e401f that had to be reverted.

I've modified them to avoid the bug that is being fixed by D126036.
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll
Commit 415b9f595d4d2fae947f86b239777ec54c3824dc by craig.topper
Recommit "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates."

This reverts commit dfe513ae1bb6e788ead93b850d80d77d54cf29d3.

Tests have been changed to avoid the type legalization bug being
fixed in D126036.

Original commit message:
This will remove masks on the shift amount. We usually get this with
SimplifyDemandedBits in DAGCombine, but that's restricted to cases
where the AND has a single use. selectShiftMaskXLen does not have
that restriction.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZb.td
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll
Commit 28432b0f655641df7f9d079cf69ba235038d6340 by paul.robinson
[PS5] Verify defaults to -fno-stack-size-section
The file was modifiedclang/test/Driver/stack-size-section.c
Commit d90e866a191fb77bb20140c6a955a4b3258c6ee3 by pklausler
[flang][runtime] INQUIRE(UNIT=666,NUMBER=n) must set n=666

Whether a unit number in an inquire-by-unit statement is valid or not,
it should be the value to which the NUMBER= variable is set, not -1.
-1 should be returned to NUMBER= only for an inquire-by-file statement
when the FILE= is not connected to any unit.

Differential Revision: https://reviews.llvm.org/D126145
The file was modifiedflang/runtime/io-stmt.h
The file was modifiedflang/runtime/io-stmt.cpp
The file was modifiedflang/runtime/io-api.cpp
Commit 11dd508bd43d606b8a2f52f4d0cf7471f78aca16 by chris.bieneman
NFC. Clang-formatting.

Since the rest of the DirectX backend is pretty well clang-format
clean, this file should be too.
The file was modifiedllvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
Commit efebb27b745a0d677ad2ea9aefff242c12aef29c by paul.robinson
Revert "[PS5] Verify defaults to -fno-stack-size-section"

This reverts commit 28432b0f655641df7f9d079cf69ba235038d6340.

Caused some unexpected buildbot failures.
The file was modifiedclang/test/Driver/stack-size-section.c
Commit ee8524087c78a673fcf5486ded69ee597a85e0f1 by Alex Lorenz
[libclang] add supporting for indexing/visiting C++ concepts

This commit builds upon recently added indexing support for C++ concepts
from https://reviews.llvm.org/D124441 by extending libclang to
support indexing and visiting concepts, constraints and requires
expressions as well.

Differential Revision: https://reviews.llvm.org/D126031
The file was modifiedclang/tools/libclang/CursorVisitor.h
The file was modifiedclang/tools/libclang/CXCursor.cpp
The file was modifiedclang/include/clang-c/Index.h
The file was modifiedclang/tools/c-index-test/c-index-test.c
The file was modifiedclang/tools/libclang/CXIndexDataConsumer.h
The file was addedclang/test/Index/index-concepts.cpp
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was modifiedclang/tools/libclang/CXIndexDataConsumer.cpp
The file was addedclang/test/Index/index-concept-kind.cpp
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
Commit 5df6669d45bc72df8a9ac7fb0f4f4cfc00444e0d by Stanislav.Mekhanoshin
[AMDGPU] Enforce alignment of image vaddr on gfx90a

Even though single address image instructions only use a single VGPR
HW accesses 4 or 5 which creates alignment requirement.

Fixes: SWDEV-316648

Differential Revision: https://reviews.llvm.org/D126009
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
Commit 4a3e2aff5f849278f6c49678fd21f8ca5e59c4e7 by paul.robinson
Reland "[PS5] Verify defaults to -fno-stack-size-section"

This reverts commit efebb27b745a0d677ad2ea9aefff242c12aef29c.
Fixes typos (accidentally omitted %s from some RUN lines).
The file was modifiedclang/test/Driver/stack-size-section.c
Commit 175833ed6f62b697ce6248930da54e4ddb7f4c00 by zeratul976
[clangd] Handle '--' in QueryDriverDatabase

Fixes https://github.com/clangd/clangd/issues/1100,
a regression from D116721.

Differential Revision: https://reviews.llvm.org/D126274
The file was modifiedclang-tools-extra/clangd/QueryDriverDatabase.cpp
Commit c8644ea88ea220a28ef41b7364ca2eb1071552f9 by leonardchan
[compiler-rt][lsan] Update CanBeAHeapPointer for AArch64

While attempting to get the 64-bit lsan allocator working for Fuchsia, I
noticed this function would incorrectly return false for pointers returned
by the 64-bit allocator. On AArch64, this function attempts to get the VMA
size dynamically by counting the number of leading zeros from the function
frame address. This will fail if the frame address is significantly below an
allocated pointer (that is, the frame address has more leading zeros than an
allocated pointer). This is possible on Fuchsia and linux (when not called
from the initial thread stack).

It seems the intended use of this function is to speed up pointer scanning by
filtering out addresses that user code might not be able to access. Other
platforms this check is done on seem to hardcode the VMA size/shift, so it
seems appropriate to do this for aarch64 as well. This implies pointers on
aarch64 where the VMA size is <64 will pass through, but bad pointers will
still be caught by subsequent scan checks.

This patch also renames the function to something more fitting of what it's
trying to do.

Differential Revision: https://reviews.llvm.org/D123814
The file was modifiedcompiler-rt/lib/lsan/lsan_common.cpp
Commit 8527f9e4437fbecb529babb674777eb2cab99ca5 by pklausler
[flang][runtime] Handle BACKSPACE after reading past EOF

An external READ(END=) that hits the end of the file must
also note the virtual position of the endfile record that
has just been discovered, so that a later BACKSPACE statement
won't end up at the wrong record.

Differential Revision: https://reviews.llvm.org/D126146
The file was modifiedflang/runtime/unit.cpp
The file was modifiedflang/runtime/unit.h
Commit 9ba937112fa6d4076e4a98b587a334786b6c0d9c by michael.p.rice
[OpenMP] Add parsing/sema support for omp_all_memory reserved locator

Adds support for the reserved locator 'omp_all_memory' for use
in depend clauses with 'out' or 'inout' dependence-types.

Differential Revision: https://reviews.llvm.org/D125828
The file was modifiedclang/lib/AST/OpenMPClause.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/test/OpenMP/task_depend_messages.cpp
The file was modifiedclang/include/clang/Basic/OpenMPKinds.def
The file was modifiedclang/include/clang/AST/OpenMPClause.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/test/OpenMP/task_ast_print.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
Commit 3723868d9e07de5d4a7468a4c2c74fc8517afc14 by jhuber6
[OpenMP] Fix file arguments for embedding bitcode in the linker wrapper

Summary:
The linker wrapper supports embedding bitcode images instead of linked
device images to facilitate JIT in the device runtime. However, we were
incorrectly passing in the file twice when this option was set. This
patch makes sure we only use the intermediate result of the LTO pass and
don't add the final output to the full job.

In the future we will want to add both of these andle handle that
accoridngly to allow the runtime to either use the AoT compiled version
or JIT compile the bitcode version if availible.
The file was modifiedclang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Commit b159108bc5ebd7f37373896ece1da8f49612f7a6 by Saleem Abdulrasool
Sema: adjust assertion to account for deduced types

Previous changes for the BTF attributes introduced a new sub-tree
visitation.  That uncovered that when accessing the typespec location we
would assert that the type specification is either a type declaration or
`typename`.  However, `typename` was explicitly permitted.  This change
predates the introduction of newer deduced type representations such as
`__underlying_type` from C++ and the addition of the GNU `__typeof__`
expression.

Thanks to aaron.ballman for the valuable discussion and pointer to
`isTypeRep`.

Differential Revision: https://reviews.llvm.org/D126093
Reviewed By: aaron.ballman, yonghong-song
The file was addedclang/test/Sema/typerep-typespec.c
The file was modifiedclang/include/clang/Sema/DeclSpec.h
Commit f6038cdca03115da22b9e6ada5c25de4df5f42d2 by leonardchan
[compiler-rt][scudo] Simplify TBI checks

Differential Revision: https://reviews.llvm.org/D111080
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 26c4cf23915a598ec4bba01342f4166902bd5dbe by Stanislav.Mekhanoshin
[AMDGPU] Disable newly added gfx90a global isel image tests. NFC.

This fixed build failure with expensive checks after D126009.
The change has added new run lines for Global ISel which has
uncovered a pre-existing problem: it does not select a correct
flavor of these image instructions.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
Commit 1e1f60c605a9b1c803f3bbb1a1339c9bb1af4e34 by vdonaldson
[flang] Alternate entry points with unused arguments

A dummy argument in an entry point of a subprogram with multiple
entry points need not be defined in other entry points. It is only
legal to reference such an argument when calling an entry point that
does have a definition. An entry point without such a definition
needs a local "substitute" definition sufficient to generate code.
It is nonconformant to reference such a definition at runtime.
Most such definitions and associated code will be deleted as dead
code at compile time. However, that is not always possible, as in
the following code. This code is conformant if all calls to entry
point ss set m=3, and all calls to entry point ee set n=3.

subroutine ss(a, b, m, d, k) ! no x, y, n
  integer :: a(m), b(a(m)), m, d(k)
  integer :: x(n), y(x(n)), n
  integer :: k
1 print*, m, k
  print*, a
  print*, b
  print*, d
  if (m == 3) return
entry ee(x, y, n, d, k) ! no a, b, m
  print*, n, k
  print*, x
  print*, y
  print*, d
  if (n /= 3) goto 1
end

  integer :: xx(3), yy(5), zz(3)
  xx = 5
  yy = 7
  zz = 9
  call ss(xx, yy, 3, zz, 3)
  call ss(xx, yy, 3, zz, 3)
end

Lowering currently generates fir::UndefOp's for all unused arguments.
This is usually ok, but cases such as the one here incorrectly access
unused UndefOp arguments for m and n from an entry point that doesn't
have a proper definition.

The problem is addressed by creating a more complete definition of an
unused argument in most cases. This is implemented in large part by
moving the definition of an unused argument from mapDummiesAndResults
to mapSymbolAttributes. The code in mapSymbolAttributes then chooses
one of three code generation options, depending on information
available there.

This patch deals with dummy procedures in alternate entries, and adds
a TODO for procedure pointers (the PFTBuilder is modified to analyze
procedure pointer symbol so that they are not silently ignored, and
instead hits proper TODOs).

BoxAnalyzer is also changed because assumed-sized arrays were wrongfully
categorized as constant shape arrays.  This had no impact, except when
there were unused entry points.

Co-authored-by: jeanPerier <jperier@nvidia.com>

Differential Revision: https://reviews.llvm.org/D125867
The file was modifiedflang/lib/Lower/PFTBuilder.cpp
The file was modifiedflang/lib/Lower/ConvertVariable.cpp
The file was modifiedflang/lib/Lower/Bridge.cpp
The file was modifiedflang/include/flang/Lower/BoxAnalyzer.h
The file was addedflang/test/Lower/dummy-procedure-in-entry.f90
The file was modifiedflang/test/Lower/entry-statement.f90
The file was modifiedflang/include/flang/Lower/PFTBuilder.h
The file was modifiedflang/lib/Lower/ConvertType.cpp
Commit 03095bd97b81b40d74762713b6ed72adb59df658 by pklausler
[flang] Fix crash in semantics after PDT instantiation

The code in semantics that reinitializes symbol table pointers in
the parse tree of a parameterized derived type prior to a new
instantiation of the type was processing the symbols of the
derived type instantiation scope in arbitrary address order,
which could fail if a reference to a type parameter inherited from
an ancestor type was processed prior to the parent component sequence.
Fix by instantiating components of PDT instantiations in declaration
order.

Differential Revision: https://reviews.llvm.org/D126147
The file was modifiedflang/lib/Semantics/type.cpp
Commit 67be40df6eefe375a0c97341940922f0ef7775a4 by apostolakis
Recommit "[SelectOpti][5/5] Optimize select-to-branch transformation"

Use container::size_type directly to avoid type mismatch causing build failures in Windows.

Original commit message:
This patch optimizes the transformation of selects to a branch when the heuristics deemed it profitable.
It aggressively sinks eligible instructions to the newly created true/false blocks to prevent their
execution on the common path and interleaves dependence slices to maximize ILP.

Depends on D120232

Reviewed By: davidxl

Differential Revision: https://reviews.llvm.org/D120233
The file was modifiedllvm/lib/CodeGen/SelectOptimize.cpp
The file was modifiedllvm/test/CodeGen/X86/select-optimize.ll
Commit 676eaa2ca967ca6ad4a84d31d6f0ebabdcf3e44b by leonardchan
[compiler-rt][scudo] Add missing preprocessor token

This should fix build errors seen on bots like
https://lab.llvm.org/buildbot/#/builders/57/builds/18263.
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 6edbdf80cac119f8f30d2ae6fa2972d9e778510b by leonardchan
Revert "[compiler-rt][scudo] Add missing preprocessor token" and "[compiler-rt][scudo] Simplify TBI checks"

This reverts commit 676eaa2ca967ca6ad4a84d31d6f0ebabdcf3e44b
and f6038cdca03115da22b9e6ada5c25de4df5f42d2 since builders are still
broken.
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 05527b68a0be19fe49b884f3b22195701dc4b46f by spatel
[InstCombine] fold more shuffles with FP<->Int cast operands

shuffle (cast X), (cast Y), Mask --> cast (shuffle X, Y, Mask)

This extends the transform added with 0353c2c996c5.

If the shuffle reduces vector length, the transform
reduces the width of the cast, so that should be a
win for most codegen (if not, it can be inverted).
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit 9df0568b073307dd9390e7d670873e40b65c9f95 by vporpodas
[SLP] Fix crash caused by reorderBottomToTop().

The crash is caused by incorrect order set by reorderBottomToTop(), which
happens when it is reordering a TreeEntry which has a user that has already been
reordered earlier. Please see the detailed description in the lit test.

Differential Revision: https://reviews.llvm.org/D126099
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was addedllvm/test/Transforms/SLPVectorizer/X86/reorder_with_reordered_users.ll
Commit c428620913ba318a7d6d2a2164b56ff116f90c56 by pklausler
[flang] Catch calls to assumed-length character functions

Semantics was allowing calls to CHARACTER(*) functions, which are odd
things -- they can be declared, and passed around, but can never actually
be called as such.  They must be redeclared with an explicit length that
ends up being passed as a hidden argument.  So check for these calls
and diagnose them, add tests, and clean up some existing tests that
were in error and now get caught.

Possible TODO for lowering: there were some test cases that used
bad calls to assumed-length CHARACTER*(*) functions and validated
their implementations.  I've removed some, and adjusted another,
but the code that somehow implemented these calls may need to be
removed and replaced with an assert about bad semantics.

Differential Revision: https://reviews.llvm.org/D126148
The file was modifiedflang/test/Lower/dummy-procedure-character.f90
The file was modifiedflang/lib/Semantics/expression.cpp
The file was modifiedflang/test/Lower/host-associated.f90
The file was modifiedflang/test/Lower/dummy-procedure-in-entry.f90
The file was modifiedflang/test/Evaluate/rewrite01.f90
The file was modifiedflang/test/Semantics/call01.f90
Commit 8246b2e156568c31e71e16cbaf4c14d316e7c06e by m_borsa
[Sanitizers][Darwin] Replace SANITIZER_MAC with SANITIZER_APPLE in source files

This is a follow up to [Sanitizers][Darwin] Rename Apple macro SANITIZER_MAC -> SANITIZER_APPLE (D125816)

Performed a global search/replace as in title against LLVM sources

Differential Revision: https://reviews.llvm.org/D126263
The file was modifiedcompiler-rt/lib/lsan/lsan_common.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
The file was modifiedcompiler-rt/lib/asan/asan_flags.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_interceptors_libdispatch.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_platform.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_flags.inc
The file was modifiedcompiler-rt/lib/asan/asan_mac.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_malloc_mac.cpp
The file was modifiedcompiler-rt/lib/interception/interception_win.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_procmaps_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_interceptors.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_mac.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.h
The file was modifiedcompiler-rt/lib/ubsan/ubsan_value.cpp
The file was modifiedcompiler-rt/lib/asan/tests/asan_noinst_test.cpp
The file was modifiedcompiler-rt/lib/asan/asan_new_delete.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_malloc_mac.cpp
The file was modifiedcompiler-rt/lib/xray/xray_init.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_libignore.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common_mac.cpp
The file was modifiedcompiler-rt/lib/interception/interception_type_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/asan/asan_mapping.h
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_flags.inc
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_libdispatch.cpp
The file was modifiedcompiler-rt/lib/interception/interception_mac.h
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_rtl.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_flags.inc
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_interceptors_mac.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_procmaps_mac.cpp
The file was modifiedcompiler-rt/lib/xray/xray_basic_logging.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_mac.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/xray/xray_x86_64.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_dispatch_defs.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac_libcdep.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_malloc_mac.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
The file was modifiedcompiler-rt/lib/interception/interception.h
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_report.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_report.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_mac.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
The file was modifiedcompiler-rt/lib/asan/asan_interceptors.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_errno.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_mac_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_syscall_generic.inc
The file was modifiedcompiler-rt/lib/asan/asan_flags.inc
The file was modifiedcompiler-rt/lib/asan/asan_malloc_mac.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_unwind_linux_libcdep.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/asan/tests/asan_test_main.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_procmaps.h
The file was modifiedcompiler-rt/lib/asan/asan_interceptors.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_common_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl-old/tsan_platform_mac.cpp
The file was modifiedcompiler-rt/lib/interception/interception_mac.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_mac.cpp
Commit 6eb9e0f5ebb94cccf52ea27aa342001b84c1c8b1 by yitzhakm
[clang][dataflow] Make limit on fixpoint-algorithm iterations proportional to size of CFG.

Currently, the maximum number of iterations of the loop for finding the fixpoint
of the dataflow analysis is set at 2^16. When things go wrong in an analysis,
this can be far too large.  This patch changes the limit to be proportional to
the size of the CFG, which will generally be far smaller than 2^16 (while still
maintaining 2^16 as the absolute limit).

Differential Revision: https://reviews.llvm.org/D126316
The file was modifiedclang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp
Commit cd2a8df8916505de9df68b9a6c1700f71e5ebf44 by pklausler
[flang] Don't prematurely resolve subprogram names

Name resolution for subprograms checks whether the name is already
present in the enclosing scope as a generic interface, so that the
case of a generic with the same name as one of its specifics can be
handled.  The particular means by which the enclosing scope is searched
for the name would resolve the name (bind a symbol to it) as a side
effect.  This turns out to be the wrong thing to do when the subprogram
is going to have its symbol created in another scope to cope with its
BIND(C,NAME="name") name, and its Fortran name is already present in the
enclosing scope for a subprogram of the same name but without
BIND(C,NAME="name").

A very long explanation for a one-line fix, sorry.  In short, change
the code to look up the name but not resolve it at that point.

Differential Revision: https://reviews.llvm.org/D126149
The file was modifiedflang/lib/Semantics/resolve-names.cpp
Commit 1b34f1e996565bc5e4f2be14b89f881f8fe0f3b9 by Alex Lorenz
[clang][test] mark tests added in ee8524087c78 as unsupported on AIX

These tests are failing on the PPC64 AIX CI bot, but it's unclear why,
as they pass on other CI jobs.
I marked them as unsupported on AIX for now while investigating the failure.
The file was modifiedclang/test/Index/index-concept-kind.cpp
The file was modifiedclang/test/Index/index-concepts.cpp
Commit bd92bca53517bfbce3396d9f87f42fa438e8d1fd by pklausler
[flang] Fix purity testing for generic calls

The purity or impurity of a call to a generic interface
depends on the attributes of the specific procedure or specific
binding.  Change expression analysis of calls to generic interfaces
to replace the symbol in the parse tree with the specific procedure
or binding; this ensures that later checking for purity in
DO CONCURRENT and other contexts will be accurate.

Remove an "XFAIL" from a test that now passes again with this fix.

Differential Revision: https://reviews.llvm.org/D126150
The file was addedflang/test/Semantics/doconcurrent09.f90
The file was modifiedflang/lib/Semantics/expression.cpp
Commit 48a8a3eb2f5646c9ac847a07f42316a81e025c23 by pklausler
[flang] Accept defined assignment with CLASS(*) RHS

A utility predicate in semantics was incorrectly determining that
an INTERFACE ASSIGNMENT(=) (or other form of generic) could not have
a specific procedure with an unlimited polymorphic second argument.
This led to a crash later in expression analysis.  Fix, and
extend tests.

Differential Revision: https://reviews.llvm.org/D126151
The file was modifiedflang/lib/Semantics/tools.cpp
The file was modifiedflang/test/Semantics/defined-ops.f90
Commit dcf9ba82d99c2b4625b2e0c00c44a469048f2827 by pklausler
[flang] Fix false error for multiple defined I/O subroutines

User-defined derived type I/O subroutines need to be unique for
a given type and operation in any scope, but it is acceptable
to have more than one defined I/O subroutine so long as only one
of them is visible.

Differential Revision: https://reviews.llvm.org/D126152
The file was modifiedflang/lib/Semantics/check-declarations.cpp
The file was modifiedflang/test/Semantics/io11.f90
Commit 2f93bbb9cd7c20ea1a273cf652d852d4b641f94a by yitzhakm
[clang][dataflow] Relax `Environment` comparison operation.

Ignore `MemberLocToStruct` in environment comparison. As an ancillary data
structure, including it is redundant. We also can generate environments which
differ in their `MemberLocToStruct` but are otherwise equivalent.

Differential Revision: https://reviews.llvm.org/D126314
The file was modifiedclang/unittests/Analysis/FlowSensitive/TransferTest.cpp
The file was modifiedclang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
Commit d52a6e75b0c402c7f3b42a2b1b2873f151220947 by pklausler
[flang] Process subprogram BIND(C,NAME=...) locally

The scalar-default-character-expression that defines the interoperable
name of a function or subroutine (or interface) must have its names
resolved within the context of the subprogram, despite its appearance
on a function-stmt or a subroutine-stmt.  Failure to do so can lead
to bogus errors or to incorrect results.

The solution is to defer name resolution for function-stmt suffixes
(but not entry-stmt suffixes) and for subroutine-stmt language binding
specifications to EndSubprogram().  (Their resolution only need to be
deferred to the end of the specification part, but it's cleanest to
deal with it in EndSubprogram().)

Differential Revision: https://reviews.llvm.org/D126153
The file was modifiedflang/test/Lower/program-units-fir-mangling.f90
The file was modifiedflang/lib/Semantics/resolve-names.cpp
Commit 0a79113b9e064e50f660ebe6e257bf69ba028026 by pklausler
[flang] Replace crash and improve a semantics TODO message

The derived type information table construction code had a
crash whose root cause was replacing an expression with one
of its operands -- the deletion of the LHS of that assignment
led to the RHS being invalidated before it could be read.
Fix by cloning the RHS.  Also update a TODO message to the
new "_todo_en_US" message class and add a comment about how
it should be resolved.

Differential Revision: https://reviews.llvm.org/D126154
The file was modifiedflang/lib/Semantics/runtime-type-info.cpp
Commit cdd54cbdd937f7473e0ba065ecafc70742f3f1fd by pklausler
[flang][runtime] Catch decimal integer input overflow

B/O/Z input overflow is already caught, and real input overflow
is signalled as an IEEE arithmetic exception, but regular decimal
integer overflow was silent.

Differential Revision: https://reviews.llvm.org/D126155
The file was modifiedflang/runtime/edit-input.cpp
The file was modifiedflang/runtime/iostat.cpp
The file was modifiedflang/include/flang/Runtime/iostat.h
Commit 0bf3c38b0be3f9b45b589b780ed53f2de4d364d4 by amy.kwan1
Fix build failure revealed by c35ca3a1c78f693b749ad11742350b7fc6c5cd89

This commit resolves a Linux kernel build failure that was revealed by
c35ca3a1c78f693b749ad11742350b7fc6c5cd89. The patch introduces two new
intrinsics, which ultimately changes the intrinsic numbering of other PPC
intrinsics. This causes an issue introduced by
ff40fb07ad6309131c2448ca00572a078c7a2d59, as the patch checks for intrinsics
with particular values, but the addition of the fnabs/fnabss intrinsics updates
the original sqrt/sdiv intrinsic values.
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 29f167abcf7d871d17dd3f38f361916de1a12470 by kiran.chandramohan
[Flang][OpenMP] Fixes for unstructured OpenMP code

Since the FIR operations are mostly structured, it is only the functions
that could contain multiple blocks inside an operation. This changes
with OpenMP since OpenMP regions can contain multiple blocks. For
unstructured code, the blocks are created in advance and belong to the
top-level function. This caused code in OpenMP region to be placed under
the function level.

In this fix, if the OpenMP region is unstructured then new blocks are
created inside it.

Note1: This is part of upstreaming from the fir-dev branch of
https://github.com/flang-compiler/f18-llvm-project. The code in this patch is a
subset of the changes in https://github.com/flang-compiler/f18-llvm-project/pull/1178.

Reviewed By: vdonaldson

Differential Revision: https://reviews.llvm.org/D126293

Co-authored-by: Val Donaldson <vdonaldson@nvidia.com>
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>
The file was addedflang/test/Lower/OpenMP/omp-unstructured.f90
The file was modifiedflang/lib/Lower/OpenMP.cpp
Commit 6f215ca680fdda6eff0114bbd9d26a3efd8b21be by paul.walker
[SelectionDAG] Add support to widen ISD::STEP_VECTOR operations.

Fixes: #55165

Differential Revision: https://reviews.llvm.org/D126168
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-stepvector.ll
Commit a95ecb20bca894cc1373a85360ad5939dd2c3ff9 by listmail
[RISCV] Hoist VSETVLI out of idiomatic fixed length vector loops

This patch teaches the VSETVLI insertion pass to perform a very limited form of partial redundancy elimination. The motivating example comes from the fixed length vectorization of a simple loop such as:

for (unsigned i = 0; i < a_len; i++)
    a[i] += b;

Without this change, the core vector loop and preheader is as follows:

.LBB0_3:                                # %vector.ph
andi a1, a6, -8
addi a4, a0, 16
mv a5, a1
.LBB0_4:                                # %vector.body
                                        # =>This Inner Loop Header: Depth=1
addi a3, a4, -16
vsetivli zero, 4, e32, m1, ta, mu
vle32.v v8, (a3)
vle32.v v9, (a4)
vadd.vx v8, v8, a2
vadd.vx v9, v9, a2
vse32.v v8, (a3)
vse32.v v9, (a4)
addi a5, a5, -8
addi a4, a4, 32
bnez a5, .LBB0_4

The key thing to note here is that, the execution of the vsetivli only needs to happen once. Since there's no tail folding happening here, the value of the vector configuration registers are invariant through the loop.

After this patch, we hoist the configuration into the preheader and perform it once.

.LBB0_3:                                # %vector.ph
andi a1, a6, -8
vsetivli zero, 4, e32, m1, ta, mu
addi a4, a0, 16
mv a5, a1
.LBB0_4:                                # %vector.body
                                        # =>This Inner Loop Header: Depth=1
addi a3, a4, -16
vle32.v v8, (a3)
vle32.v v9, (a4)
vadd.vx v8, v8, a2
vadd.vx v9, v9, a2
vse32.v v8, (a3)
vse32.v v9, (a4)
addi a5, a5, -8
addi a4, a4, 32
bnez a5, .LBB0_4

Differential Revision: https://reviews.llvm.org/D124869
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
Commit fb948572e03321b1470a2e47fbf685226f8f5f18 by listmail
[riscv] Use getFirstInstrTerminator [nfc]
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit d2ee2c9c8d34bc915a3d7c00951831eb24708f6a by craig.topper
[RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt.

Instead of matching opcodes to know the format to emit, use an
enum value that we can get from the RISCVMatInt::Inst class.

Change the consumers to use fully covered switches so that we get
a compiler warning if a new kind is added. With the opcode checks
it was easier to forget to update one of the 3 consumers.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126317
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
Commit 5799f843a22029bd51d45edcd773e3c8662a0a08 by ajcbik
[mlir][sparse] add new complex ops to reduction recognition

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D126318
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
Commit 948d931323a13dfc68430814a44b9075a59e2310 by listmail
[RISCV] Ensure the forwarded AVL register is alive

When the AVL value does not fit in 5 bits, the register in which this value is stored may be dead when we want to forward it. This patch ensure the kill flags on the register are cleared before forwarding.

Patch by: loralb
Differential Revision: https://reviews.llvm.org/D125971
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 239094cdee8e3f5de4a6757f43b94cc21f9a808f by michael.p.rice
[OpenMP] Add codegen for 'omp_all_memory' reserved locator.

This creates an entry with address=nullptr and flag=0x80.
When an 'omp_all_memory' entry is specified any other 'out' or
'inout' entries are not needed and are not passed to the runtime.

Differential Revision: https://reviews.llvm.org/D126321
The file was modifiedclang/test/OpenMP/task_codegen.cpp
The file was modifiedclang/test/OpenMP/target_update_depend_codegen.cpp
The file was modifiedclang/test/OpenMP/target_enter_data_depend_codegen.cpp
The file was modifiedclang/test/OpenMP/task_if_codegen.cpp
The file was modifiedclang/test/OpenMP/depobj_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/test/OpenMP/interop_irbuilder.cpp
The file was modifiedclang/test/OpenMP/target_exit_data_depend_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/test/OpenMP/task_codegen.c
Commit 2a5d5078d5dadb1aaa4487c89a92c91a98e2ed12 by sivachandra
[libc] Add the pthread_mutex_t type.

Simple implementations of the functions pthread_mutex_init,
pthread_mutex_destroy, pthread_mutex_lock and pthread_mutex_unlock have
have also been added. Future patches will extend these functions to add
features required by the POSIX specification.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D126235
The file was modifiedlibc/spec/posix.td
The file was modifiedlibc/include/llvm-libc-types/__mutex_type.h
The file was addedlibc/src/pthread/pthread_mutex_destroy.h
The file was addedlibc/include/llvm-libc-types/pthread_mutex_t.h
The file was modifiedlibc/src/pthread/pthread_mutexattr.h
The file was addedlibc/src/pthread/pthread_mutex_init.cpp
The file was addedlibc/src/pthread/pthread_mutex_lock.cpp
The file was addedlibc/src/pthread/pthread_mutex_unlock.h
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was addedlibc/src/pthread/pthread_mutex_lock.h
The file was modifiedlibc/test/src/pthread/CMakeLists.txt
The file was modifiedlibc/include/CMakeLists.txt
The file was modifiedlibc/src/pthread/CMakeLists.txt
The file was addedlibc/src/pthread/pthread_mutex_destroy.cpp
The file was modifiedlibc/config/linux/api.td
The file was addedlibc/src/pthread/pthread_mutex_unlock.cpp
The file was addedlibc/test/src/pthread/pthread_mutex_test.cpp
The file was modifiedlibc/include/llvm-libc-types/CMakeLists.txt
The file was addedlibc/src/pthread/pthread_mutex_init.h
Commit 46c0ec9df46f5bb1d53ae5b98a337e23687bd3ff by msebor
[InstCombine] Fold memrchr calls with sequences of identical bytes.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D123631
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/memrchr-4.ll
Commit a9e354c83b9e158c690d83c69ad6f8b5c8d1daa6 by ajcbik
[mlir][sparse] complex lowering

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D126335
The file was modifiedmlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
Commit 9426df95b1b21ebbad6587ea95c80847fa550c47 by paul.walker
[LLVM][IR] Fix assert in ConstantExpr::getPtrToInt so all vector types are supported.

Fixes: #55410
The file was modifiedllvm/lib/IR/Constants.cpp
The file was modifiedllvm/unittests/IR/ConstantsTest.cpp
Commit b2b0322a8114af783d103435202b576167426c7f by browneee
[DFSan] Add option to specify individual library files, and an option to exit with an error code if any library file was not found.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D126336
The file was modifiedcompiler-rt/lib/dfsan/scripts/build-libc-list.py
Commit 9ff4f2dfea632d63e3a57a88a2faa634aae5c772 by mail
[clang-tidy] Fix #55134 (regression introduced by 5da7c04)

5da7c04 introduced a regression in the NOLINT macro checking loop, replacing the
call to `getImmediateExpansionRange().getBegin()` with
`getImmediateMacroCallerLoc()`, which has similar but subtly different
behaviour.

The consequence is that NOLINTs cannot suppress diagnostics when they are
attached to a token that came from a macro **argument**, rather than elsewhere
in the macro expansion.

Revert to pre-patch behaviour and add test cases to cover this issue.

Differential Revision: https://reviews.llvm.org/D126138
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
The file was modifiedclang-tools-extra/test/clang-tidy/infrastructure/nolint.cpp
The file was modifiedclang-tools-extra/clang-tidy/NoLintDirectiveHandler.cpp
Commit f179f403c8579c939e09d27c383b6263cf2523aa by Jonas Devlieghere
[lldb] Disable modules in Apple-lldb-base

The LLDB website recommends using the CMake caches to build on macOS.
Although modules result in a faster build, this configuration tends to
break occasionally because it's specific to our platform. I don't expect
newcomers to be able to deal with those kind of breakages so don't
enable them by default.
The file was modifiedlldb/cmake/caches/Apple-lldb-base.cmake
Commit 436eaf8d32fa8d5db6782f4da30d0b5b7c2690e8 by Jonas Devlieghere
[lldb] Improve TestAppleSimulatorOSType.py error message

This was inspired by D109336 which got reverted because we didn't want
the test to fail silently. This patch prints a more informative error
message when we fail to parse the simctl output while still failing the
test.

Differential revision: https://reviews.llvm.org/D126217
The file was modifiedlldb/test/API/tools/lldb-server/TestAppleSimulatorOSType.py
Commit b976fac6eec4d7bc636830dafec3cd1db541ee89 by aaupov
[BOLT][NFC] Remove unused BF::computeLocalUDChain method definition

The function is only used inside AArch64MCPlusBuilder class, there are no uses
of it as a BinaryFunction method.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D126220
The file was modifiedbolt/include/bolt/Core/BinaryFunction.h
Commit 5d8247d4c7c40d3f83fdffd1e337ee8cae7841d1 by aaupov
[BOLT][NFC] Use for_each to simplify printLoopInfo

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D126242
The file was modifiedbolt/lib/Core/BinaryFunction.cpp
Commit 69f87b6c292ba24ba96f9b90bfb395fd0810995b by aaupov
[BOLT][NFC] Customize endline character for printInstruction(s)

This would be used in `BF::dumpGraph` to dump left-justified text.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D126232
The file was modifiedbolt/lib/Core/BinaryContext.cpp
The file was modifiedbolt/include/bolt/Core/BinaryContext.h
Commit f7581a3969c49653060abe29eb69076330d76290 by aaupov
[BOLT][NFC] Use ListSeparator in BinaryFunction print methods

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D126243
The file was modifiedbolt/lib/Core/BinaryFunction.cpp
Commit bebf7bdf9aad4e5d3ae09140d5af4d03bfda9094 by owenca
[clang-format][NFC] Insert/remove braces in clang/lib/Format/

Differential Revision: https://reviews.llvm.org/D126157
The file was modifiedclang/lib/Format/QualifierAlignmentFixer.cpp
The file was modifiedclang/lib/Format/BreakableToken.cpp
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
The file was modifiedclang/lib/Format/ContinuationIndenter.cpp
The file was modifiedclang/lib/Format/SortJavaScriptImports.cpp
The file was modifiedclang/lib/Format/AffectedRangeManager.cpp
The file was modifiedclang/lib/Format/DefinitionBlockSeparator.cpp
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/lib/Format/FormatToken.cpp
The file was modifiedclang/lib/Format/WhitespaceManager.cpp
The file was modifiedclang/lib/Format/Format.cpp
The file was modifiedclang/lib/Format/UnwrappedLineFormatter.cpp
Commit 793bb7049db012df4fe3ff6e8abc320677845400 by Chenbing.Zheng
[InstCombine] add test for trunc-shl-trunc ; NFC
The file was modifiedllvm/test/Transforms/InstCombine/trunc-shift-trunc.ll
Commit 269e3f7369d2286a1e711a7fa0442ca64817ff9f by Chenbing.Zheng
[InstCombine] [NFC] Move transforms for truncated shifts into narrowBinOp

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126056
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit a1ffba8d528681d55c901a997beedbc69946eb90 by yedeng.yd
[C++20] [Coroutines] Conform the updates for CWG issue 2585

According to the updates in CWG issue 2585
https://cplusplus.github.io/CWG/issues/2585.html, we shouldn't find an
allocation function with (size, p0, …, pn) in global scope.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D126187
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was addedclang/test/CodeGenCoroutines/coro-alloc-2.cpp
Commit 80c4910f3d4c8b36120bcdb6670d15c693f0f0df by czhengsz
Revert "[MachineSink] replace MachineLoop with MachineCycle"

This reverts commit 62a9b36fcf728b104ea87e6eb84c0be69b779df7.
Cause build failure on lldb incremental buildbot:
https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/43994/changes
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/CodeGen/AArch64/loop-sink-limit.mir
The file was modifiedllvm/include/llvm/ADT/GenericCycleInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineSSAContext.h
The file was modifiedllvm/lib/CodeGen/MachineCycleAnalysis.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/include/llvm/ADT/GenericCycleImpl.h
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineCycleAnalysis.h
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/RISCV/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/x86-shrink-wrapping.ll
The file was modifiedllvm/test/CodeGen/X86/pr38795.ll
The file was modifiedllvm/test/CodeGen/X86/switch-phi-const.ll
Commit b06049bc3b79be4a037a60dec4ad19a68e196a8f by varconst
[libc++][NFC] Add more tests to `move_{iterator,sentinel}`.

More test coverage for the parts added by the One Ranges Proposal.

Differential Revision: https://reviews.llvm.org/D124906
The file was modifiedlibcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/iter_move.pass.cpp
The file was modifiedlibcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/ranges_uninitialized_move_n.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.incr/post.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/reverse.iterators/types.compile.pass.cpp
The file was modifiedlibcxx/include/__iterator/move_iterator.h
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/op_eq.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.star/op_star.pass.cpp
The file was modifiedlibcxx/include/__iterator/move_sentinel.h
The file was addedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.-/sentinel.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/ctor.sentinel.pass.cpp
The file was modifiedlibcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/ranges_uninitialized_move.pass.cpp
The file was addedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.nonmember/iter_move.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/ctor.default.pass.cpp
The file was addedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.conv/base.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.index/difference_type.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/assign.converting.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.inner/iter_swap.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/ctor.converting.pass.cpp
The file was addedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.nonmember/iter_swap.pass.cpp
The file was modifiedlibcxx/test/support/test_iterators.h
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.sentinel/base.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.inner/iter_move.pass.cpp
The file was removedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.conv/tested_elsewhere.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/iter_swap.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.const/default.pass.cpp
Commit e59f648d698efe58b96e9b6224449b2b8cfa872a by dblaikie
Move GCC-compatible pod-packing change to v15/old behavior available at v14 and below

Since this didn't make it into the v14 release - anyone requesting the
v14 ABI shouldn't get this GCC-compatible change that isn't backwards
compatible with v14 Clang.

Differential Revision: https://reviews.llvm.org/D126334
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
The file was modifiedclang/test/SemaCXX/class-layout.cpp
Commit fd937366579e68e4413cda13b1b78a74b234be81 by fraser
[RISCV] Replace untested code with assert

We found untested code where negative frame indices were ostensibly
handled despite it being in a block guarded by !MFI.isFixedObjectIndex.

While the implementation of MachineFrameInfo::isFixedObjectIndex
suggests this is possible (i.e., if a frame index was more negative - less than the
number of fixed objects), I couldn't find any test in tree -- for any
target -- where a negative frame index wasn't also a fixed object
offset. I couldn't find a way of creating such a object with the
public MachineFrameInfo creation APIs. Even
MachineFrameInfo::getObjectIndexBegin starts counting at the negative
number of fixed objects, so such frame indices wouldn't be covered by
loops using the provided begin/end methods.

Given all this, an assert that any object encountered in the block is
non-negative seems reasonable.

Reviewed By: StephenFan, kito-cheng

Differential Revision: https://reviews.llvm.org/D126278
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 360411957b6f40f50b35097b7abedd91250f2434 by llvm-project
[flang][MSVC] Fix building with `/permissive-` flag

CLOCK_REALTIME is POSIX defined and never available with MSVC, even without /permissive-.
The difference is that the template is never instantiated and the compiler ignores the undefined identifier.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D125262
The file was modifiedflang/runtime/time-intrinsic.cpp
Commit 66db5312bd6676cae721b3ad9f76b68af7909e7c by craig.topper
[RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL.

We were incorrectly using VLMax instead of the passed VL.

Reviewed By: khchen, reames

Differential Revision: https://reviews.llvm.org/D126319
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td