|
 | clang/lib/Format/QualifierAlignmentFixer.h (diff) |
| clang/lib/Format/QualifierAlignmentFixer.cpp (diff) |
| clang/unittests/Format/QualifierFixerTest.cpp (diff) |
|
| llvm/lib/Transforms/IPO/SampleProfileProbe.cpp (diff) |
Commit
7ff8094a397127c8204c34079f8893fc8acbf1dd
by github[flang][OpenMP] Add semantic check for declare target (#71861)
This patch adds the following check from OpenMP 5.2.
```
If the directive has a clause, it must contain at least one enter clause
or at least one link clause.
```
Also added a warning for the deprication of `TO` clause on `DECLARE
TARGET` construct.
```
The clause-name to may be used as a synonym for the clause-name enter.
This use has been deprecated.
```
Based on the tests for to clause, the tests for enter clause are added.
This patch does not add tests where both to and enter clause are used together.
|
| flang/test/Lower/OpenMP/declare-target-data.f90 (diff) |
| flang/test/Semantics/OpenMP/declare-target06.f90 (diff) |
| flang/lib/Semantics/check-omp-structure.h (diff) |
| flang/test/Semantics/OpenMP/requires04.f90 (diff) |
 | flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 |
| flang/test/Parser/OpenMP/declare_target-device_type.f90 (diff) |
| flang/test/Semantics/OpenMP/requires05.f90 (diff) |
| flang/lib/Lower/OpenMP.cpp (diff) |
| flang/test/Lower/OpenMP/declare-target-func-and-subr.f90 (diff) |
| flang/lib/Parser/openmp-parsers.cpp (diff) |
| flang/test/Lower/OpenMP/FIR/declare-target-data.f90 (diff) |
| flang/test/Lower/OpenMP/declare-target-implicit-tarop-cap.f90 (diff) |
| flang/test/Semantics/OpenMP/declare-target01.f90 (diff) |
| flang/lib/Semantics/check-omp-structure.cpp (diff) |
| flang/test/Lower/OpenMP/FIR/declare-target-func-and-subr.f90 (diff) |
| flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 |
| flang/test/Lower/OpenMP/function-filtering-2.f90 (diff) |
| flang/lib/Semantics/resolve-directives.cpp (diff) |
| llvm/include/llvm/Frontend/OpenMP/OMP.td (diff) |
| flang/test/Semantics/OpenMP/declare-target02.f90 (diff) |
| flang/test/Semantics/OpenMP/declarative-directive.f90 (diff) |
| flang/test/Lower/OpenMP/function-filtering.f90 (diff) |
|
| clang/lib/Driver/ToolChains/OpenBSD.cpp (diff) |
| clang/lib/Driver/ToolChains/DragonFly.cpp (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
|
| llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp (diff) |
Commit
b2bbe8cc1c7653fb33f8aef69bbf77c1d3af4f26
by Lang Hames[ORC-RT] Add bitmask-enum and bit_ceil utilities to the ORC runtime.
bitmask_enum.h is essentially a copy of llvm/ADT/BitmaskEnum.h, with some minor
cleanup and renaming.
The bit_ceil function is a placeholder for std::bit_ceil, which we can use once
compiler-rt can use c++20.
These utilities will be used to simplify bitfield enum usage in upcoming
ORC-RT patches.
|
| compiler-rt/lib/orc/tests/unit/bitmask_enum_test.cpp |
| compiler-rt/lib/orc/stl_extras.h (diff) |
| compiler-rt/lib/orc/bitmask_enum.h |
| compiler-rt/lib/orc/tests/unit/CMakeLists.txt (diff) |
|
| llvm/include/llvm-c/Orc.h (diff) |
Commit
4fe29d0dc2f65e60ae7dde63e7f4595446f3baca
by github[ASan] AddressSanitizerPass constructor should honor the AsanCtorKind argument (#72330)
Currently, the ConstructorKind member variable in AddressSanitizerPass
gets overriden by the ClConstructorKind whether the option is passed
from the command line or not. This override should only happen if the
ClConstructorKind argument is passed from the command line. Otherwise,
the constructor should honor the argument passed to it. This patch makes
this fix.
rdar://118423755
|
| llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp (diff) |
Commit
c5a67e16b6117d0c37d004dd5467b56be006ad8f
by github[mlir][sparse] Use variable instead of inlining sparse encoding (#72561)
Example:
#CSR = #sparse_tensor.encoding<{
map = (d0, d1) -> (d0 : dense, d1 : compressed),
}>
// CHECK: #[[$CSR.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0
: dense, d1 : compressed) }>
// CHECK-LABEL: func private @sparse_csr(
// CHECK-SAME: tensor<?x?xf32, **#[[$CSR]]**>)
func.func private @sparse_csr(tensor<?x?xf32, #CSR>)
|
| mlir/test/Dialect/SparseTensor/sparse_pack.mlir (diff) |
| mlir/test/Dialect/SparseTensor/vectorize_reduction.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir (diff) |
| mlir/test/Dialect/SparseTensor/one_trip.mlir (diff) |
| mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_foreach.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_parallel_reduce.mlir (diff) |
| mlir/test/Dialect/SparseTensor/GPU/gpu_matmul_lib.mlir (diff) |
| mlir/test/Dialect/SparseTensor/GPU/gpu_matvec_lib.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_3d.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_reshape.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_out.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_tensor_reshape.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_sddmm.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_perm.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_nd.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_index.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_1d.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_concat.mlir (diff) |
| mlir/test/Dialect/SparseTensor/fold.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_transpose.mlir (diff) |
| mlir/test/Dialect/SparseTensor/dense.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir (diff) |
| mlir/test/Dialect/SparseTensor/GPU/gpu_sddmm_lib.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_lower_col.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_lower.mlir (diff) |
| mlir/test/Dialect/SparseTensor/semi_ring.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_vector_index.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_scalars.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_sddmm_org.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_extract_slice.mlir (diff) |
| mlir/test/Dialect/SparseTensor/codegen.mlir (diff) |
| mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp (diff) |
| mlir/test/Dialect/SparseTensor/spy_sddmm.mlir (diff) |
| mlir/test/Dialect/SparseTensor/rewriting_for_codegen.mlir (diff) |
| mlir/test/Dialect/SparseTensor/unused-tensor.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir (diff) |
| mlir/test/Dialect/SparseTensor/GPU/gpu_sampled_matmul_lib.mlir (diff) |
| mlir/test/Dialect/SparseTensor/rejected.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sorted_coo.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_kernels.mlir (diff) |
| mlir/test/Dialect/SparseTensor/pre_rewriting.mlir (diff) |
| mlir/test/Dialect/SparseTensor/roundtrip.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_affine.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_2d.mlir (diff) |
| mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
Commit
c6f7b631a9c0757130a8a7bb6b0ccc10da340e42
by github[mlir][spirv] Fix VectorShuffle assembly format (#72568)
Align with the rest of the spirv dialect by using a functional type
syntax.
Regex for updating existing code:
`spirv\.VectorShuffle (\[.+\]) (%[^:]+): ([^,]+), (%[^:]+): ([^\s]+) ->(.+)`
==>
`spirv.VectorShuffle $1 $2, $4 : $3, $5 ->$6`
|
| mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td (diff) |
| mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir (diff) |
| mlir/test/Target/SPIRV/composite-op.mlir (diff) |
| mlir/test/Conversion/SPIRVToLLVM/misc-ops-to-llvm.mlir (diff) |
| mlir/test/Dialect/SPIRV/IR/composite-ops.mlir (diff) |
|
| mlir/include/mlir/Dialect/OpenACC/OpenACCOpsTypes.td (diff) |
| flang/test/Lower/OpenACC/HLFIR/acc-declare.f90 (diff) |
| flang/lib/Lower/OpenACC.cpp (diff) |
| mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td (diff) |
| mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp (diff) |
|
| compiler-rt/lib/orc/stl_extras.h (diff) |
Commit
83cf0dc98234bbd8cb0d0959baa570477a8daf92
by github[mlir][sparse] implement direct IR alloc/empty/new for non-permutations (#72585)
This change implements the correct *level* sizes set up for the direct
IR codegen fields in the sparse storage scheme. This brings libgen and
codegen together again.
This is step 3 out of 3 to make sparse_tensor.new work for BSR
|
| mlir/test/Dialect/SparseTensor/codegen_buffer_initialization.mlir (diff) |
| mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp (diff) |
| mlir/test/Dialect/SparseTensor/codegen.mlir (diff) |
| mlir/include/mlir/ExecutionEngine/SparseTensor/File.h (diff) |
| mlir/test/Integration/Dialect/SparseTensor/CPU/block.mlir (diff) |
| mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sddmm-lib.mlir (diff) |
|
| flang/test/Semantics/OpenMP/requires05.f90 (diff) |
| flang/test/Semantics/OpenMP/declarative-directive.f90 (diff) |
| flang/lib/Parser/openmp-parsers.cpp (diff) |
| flang/test/Lower/OpenMP/FIR/declare-target-func-and-subr.f90 (diff) |
| flang/lib/Semantics/check-omp-structure.h (diff) |
| flang/test/Semantics/OpenMP/declare-target02.f90 (diff) |
| flang/lib/Semantics/resolve-directives.cpp (diff) |
| flang/test/Lower/OpenMP/declare-target-implicit-tarop-cap.f90 (diff) |
| llvm/include/llvm/Frontend/OpenMP/OMP.td (diff) |
| flang/test/Lower/OpenMP/declare-target-data.f90 (diff) |
| flang/test/Lower/OpenMP/FIR/declare-target-data.f90 (diff) |
| flang/lib/Semantics/check-omp-structure.cpp (diff) |
| flang/test/Lower/OpenMP/function-filtering.f90 (diff) |
| flang/test/Semantics/OpenMP/requires04.f90 (diff) |
 | flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 |
| flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90 |
| flang/test/Semantics/OpenMP/declare-target06.f90 (diff) |
| flang/test/Parser/OpenMP/declare_target-device_type.f90 (diff) |
| flang/test/Semantics/OpenMP/declare-target01.f90 (diff) |
| flang/test/Lower/OpenMP/declare-target-func-and-subr.f90 (diff) |
| flang/test/Lower/OpenMP/function-filtering-2.f90 (diff) |
| flang/lib/Lower/OpenMP.cpp (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
Commit
09ac2ec3ad368f82e6b0814a6427b2cb93591ef6
by githubRemove deprecated warning from cmake files (#72595)
`LIBCXXABI_SYSROOT`, `LIBCXXABI_TARGET_TRIPLE` and
`LIBCXXABI_GCC_TOOLCHAIN` are not supported anymore. Based on the
comment, the warning should be removed after branching for LLVM 15.
|
| libunwind/CMakeLists.txt (diff) |
| libcxxabi/CMakeLists.txt (diff) |
|
| libcxx/include/deque (diff) |
|
| libcxx/test/std/experimental/simd/test_utils.h (diff) |
|
| lld/ELF/InputFiles.h (diff) |
| lld/ELF/InputSection.cpp (diff) |
| lld/ELF/InputSection.h (diff) |
| lld/ELF/InputFiles.cpp (diff) |
|
| llvm/lib/CodeGen/CalcSpillWeights.cpp (diff) |
| llvm/lib/CodeGen/InlineSpiller.cpp (diff) |
| llvm/lib/CodeGen/SpillPlacement.h (diff) |
| llvm/lib/CodeGen/SpillPlacement.cpp (diff) |
Commit
865c1fda6f3e258b47a4f7992bb19ca2e9edcfa1
by github[InstCombine] Preserve NSW flags for neg instructions (#72548)
Alive2: https://alive2.llvm.org/ce/z/F9HG3M
This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.
|
| llvm/test/Transforms/InstCombine/sdiv-exact-by-negative-power-of-two.ll (diff) |
| llvm/test/Transforms/InstCombine/div.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (diff) |
|
| clang/lib/AST/Interp/IntegralAP.h (diff) |
Commit
3defe8facc55431c040f964802588473e2d4452b
by github[clang][Interp] Implement __builtin_bitreverse (#71687)
Since the return value of this function is slightly more involved than
the void/bool/int/size_t return values we've seen so far, also refactor
this.
|
| clang/test/AST/Interp/builtin-functions.cpp (diff) |
| clang/lib/AST/Interp/InterpBuiltin.cpp (diff) |
|
| clang/lib/AST/ExprConstant.cpp (diff) |
| clang/test/SemaCXX/builtin-classify-type.cpp (diff) |
| clang/test/Sema/builtin-classify-type.c (diff) |
| clang/docs/ReleaseNotes.rst (diff) |
|
| bolt/lib/Core/BinaryFunction.cpp (diff) |
|
| llvm/docs/CommandGuide/llvm-exegesis.rst (diff) |
|
| lld/test/ELF/lto/arm.ll |
Commit
de176d8c5496d6cf20e82aface98e102c593dbe2
by github[SCEV][LV] Invalidate LCSSA exit phis more thoroughly (#69909)
This an alternative to #69886. The basic problem is that SCEV can look
through trivial LCSSA phis. When the phi node later becomes non-trivial,
we do invalidate it, but this doesn't catch uses that are not covered by
the IR use-def walk, such as those in BECounts.
Fix this by adding a special invalidation method for LCSSA phis, which
will also invalidate all the SCEVUnknowns/SCEVAddRecExprs used by the
LCSSA phi node and defined in the loop.
We should probably also use this invalidation method in other places
that add predecessors to exit blocks, such as loop unrolling and loop
peeling.
Fixes #69097.
Fixes #66616.
Fixes #63970.
|
| llvm/lib/Analysis/ScalarEvolution.cpp (diff) |
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
| llvm/include/llvm/Analysis/ScalarEvolution.h (diff) |
| llvm/test/Transforms/LoopVectorize/pr66616.ll |
Commit
fd2d5add437b2b324492b1bc29374699fe7b614b
by github[include-cleaner] Make sure exports of stdlib also works for physical files (#72246)
This was creating discrepancy in cases where we might have a physical
file entry (e.g. because we followed a source location from a stdlib
file) and tried to find its exporters.
|
| clang-tools-extra/include-cleaner/lib/Record.cpp (diff) |
| clang-tools-extra/include-cleaner/unittests/RecordTest.cpp (diff) |
Commit
76a441a6efa5b7e73d96a3d67512493f3873b1cb
by i[MC] Fix compression header size check in ELF writer
This is #66888 with a test. For MC we only use a zstd test, as zlib has
a lot of versions/forks with different speed/size tradeoff, which would
make the test more brittle. If clang/test/Misc/cc1as-compress.s turns
out to be brittle, we could make the string longer.
|
| llvm/lib/MC/ELFObjectWriter.cpp (diff) |
| clang/test/Misc/cc1as-compress.s (diff) |
| llvm/test/MC/ELF/compress-debug-sections-zstd.s (diff) |
Commit
c4fd1fd6d4e0d21b2315fadecbcdc0892f3c6925
by github[mlir][emitc] Rename `call` op to `call_opaque` (#72494)
This renames the `emitc.call` op to `emitc.call_opaque` as the existing
call op does not refer to the callee by symbol. The rename allows to
introduce a new call op alongside with a future `emitc.func` op to model
and facilitate functions and function calls.
|
| mlir/test/Dialect/EmitC/attrs.mlir (diff) |
| mlir/test/Dialect/EmitC/types.mlir (diff) |
| mlir/include/mlir/Dialect/EmitC/IR/EmitC.td (diff) |
| mlir/test/Conversion/SCFToEmitC/if.mlir (diff) |
| mlir/docs/Dialects/emitc.md (diff) |
| mlir/test/Dialect/EmitC/invalid_ops.mlir (diff) |
| mlir/test/Target/Cpp/common-cpp.mlir (diff) |
| mlir/test/Dialect/EmitC/ops.mlir (diff) |
| mlir/test/Target/Cpp/control_flow.mlir (diff) |
| mlir/test/Target/Cpp/if.mlir (diff) |
| mlir/test/Target/Cpp/for.mlir (diff) |
| mlir/test/Target/Cpp/literal_call_operand.mlir (diff) |
| mlir/lib/Dialect/EmitC/IR/EmitC.cpp (diff) |
| mlir/test/Target/Cpp/call.mlir (diff) |
| mlir/lib/Target/Cpp/TranslateToCpp.cpp (diff) |
| mlir/test/Target/Cpp/attrs.mlir (diff) |
| mlir/test/Target/Cpp/types.mlir (diff) |
Commit
8775232c49cde288c429e27dd0f4f492fbb0cefa
by npopov[ValueTracking] Remove handling of KnownBits assumptions with invert
For all practical purposes, we only care about comparisons with
constant RHS in this code. In that case, an invert will be
canonicalized into the constant and it will be handled by other cases.
Given the complete lack of test coverage, I'm removing this code.
|
| llvm/lib/Analysis/ValueTracking.cpp (diff) |
| llvm/lib/Analysis/AssumptionCache.cpp (diff) |
|
| mlir/lib/Analysis/Presburger/IntegerRelation.cpp (diff) |
|
| llvm/lib/Transforms/InstCombine/InstructionCombining.cpp (diff) |
Commit
58253dcbcdfafb1fb1fb5ffc43d6f11a31f35e2a
by llvm-dev[X86] getTargetConstantBitsFromNode - bail if we're loading from a constant vector element type larger than the target value size
This can be improved upon by just truncating the constant value, but the crash needs to be addressed first.
Fixes #72539
|
| llvm/test/CodeGen/X86/pr72539.ll |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
Commit
915f6c3d6a4377e2672a95c656374d71df62e95a
by github[flang][RFC] Adding a design document for assumed-rank objects (#71959)
This patch adds a document describing assumed-rank objects and the
related features as well as how they will be implemented in Flang.
|
| flang/docs/index.md (diff) |
| flang/docs/AssumedRank.md |
|
| llvm/test/CodeGen/X86/vec_fabs.ll (diff) |
|
| llvm/test/CodeGen/X86/vec_fabs.ll (diff) |
|
| clang-tools-extra/include-cleaner/unittests/RecordTest.cpp (diff) |
Commit
a67b85ef63c7ec29c2076294e3f7c7f923144a53
by githubAdd llvm-dlltool to the toolchain list (#72563)
This adds dlltool to the list of tools which don't get excluded from
installation when LLVM_INSTALL_TOOLCHAIN_ONLY is set.
The most important effect here is that this tool will now be included in
the official Windows release.
While llvm-lib reuses the dlltool machinary internally and has many of
the same capabilities, it does not expose the functionality controller
by the '-k' flag, which is currently the only way to create import
libraries for i386 with stdcall symbols from a module definition alone.
We avoid changing llvm-lib tool, since it is designed to emulate LIB.EXE
from MSVC toolchain, and as this functionality is not supported there,
we would have had to introduce an LLVM extension flag in order to
support it.
See https://reviews.llvm.org/D36548 for reference on rationale for
dlltool '-k' flag.
|
| llvm/cmake/modules/AddLLVM.cmake (diff) |
|
| lld/COFF/Writer.cpp (diff) |
Commit
f049395fc8d6d8bbbc711c7a2ce293210c580240
by github[APINotes] Upstream APINotesManager
This upstreams more of the Clang API Notes functionality that is
currently implemented in the Apple fork:
https://github.com/apple/llvm-project/tree/next/clang/lib/APINotes
|
| clang/include/clang/Basic/DiagnosticCommonKinds.td (diff) |
| clang/include/clang/Basic/LangOptions.def (diff) |
| clang/include/clang/Basic/Module.h (diff) |
| clang/include/clang/Basic/SourceMgrAdapter.h |
| clang/lib/Basic/CMakeLists.txt (diff) |
| clang/lib/APINotes/CMakeLists.txt (diff) |
| clang/lib/Basic/SourceMgrAdapter.cpp |
| clang/include/clang/APINotes/Types.h (diff) |
| clang/lib/APINotes/APINotesManager.cpp |
| clang/include/clang/APINotes/APINotesManager.h |
Commit
26ce3e4239150ccc3328c43e4b47264989c07411
by github[InstCombine] Preserve NSW flags for `lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2)` (#72625)
Alive2: https://alive2.llvm.org/ce/z/TU_V9M
This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.
|
| llvm/test/Transforms/InstCombine/shift-logic.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp (diff) |
Commit
9ed4a57e31ddabd9628b31fe1c0abe75d3789ecf
by githubAdd libc++ github actions workflow to replace buildkite (#71836)
This change ports almost all of the linux buildkite builders to github
actions.
I would like to have this transition occur as soon as possible.
|
| libcxx/utils/ci/buildkite-pipeline.yml (diff) |
| .github/workflows/libcxx-build-and-test.yaml |
Commit
e5e71affb72178ccfedae2083c686999d9fa4941
by github[LV] Reverse mask up front, not when creating vector pointer. (#72163)
Reverse mask early on when populating BlockInMask. This will enable
separating mask management and address computation from the memory
recipes in the future and is also needed to enable explicit unrolling in
VPlan.
|
| llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll (diff) |
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
| llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll (diff) |
| llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll (diff) |
Commit
e77af7e1b07ac648c026922e4a0b07e9af35f714
by github[DebugInfo] Make DIArgList inherit from Metadata and always unique (#72147)
This patch changes the `DIArgList` class's inheritance from `MDNode` to
`Metadata, ReplaceableMetadataImpl`, and ensures that it is always
unique, i.e. a distinct DIArgList should never be produced.
This should not result in any changes to IR or bitcode parsing and
printing, as the format for DIArgList is unchanged, and the order in which it
appears should also be identical. As a minor note, this patch also fixes
a gap in the verifier, where the ValueAsMetadata operands to a DIArgList
would not be visited.
|
| llvm/include/llvm/IR/Metadata.h (diff) |
| llvm/lib/AsmParser/LLParser.cpp (diff) |
| llvm/lib/IR/LLVMContextImpl.cpp (diff) |
| llvm/include/llvm/AsmParser/LLParser.h (diff) |
| llvm/lib/IR/DebugInfoMetadata.cpp (diff) |
| llvm/lib/IR/LLVMContextImpl.h (diff) |
| llvm/lib/IR/TypeFinder.cpp (diff) |
| llvm/include/llvm/IR/Metadata.def (diff) |
| llvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff) |
| llvm/lib/IR/AsmWriter.cpp (diff) |
| llvm/include/llvm/IR/DebugInfoMetadata.h (diff) |
| llvm/lib/IR/Metadata.cpp (diff) |
| llvm/lib/IR/Verifier.cpp (diff) |
|
| mlir/lib/Dialect/Vector/IR/VectorOps.cpp (diff) |
| mlir/test/Dialect/Vector/vector-transpose-lowering.mlir (diff) |
| mlir/test/Dialect/Vector/canonicalize.mlir (diff) |
| mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp (diff) |
|
| llvm/lib/Analysis/ConstantFolding.cpp (diff) |
| llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll (diff) |
Commit
9c0e64999b23046d0b8987a48ddc41a4c6129f9d
by github[Offloading][NFC] Refactor handling of offloading entries (#72544)
Summary:
This patch is a simple refactoring of code out of the linker wrapper
into a common location. The main motivation behind this change is to
make it easier to change the handling in the future to accept a triple
to be used to emit entries that function on that target.
|
| llvm/include/llvm/Frontend/Offloading/Utility.h (diff) |
| clang/test/Driver/linker-wrapper-image.c (diff) |
| clang/tools/clang-linker-wrapper/CMakeLists.txt (diff) |
| llvm/lib/Frontend/Offloading/Utility.cpp (diff) |
| clang/tools/clang-linker-wrapper/OffloadWrapper.cpp (diff) |
Commit
ff219ea9ca80f46ff85dbdb94622ffb319a0d237
by github[OpenACC] Initial commits to support OpenACC (#70234)
Initial commits to support OpenACC. This patchset:
adds a clang-command line argument '-fopenacc', and starts
to define _OPENACC, albeit to '1' instead of the standardized
value (since we don't properly implement OpenACC yet).
The OpenACC spec defines `_OPENACC` to be equal to the latest standard
implemented. However, since we're not done implementing any standard,
we've defined this by default to be `1`. As it is useful to run our
compiler against existing OpenACC workloads, we're providing a
temporary override flag to change the `_OPENACC` value to be any
entirely digit value, permitting testing against any existing OpenACC
project.
Exactly like the OpenMP parser, the OpenACC pragma parser needs to
consume and reprocess the tokens. This patch sets up the infrastructure
to do so by refactoring the OpenMP version of this into a more general
version that works for OpenACC as well.
Additionally, this adds a few diagnostics and token kinds to get us
started.
|
| clang/include/clang/Basic/DiagnosticGroups.td (diff) |
| clang/test/ParserOpenACC/unimplemented.c |
| clang/test/ParserOpenACC/unimplemented.cpp |
| clang/include/clang/Driver/Options.td (diff) |
| clang/lib/Serialization/ASTReader.cpp (diff) |
| clang/lib/Frontend/CompilerInvocation.cpp (diff) |
| clang/lib/Serialization/ASTWriter.cpp (diff) |
| clang/test/ParserOpenACC/disabled.c |
| clang/test/Driver/openacc.c |
| clang/lib/Driver/ToolChains/Clang.cpp (diff) |
| clang/lib/Parse/ParsePragma.cpp (diff) |
| clang/lib/Parse/CMakeLists.txt (diff) |
| clang/lib/Parse/Parser.cpp (diff) |
| clang/test/Preprocessor/openacc.c |
| clang/include/clang/Basic/TokenKinds.def (diff) |
| clang/lib/Frontend/InitPreprocessor.cpp (diff) |
| clang/lib/Parse/ParseStmt.cpp (diff) |
| clang/include/clang/Parse/Parser.h (diff) |
| clang/lib/Parse/ParseDecl.cpp (diff) |
| clang/lib/Parse/ParseDeclCXX.cpp (diff) |
| clang/include/clang/Basic/LangOptions.def (diff) |
| clang/docs/ReleaseNotes.rst (diff) |
| clang/lib/Parse/ParseOpenACC.cpp |
| clang/include/clang/Basic/DiagnosticParseKinds.td (diff) |
| clang/include/clang/Basic/LangOptions.h (diff) |
Commit
2ed15877e7427801d1699611d0b29f23718b01ab
by llvm-dev[X86] Ensure asm comments only print the constant values for the vector load's register width
We were printing the entire Constant, which if we were loading from a wider constant pool entry meant that we were confusing the asm comment with upper bits that aren't actually part of the load result
|
| llvm/lib/Target/X86/X86MCInstLower.cpp (diff) |
| llvm/test/CodeGen/X86/insert-into-constant-vector.ll (diff) |
Commit
44af5924b1cbbb395e7e71250a5445053c4ec4a3
by github[Statepoint] Return undef value for the statepoint of the none token (#72552)
Helps avoid the crash in verifier when it tries to print the error.
`none` token might be produced by llvm-reduce, since it's a default
value, so by extension this also fixes llvm-reduce crash, allowing it to
just discard invalid IR.
---------
Co-authored-by: arpilipe <apilipenko@azul.com>
|
| llvm/test/Verifier/gc_none_token.ll |
| llvm/lib/IR/IntrinsicInst.cpp (diff) |
|
| llvm/lib/TextAPI/TextStubV5.cpp (diff) |
Commit
8f81c605f5f450c4b4b641f805935a85b9409d98
by github[RISCV] Remove custom instruction selection for VFCVT_RM and friends (#72540)
We already have the pseudo's for lowering these as MI nodes with
rounding mode operands, and the generic FRM insertion pass. Doing the
insertion later in the backend allows SSA level passes to avoid
reasoning about physical register copies, and happens to produce better
code in practice. The later is mostly an accident of our insertion
order; we happen to place the frm write after the vsetvli, and it's very
common for a register to be killed at the vsetvli. End result is that we
get slightly better scalar register allocation.
I'm a bit unclear on the history here. I was surprised to find this code
in ISEL lowering at all, but am also surprised once I found it that all
the patterns and pseudos seem to already exist. My best guess is that
maybe we didn't do all the possible cleanup after introducing the
HasRoundMode mechanism?
|
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll (diff) |
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
| llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/round-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/floor-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll (diff) |
| llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (diff) |
|
| clang/lib/AST/Interp/Function.h (diff) |
| clang/lib/AST/ExprConstant.cpp (diff) |
| clang/lib/AST/Interp/ByteCodeEmitter.cpp (diff) |
| clang/test/SemaCXX/builtin-classify-type.cpp (diff) |
| clang/test/Sema/builtin-classify-type.c (diff) |
| clang/lib/AST/Interp/ByteCodeExprGen.cpp (diff) |
| clang/lib/AST/Interp/Function.cpp (diff) |
| clang/lib/AST/Interp/InterpBuiltin.cpp (diff) |
| clang/lib/AST/ExprConstShared.h |
| clang/lib/AST/Interp/Interp.cpp (diff) |
Commit
06effaf43e9669c55ee4a1e2254166b5e7dc5b29
by github[lldb][test] Add the ability to extract the variable value out of the summary. (#72631)
Fix for https://github.com/llvm/llvm-project/issues/71897
When it comes to test infrastructure the test (TestDAP_variables.py:
test_scopes_variables_setVariable_evaluate_with_descriptive_summaries)
will fail if the variable has a summary along with value.
I just tried to add a summary to a variable before we set a value to the
variable using below expression from “request_setVariable” function.
RunLLDBCommands(llvm::StringRef(), {std::string("type summary add
--summary-string "{sample summary}" (const char **) argv")});
As value has nonnumeric characters where we are trying to convert into
integer, python is throwing an error. We did not see this issue in
upstream as we are not adding summary explicitly, by default we are
getting empty summary & value for all children’s of argv parameter (even
after auto summary).
The test is failing with below error:
ERROR:
test_scopes_variables_setVariable_evaluate_with_descriptive_summaries
(TestDAP_variables.TestDAP_variables)
Traceback (most recent call last):
File
"/llvm/llvm-project/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py",
line 372, in
test_scopes_variables_setVariable_evaluate_with_descriptive_summaries
enableAutoVariableSummaries=True
File
"/llvm/llvm-project/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py",
line 266, in do_test_scopes_variables_setVariable_evaluate
argv = self.get_local_as_int("argv")
File
"//llvm/llvm-project/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py",
line 199, in get_local_as_int
return int(value, 16)
ValueError: invalid literal for int() with base 16: '0x0000000000001234
sample summary'
Config=x86_64-//llvm/llvm-build/bin/clang
Co-authored-by: Santhosh Kumar Ellendula <sellendu@hu-sellendu-hyd.qualcomm.com>
|
| lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py (diff) |
Commit
0765f6451ff964c4e209133e4ddef00a52dc9e7f
by github[RISCV] Use correct register class for Z[df]inx inline asm (#71872)
Allocate a register of the correct register class for inline asm
constraint "r" when used for FP values with -Zfinx/-Zdinx.
---------
Co-authored-by: Nemanja Ivanovic <nemanja@synopsys.com>
|
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
| llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll |
Commit
227607190e68c303920bcbd148043dbb1aa5d3b1
by github[RISCV] Fix crash in PEI with empty entry block with Zcmp (#72117)
We check the opcode of the first instruction in the block where the
prologue is inserted without checking if the iterator points to any
instructions. When the basic block is empty, that causes a crash. One
way the prologue block can be empty is when it starts with a call to
__builtin_readcyclecounter on RV32 since that produces a loop.
Co-authored-by: Nemanja Ivanovic <nemanja@synopsys.com>
|
| llvm/test/CodeGen/RISCV/pei-crash.ll |
| llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (diff) |
Commit
7d1a9e81b0b59d020a52c789d659acb5ee5fdc41
by erichkeane[OpenACC] Rename ParseOpenACCDirective to ParseOpenACCDirectiveDecl
The former name is more useful as a callee of the function in a future
patch, so as suggested in that review, move the rename here.
|
| clang/lib/Parse/ParseDeclCXX.cpp (diff) |
| clang/include/clang/Parse/Parser.h (diff) |
| clang/lib/Parse/Parser.cpp (diff) |
| clang/lib/Parse/ParseOpenACC.cpp (diff) |
| clang/lib/Parse/ParseDecl.cpp (diff) |
|
| llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp (diff) |
Commit
ec6a34e2a781fcfc6fe1d30e7cd358fb779157cf
by github[lldb] Pass important options to dsymForUUID (#72669)
On macOS, we usually use the DebugSymbols framework to find dSYMs, but
we have a few places (including crashlog.py) that calls out directly to
dsymForUUID. Currently, this invocation is missing two important
options:
* `--ignoreNegativeCache`: Poor network connectivity or lack of VPN can
lead to a negative cache hit. Avoiding those issues is worth the penalty
of skipping these caches.
* `--copyExecutable`: Ensure we copy the executable as it might not be
available at its original location.
rdar://118480731
|
| lldb/examples/python/crashlog.py (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
|
| llvm/lib/Analysis/InstructionSimplify.cpp (diff) |
Commit
c601be9c8400929f7b5c015a2bceae57e3aab550
by github[coroutines] Introduce [[clang::coro_return_type]] and [[clang::coro_wrapper]] (#71945)
First step in the implementation of
[RFC](https://discourse.llvm.org/t/rfc-lifetime-bound-check-for-parameters-of-coroutines/74253)
([final approved
doc](https://docs.google.com/document/d/1hkfXHuvIW1Yv5LI-EIkpWzdWgIoUlzO6Zv_KJpknQzM/edit)).
This introduces the concepts of a **coroutine return type** and explicit
**coroutine wrapper** functions.
---------
Co-authored-by: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
|
| clang/test/SemaCXX/coro-return-type-and-wrapper.cpp |
| clang/docs/ReleaseNotes.rst (diff) |
| clang/include/clang/Basic/Attr.td (diff) |
| clang/include/clang/Basic/AttrDocs.td (diff) |
| clang/include/clang/Basic/DiagnosticSemaKinds.td (diff) |
| clang/lib/Sema/SemaDecl.cpp (diff) |
| clang/include/clang/Sema/Sema.h (diff) |
| clang/test/Misc/pragma-attribute-supported-attributes-list.test (diff) |
|
| llvm/lib/Analysis/ConstantFolding.cpp (diff) |
Commit
aeedc0763772b398a725ab34d8a9cc1d698c60cb
by llvm-dev[IR] Add GraalVM calling conventions
Adds GraalVM calling conventions. The only difference with the default calling conventions is that GraalVM reserves two registers for the heap base and the thread. Since the registers are then accessed by name, getRegisterByName has to be updated accordingly.
This patch implements the calling conventions only for X86, AArch64 and RISC-V.
For X86, the reserved registers are X14 and X15. For AArch64, they are X27 and X28. For RISC-V, they are X23 and X27.
This patch has been used by the LLVM backend of GraalVM's Native Image project in production for around 4 months with no major issues.
Differential Revision: https://reviews.llvm.org/D151107
|
| llvm/lib/Target/X86/X86RegisterInfo.cpp (diff) |
| llvm/lib/AsmParser/LLLexer.cpp (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/graalcc.ll |
| llvm/include/llvm/IR/CallingConv.h (diff) |
| llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (diff) |
| llvm/include/llvm/AsmParser/LLToken.h (diff) |
| llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff) |
| llvm/lib/AsmParser/LLParser.cpp (diff) |
| llvm/test/CodeGen/RISCV/graalcc.ll |
| llvm/lib/IR/AsmWriter.cpp (diff) |
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
| llvm/test/CodeGen/AArch64/graalcc.ll |
| llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (diff) |
|
| llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll (diff) |
| llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll (diff) |
|
| llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn (diff) |
| llvm/utils/gn/secondary/clang/lib/APINotes/BUILD.gn (diff) |
|
| llvm/utils/gn/secondary/clang/lib/Parse/BUILD.gn (diff) |
Commit
764c3afd43128f7ccddb070953c330b340ebe811
by github[Tooling/Inclusion] Avoid narrowing conversions in macro expansion (#72664)
```
clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp:144:65: warning:
narrowing conversion of ‘llvm::StringRef(((const char*)"std::experiment
al::filesystem::")).llvm::StringRef::size()’ from ‘size_t’ {aka ‘long un
signed int’} to ‘unsigned int’ [-Wnarrowing]
144 | #define SYMBOL(Name, NS, Header) {#NS #Name, StringRef(#NS).size
(), #Header},
| ~~~~~~~~~~~~~~~~~~~
^~
clang/lib/Tooling/Inclusions/Stdlib/StdTsSymbolMap.inc:51:1: note: in ex
pansion of macro ‘SYMBOL’
51 | SYMBOL(temp_directory_path, std::experimental::filesystem::, <ex
perimental/filesystem>)
| ^~~~~~
```
|
| clang/lib/Tooling/Inclusions/Stdlib/StandardLibrary.cpp (diff) |
Commit
aafad2d214246bae4d53ce3178b11486ebc83890
by github[Clang] Warn on deprecated specializations used in system headers. (#70353)
When the top of the instantiation stack is in user code.
The goal of this PR is to allow deprecation of some char_traits
specializations in libc++ as done in https://reviews.llvm.org/D157058
which was later reverted by
https://github.com/llvm/llvm-project/pull/66153#issuecomment-1719578384
as Clang never emitted the libc++ warnings.
Because Clang likes to eagerly instantiate, we can look for the location
of the top of the instantiation stack, and emit a warning if that
location is in user code.
The warning emission is forced by temporarily instructing the diag
engine not to silence warning in system headers.
|
| clang/test/SemaCXX/warn-deprecated-specializations-in-system-headers.cpp |
| clang/lib/Sema/SemaTemplate.cpp (diff) |
| clang/include/clang/Sema/Sema.h (diff) |
| clang/lib/Sema/SemaAvailability.cpp (diff) |
| clang/docs/ReleaseNotes.rst (diff) |
Commit
6e31709283478aec409af924d9e9c13843f13c42
by github[ClangModule] Fix decl-params-determinisim test after serialization change (#72572)
Fix decl-params-determinisim test after 48be81e1 packed some information
in the clang module. The test is to make sure the decls are appearing in
a strict ordering and it relies on check the correct field in the
bitcode format.
Add more explanation in the comments to help future updates when
serialization format affects this test.
|
| clang/test/Modules/decl-params-determinisim.m (diff) |
|
| clang/lib/AST/ASTContext.cpp (diff) |
| llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp (diff) |
Commit
b1338d1e3a8c4b1b4c7364696852f67401fa40ca
by github[tsan] Shrink RiscV64 48-bit LowApp region slightly to speed up TSan RestoreAddr (#72316)
The RiscV64 48-bit mappings introduced in
46cb8d9a325233ac11ed5e90367c43774294d87e necessitated changing
RestoreAddr to use 4-bits as the indicator. This roughly halves the
speed of RestoreAddr, because it is now brute-force testing addresses in
1TB increments, rather than 2TB increments. Crucially, this slowdown
applies to TSan on all platforms, not just RiscV64 48-bit.
This patch slightly shrinks the RiscV64 48-bit LowApp region mapping
(from 5TB to 4TB); we hope that 4TB ought to be enough for anybody,
especially since there is no ASLR applied to the binary in this region.
This allows restoring RestoreAddr to use 3-bits as the indicator again,
thus speeding up TSan on all platforms.
Co-authored-by: Thurston Dang <thurston@google.com>
|
| compiler-rt/lib/tsan/rtl/tsan_platform.h (diff) |
|
| llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll (diff) |
|
| mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir (diff) |
Commit
0fd5dc94380d5fe666dc6c603b4bb782cef743e7
by githubRevert "[DebugInfo] Make DIArgList inherit from Metadata and always unique" (#72682)
Reverts llvm/llvm-project#72147
Reverted due to buildbot failure:
https://lab.llvm.org/buildbot/#/builders/5/builds/38410
|
| llvm/lib/IR/DebugInfoMetadata.cpp (diff) |
| llvm/include/llvm/IR/Metadata.def (diff) |
| llvm/lib/IR/TypeFinder.cpp (diff) |
| llvm/lib/IR/LLVMContextImpl.cpp (diff) |
| llvm/lib/AsmParser/LLParser.cpp (diff) |
| llvm/lib/IR/Verifier.cpp (diff) |
| llvm/lib/IR/LLVMContextImpl.h (diff) |
| llvm/include/llvm/IR/Metadata.h (diff) |
| llvm/lib/IR/AsmWriter.cpp (diff) |
| llvm/include/llvm/AsmParser/LLParser.h (diff) |
| llvm/include/llvm/IR/DebugInfoMetadata.h (diff) |
| llvm/lib/IR/Metadata.cpp (diff) |
| llvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff) |
Commit
a4051932895d9ef6c4516c42309a49912f69f740
by Jon Roelofs[MC][AsmParser] Diagnose improperly nested .cfi frames
This showed up when simplifying some large testcase, where the cfi directives
became out of sync with the proc's they enclose.
rdar://111459507
Differential revision: https://reviews.llvm.org/D155245
|
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
Commit
bfbfd1caa4da70774547c1c298e482661822a137
by llvm-dev[X86] combineLoad - try to reuse existing constant pool entries for smaller vector constant data
If we already have a YMM/ZMM constant that a smaller XMM/YMM has matching lower bits, then ensure we reuse the same constant pool entry.
Extends the similar combines we already have to reuse VBROADCAST_LOAD/SUBV_BROADCAST_LOAD constant loads.
This is a mainly a canonicalization, but should make it easier for us to merge constant loads in a future commit (related to both #70947 and better X86FixupVectorConstantsPass usage for #71078).
|
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll (diff) |
Commit
4263b2ecf8c4b9b62094a731bb92c501197531b0
by github[NVPTX] Expand EXTLOAD for v8f16 and v8bf16 (#72672)
In openai/triton#2483 I've encountered a bug in the NVPTX codegen. Given
`load<8 x half>` followed by `fpext to <8 x float>` we get
```
ld.shared.v4.b16 {%f1, %f2, %f3, %f4}, [%r15+8];
ld.shared.v4.b16 {%f5, %f6, %f7, %f8}, [%r15];
```
Which loads float16 values into float registers without any conversion
and the result is simply garbage.
This PR brings `v8f16` and `v8bf16` into line with the other vector
types by expanding it to load + cvt.
cc @manman-ren @Artem-B @jlebar
|
| llvm/test/CodeGen/NVPTX/vector-loads.ll (diff) |
| llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp (diff) |
| llvm/test/CodeGen/NVPTX/bf16-instructions.ll (diff) |
Commit
e2fb816c4f0286ddf8b1030148a343d5efc14e01
by githubAdd new API in SBTarget for loading core from SBFile (#71769)
Add a new API in SBTarget to Load Core from a SBFile.
This will enable a target to load core from a file descriptor.
So that in coredumper, we don't need to write core file to disk, instead
we can pass the input file descriptor to lldb directly.
Test:
```
(lldb) script
Python Interactive Interpreter. To exit, type 'quit()', 'exit()' or Ctrl-D.
>>> file_object = open("/home/hyubo/210hda79ms32sr0h", "r")
>>> fd=file_object.fileno()
>>> file = lldb.SBFile(fd,'r', True)
>>> error = lldb.SBError()
>>> target = lldb.debugger.CreateTarget(None)
>>> target.LoadCore(file,error)
SBProcess: pid = 56415, state = stopped, threads = 1
```
|
| lldb/include/lldb/API/SBTarget.h (diff) |
| lldb/source/API/SBTarget.cpp (diff) |
| lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py (diff) |
Commit
f99a02005970cdcb0aad0de80fa4e5b546c6546b
by stephen.tozerReapply "[DebugInfo] Make DIArgList inherit from Metadata and always unique"
This reverts commit 0fd5dc94380d5fe666dc6c603b4bb782cef743e7.
The original commit removed DIArgLists from being in an MDNode map, but did
not insert a new `delete` in the LLVMContextImpl destructor. This
reapply adds that call to delete, preventing a memory leak.
|
| llvm/include/llvm/IR/DebugInfoMetadata.h (diff) |
| llvm/lib/IR/LLVMContextImpl.h (diff) |
| llvm/lib/IR/Metadata.cpp (diff) |
| llvm/lib/IR/AsmWriter.cpp (diff) |
| llvm/include/llvm/IR/Metadata.def (diff) |
| llvm/include/llvm/AsmParser/LLParser.h (diff) |
| llvm/lib/AsmParser/LLParser.cpp (diff) |
| llvm/lib/IR/Verifier.cpp (diff) |
| llvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff) |
| llvm/lib/IR/LLVMContextImpl.cpp (diff) |
| llvm/lib/IR/TypeFinder.cpp (diff) |
| llvm/include/llvm/IR/Metadata.h (diff) |
| llvm/lib/IR/DebugInfoMetadata.cpp (diff) |
Commit
99ee2db198d86f685bcb07a1495a7115ffc31d7e
by github[TargetInstrInfo] enable foldMemoryOperand for InlineAsm (#70743)
foldMemoryOperand looks at pairs of instructions (generally a load to
virt reg then use of the virtreg, or def of a virtreg then a store) and
attempts to combine them. This can reduce register pressure.
A prior commit added the ability to mark such a MachineOperand as
foldable. In terms of INLINEASM, this means that "rm" was used (rather
than just "r") to denote that the INLINEASM may use a memory operand
rather than a register operand. This effectively undoes decisions made
by the instruction selection framework. Callers will be added in the
register allocation frameworks. This has been tested with all of the
above (which will come as follow up patches).
Thanks to @topperc who suggested this at last years LLVM US Dev Meeting
and @qcolombet who confirmed this was the right approach.
Link: https://github.com/llvm/llvm-project/issues/20571
|
| llvm/include/llvm/CodeGen/TargetInstrInfo.h (diff) |
| llvm/lib/CodeGen/TargetInstrInfo.cpp (diff) |
|
| openmp/runtime/src/z_Linux_util.cpp (diff) |
|
| mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
|
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
Commit
94ce378ec051a120d640073b885fcd90f1cf10f8
by github[lldb] Remove unused Status::SetMachError (NFC) (#72668)
This function is never used, neither here nor downstream in the Swift
fork. As far as I can tell, the same is true for the corresponding
eErrorTypeMachKernel but as that's part of the SB API we cannot remove
that.
|
| lldb/source/Utility/Status.cpp (diff) |
| lldb/include/lldb/Utility/Status.h (diff) |
Commit
18eefc186d75f60c9a828e13a8379769eb5c1812
by githubModify llvm-gsymutil lookups to handle overlapping ranges correctly. (#72350)
llvm-gsymutil allows address ranges to overlap. There was a bug where if
we had debug info for a function with a range like [0x100-0x200) and a
symbol at the same start address yet with a larger range like
[0x100-0x300), we would randomly get either only information from the
first or second entry. This could cause lookups to fail due to the way
the binary search worked.
This patch makes sure that when lookups happen we find the first address
table entry that can match an address, and also ensures that we always
select the first FunctionInfo that could match. FunctionInfo entries are
sorted such that the most debug info rich entries come first. And if we
have two ranges that have the same start address, the smaller range
comes first and the larger one comes next. This patch also adds the
ability to iterate over all function infos with the same start address
to always find a range that contains the address.
Added a unit test to test this functionality that failed prior to this
fix and now succeeds.
Also fix an issue when dumping an entire GSYM file that has duplicate address entries where it used to always print out the binary search match for the FunctionInfo, not the actual data for the address index.
|
| llvm/lib/DebugInfo/GSYM/GsymReader.cpp (diff) |
| llvm/include/llvm/DebugInfo/GSYM/GsymReader.h (diff) |
| llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp (diff) |
|
| llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp (diff) |
Commit
2fd343e56c9fe3cdb1f9afe0fc9e1ec6d52d2f44
by Jon Roelofs[MC][AsmParser] Diagnose improperly nested .cfi frames
This showed up when simplifying some large testcase, where the cfi directives
became out of sync with the proc's they enclose.
rdar://111459507
Differential revision: https://reviews.llvm.org/D155245
This reverts commit 4172fcc1ebbe0a7b699bfcbdaae9d5f688b62b09.
|
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| lld/test/COFF/gc-dwarf-eh.s (diff) |
|
| mlir/lib/Dialect/SparseTensor/IR/Detail/Var.cpp (diff) |
| mlir/lib/Dialect/SparseTensor/IR/Detail/Var.h (diff) |
| mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp (diff) |
| mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.h (diff) |
Commit
64b6ef02e263a8ee48bd91f8b06dd3945eb9be44
by github[OpenACC] Implement initial parsing for `parallel` construct (#72661)
As the first real parsing effort for the OpenACC implementation effort,
this implements the parsing for first construct/directive name. This
does not do any semantic analysis, nor any of the clauses. Those will
come in a future patch.
For the time being, we warn when we hit a point that we don't implement
the parsing for either of these situations.
|
| clang/include/clang/Basic/DiagnosticParseKinds.td (diff) |
| clang/lib/Parse/ParseOpenACC.cpp (diff) |
| clang/include/clang/Parse/RAIIObjectsForParser.h (diff) |
| clang/lib/Parse/Parser.cpp (diff) |
| clang/include/clang/Parse/Parser.h (diff) |
| clang/test/ParserOpenACC/unimplemented.c (diff) |
| clang/test/ParserOpenACC/parse-constructs.c |
| clang/test/ParserOpenACC/unimplemented.cpp (diff) |
| clang/include/clang/Basic/OpenACCKinds.h |
|
| flang/lib/Optimizer/Transforms/LoopVersioning.cpp (diff) |
Commit
9052ac954dde20f94e6c649053411bbff14fc45c
by github[NFCI][msan] Reduce code duplication by extracting VarArgHelperBase
Reviewers: thurstond, kstoimenov
Reviewed By: thurstond, kstoimenov
Pull Request: https://github.com/llvm/llvm-project/pull/72686
|
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
Commit
9bd5f808ccacef0acc84529a0bdd22b448d06e4a
by erichkeane[OpenACC] Implement 'trivial' construct/directive parsing.
Now that the `parallel` support has landed, add the other 'trivial' to
implement ones that don't require any additional work other than adding
them to the StringSwitch.
|
| clang/include/clang/Basic/OpenACCKinds.h (diff) |
| clang/lib/Parse/ParseOpenACC.cpp (diff) |
| clang/test/ParserOpenACC/parse-constructs.c (diff) |
|
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
Commit
a1ae7e97de24b7d9f3cd331ff47fc5a0cb5c29fe
by github[libc++] Fix char_traits deprecation message (LLVM 18 -> 19) (#72690)
We intend to remove the base specialization in LLVM 19, not LLVM 18. We
simply forgot to update the deprecation message accordingly.
|
| libcxx/include/__string/char_traits.h (diff) |
Commit
4db99c8b541592729cc0f8b2d1918bcb8c45f99f
by github[libc] Add base for target config within cmake (#72318)
Currently the only way to add or remove entrypoints is to modify the
entrypoints.txt file for the current target. This isn't ideal since
a user would have to carry a diff for this file when updating their
checkout. This patch adds a basic mechanism to allow the user to remove
entrypoints without modifying the repository.
|
| libc/cmake/modules/system_features/check_sys_random.cpp |
| libc/config/CMakeLists.txt (diff) |
| libc/config/linux/x86_64/exclude.txt |
| libc/CMakeLists.txt (diff) |
Commit
be32e39892372d9fe069af6bfb829aa0071176a6
by github[ValueTracking] Ignore poison values in `computeKnownBits` (#72683)
This patch handles `poison` elements of non-splat vectors in
`computeKnownBits`. It addresses test changes after I delete the
duplicate logic in https://github.com/llvm/llvm-project/pull/72535.
See also @nikic's comment:
https://github.com/llvm/llvm-project/pull/72535#pullrequestreview-1736991557
|
| llvm/test/Transforms/InstCombine/add.ll (diff) |
| llvm/test/Transforms/InstCombine/extractelement.ll (diff) |
| llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll (diff) |
| llvm/test/Transforms/InstCombine/mul.ll (diff) |
| llvm/lib/Analysis/ValueTracking.cpp (diff) |
| llvm/test/Transforms/InstCombine/lshr.ll (diff) |
Commit
fab690d6b5d50f263bdb2413c913c9bd34d47625
by github[NFC][SHT_LLVM_BB_ADDR_MAP] Define and use constructor and accessors for BBAddrMap fields. (#72689)
The fields are still kept as public for now since our tooling accesses
them. Will change them to private visibility in a later patch.
|
| llvm/lib/Object/ELF.cpp (diff) |
| llvm/include/llvm/Object/ELFTypes.h (diff) |
| llvm/tools/llvm-objdump/llvm-objdump.cpp (diff) |
| llvm/unittests/Object/ELFObjectFileTest.cpp (diff) |
Commit
144b2f579ef06e663cf233431d291a913b895074
by github[RISCV] Start vslide1down sequence with a dependency breaking splat (#72691)
If we are using entirely vslide1downs to initialize an otherwise undef
vector, we end up with an implicit_def as the source of the first
vslide1down. This register has to be allocated, and creates false
dependencies with surrounding code.
Instead, start our sequence with a vmv.v.x in the hopes of creating a
dependency breaking idiom. Unfortunately, it's not clear this will
actually work as due to the VL=0 special case for T.A. the hardware has
to work pretty hard to recognize that the vmv.v.x actually has no source
dependence. I don't think we can reasonable expect all hardware to have
optimized this case, but I also don't see any downside in prefering it.
|
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll (diff) |
| llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll (diff) |
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll (diff) |
| llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll (diff) |
| llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll (diff) |
Commit
ae182dbb1d199f92b9c146e3db8a738a30b587b9
by github[readtapi] Add Merge functionality (#72656)
Merge allows a user to merge different files (tbds for now or dylibs in
the future) to emit out a single tbd with all input contents. This does
require that all inputs represent the same library.
|
| llvm/include/llvm/TextAPI/TextAPIWriter.h (diff) |
| llvm/test/tools/llvm-readtapi/command-line.test (diff) |
| llvm/tools/llvm-readtapi/DiffEngine.cpp (diff) |
| llvm/test/tools/llvm-readtapi/merge.test |
| llvm/test/tools/llvm-readtapi/write.test |
| llvm/test/tools/llvm-readtapi/merge-invalid.test |
| llvm/tools/llvm-readtapi/DiffEngine.h (diff) |
| llvm/tools/llvm-readtapi/TapiOpts.td (diff) |
| llvm/tools/llvm-readtapi/llvm-readtapi.cpp (diff) |
| llvm/test/tools/llvm-readtapi/compare-incorrect-format.test (diff) |
|
| llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll |
| llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll |
| compiler-rt/test/msan/vararg_shadow.cpp |
|
| utils/bazel/llvm-project-overlay/clang/BUILD.bazel (diff) |
|
| lld/ELF/InputFiles.cpp (diff) |
| lld/test/ELF/lto/sparcv9.ll |
Commit
6a126e279dedc9fb8c204d29cfc227b0652ffe6c
by aeubanksRevert "[SLP][NFC]Make collectValuesToDemote member of BoUpSLP to avoid using"
This reverts commit cfd0f41f4effb5d31654dcb28c1a577c152ee23b.
Causes crashes, see https://github.com/llvm/llvm-project/commit/cfd0f41f4effb5d31654dcb28c1a577c152ee23b.
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
Commit
bd934fcbfda71fe5f332544a1c90fd8f59913d79
by aeubanksRevert "[MC][AsmParser] Diagnose improperly nested .cfi frames"
This reverts commit 2fd343e56c9fe3cdb1f9afe0fc9e1ec6d52d2f44.
Breaks building aarch64 builtins, see https://reviews.llvm.org/D155245.
|
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| lld/test/COFF/gc-dwarf-eh.s (diff) |
Commit
12bdbe2792b53ee1253c508b44f24d43735e7de9
by github[clang-tidy][NFC][DOC] Add missing HICPP rule id's (#72553)
Add HICPP rule identities to the documentation for
`hicpp-avoid-c-arrays` and `hicpp-no-assembler`.
Includes an update of `hicpp-avoid-goto` to look like other aliased
checks.
References:
* avoid-c-arrays
Commit: 2634bd599567842385e11d1fd70f5486c166f935
|
| clang-tools-extra/docs/clang-tidy/checks/hicpp/avoid-c-arrays.rst (diff) |
| clang-tools-extra/docs/clang-tidy/checks/hicpp/avoid-goto.rst (diff) |
| clang-tools-extra/docs/clang-tidy/checks/hicpp/no-assembler.rst (diff) |
|
| llvm/test/lit.cfg.py (diff) |
| clang/lib/Tooling/DumpTool/generate_cxx_src_locs.py (diff) |
| compiler-rt/test/lit.common.cfg.py (diff) |
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
|
| clang/test/ParserOpenACC/parse-constructs.c (diff) |
| clang/include/clang/Basic/DiagnosticParseKinds.td (diff) |
| clang/lib/Parse/ParseOpenACC.cpp (diff) |
|
| libcxx/utils/data/unicode/emoji-data.txt (diff) |
| libcxxabi/test/vendor/ibm/aix_xlclang_passing_excp_obj_32.pass.sh.S (diff) |
| libunwind/src/UnwindRegistersSave.S (diff) |
| libunwind/src/DwarfInstructions.hpp (diff) |
| libcxxabi/test/vendor/ibm/aix_xlclang_passing_excp_obj_64.pass.sh.S (diff) |
Commit
341ca1ad0c32fc757680e9d5d302789b6458a7de
by github[test][msan] s390x already passes the test
3bc439bdff8bb5518098bd9ef52c56ac071276bc implemented overflow copying in a different way.
It's lucky to pass this test, but may fails in a different way.
Reviewers: thurstond, iii-i
Reviewed By: thurstond
Pull Request: https://github.com/llvm/llvm-project/pull/72710
|
| compiler-rt/test/msan/vararg_shadow.cpp (diff) |
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
Commit
a3f17ba3febbd546f2342ffc780ac93b694fdc8d
by Louis Dionne[libc++] Implement P2467R1: Support exclusive mode for fstreams
This patch brings std::ios_base::noreplace from P2467R1 to libc++.
This requires compiling the shared library in C++23 mode since otherwise
fstream::open(...) doesn't know about the new flag.
Differential Revision: https://reviews.llvm.org/D137640
Co-authored-by: Louis Dionne <ldionne.2@gmail.com>
|
| libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/open_pointer.pass.cpp (diff) |
| libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/open_pointer.pass.cpp (diff) |
| libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/pointer.pass.cpp (diff) |
| libcxx/include/ios (diff) |
| libcxx/docs/FeatureTestMacroTable.rst (diff) |
| libcxx/test/std/input.output/file.streams/fstreams/fstream.members/open_pointer.pass.cpp (diff) |
| libcxx/test/std/language.support/support.limits/support.limits.general/ios.version.compile.pass.cpp |
| libcxx/utils/generate_feature_test_macro_components.py (diff) |
| libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/pointer.pass.cpp (diff) |
| libcxx/docs/Status/Cxx23Papers.csv (diff) |
| libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp (diff) |
| libcxx/include/version (diff) |
| libcxx/docs/ReleaseNotes/18.rst (diff) |
| libcxx/include/fstream (diff) |
|
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
| llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll (diff) |
|
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
|
| compiler-rt/lib/builtins/assembly.h (diff) |
Commit
4323da926f12672daec7f59384bd153a7cf28674
by Jon Roelofs[MC][AsmParser] Diagnose improperly nested .cfi frames
This showed up when simplifying some large testcase, where the cfi directives
became out of sync with the proc's they enclose.
rdar://111459507
Differential revision: https://reviews.llvm.org/D155245
This reverts commit 4172fcc1ebbe0a7b699bfcbdaae9d5f688b62b09.
|
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
| lld/test/COFF/gc-dwarf-eh.s (diff) |
|
| clang/lib/Format/WhitespaceManager.h (diff) |
| clang/unittests/Format/FormatTest.cpp (diff) |
| clang/lib/Format/WhitespaceManager.cpp (diff) |
|
| clang/test/CodeGen/cspgo-instrumentation_thinlto.c (diff) |
Commit
506c47df00bbd9e527ecc5ac6e192b5fe5daa2c5
by github[mlir][memref] Rename ReifyRankedShapedTypeShapeOpInterface in comments (#72663)
ReifyRankedShapedTypeShapeOpInterface does not exis.
ReifyRankedShapedTypeShapeOpInterface ->
ReifyRankedShapedTypeOpInterface.
|
| mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h (diff) |
Commit
a05e736d288a7f2009ee9d057e78713d9adeeb5f
by github[msan][x86] Fix shadow if vararg overflow beyond kParamTLSSize
Caller puts argument shadow one by one into __msan_va_arg_tls, until it
reaches kParamTLSSize. After that it still increment OverflowOffset but
does not store the shadow.
Callee needs OverflowOffset to prepare a shadow for the entire overflow
area. It's done by creating "varargs shadow copy" for complete list of
args, copying available shadow from __msan_va_arg_tls, and clearing the
rest.
However callee does not know if the tail of __msan_va_arg_tls was not
able to fit an argument, and callee will copy tail shadow into "varargs
shadow copy", and later used as a shadow for an omitted argument.
So that unused tail of the __msan_va_arg_tls must be cleared if left
unused.
This allows us to enable compiler-rt/test/msan/vararg_shadow.cpp for
x86.
Reviewers: kstoimenov, thurstond
Reviewed By: thurstond
Pull Request: https://github.com/llvm/llvm-project/pull/72707
|
| compiler-rt/test/msan/vararg_shadow.cpp (diff) |
| llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll (diff) |
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
Commit
635756e4f3c5c0d31c11cea7b80108ea38570323
by github[X86] Place data in large sections for large code model (#70265)
This allows better interoperability mixing small/medium/large code model
code since large code model data can be put into separate large
sections.
And respect large data threshold under large code model.
gcc also does this: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html.
See https://groups.google.com/g/x86-64-abi/c/jnQdJeabxiU.
|
| llvm/test/CodeGen/X86/code-model-elf-sections.ll (diff) |
| llvm/lib/Target/TargetMachine.cpp (diff) |
Commit
813aaf39f94609a46f38f1e3a15a763a2cc0d2cf
by github[mlir][sparse] stress test BSR (#72712)
I always enjoy a good stress test. This end-to-end integration test
ensures the major ordering of both the block and within the block are
correctly handled (giving row-row, row-col, col-row and col-row as
options).
|
| mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir |
Commit
d5ab48e583c843393a86a4e166007688baeb1263
by github[AArch64] Simplify legalizer info for G_JUMP_TABLE and G_BRJT. (#71962)
Remove s64 as a valid type for G_JUMP_TABLE since I think it is always a
pointer?
Replace custom predicate for G_BRJT with a legalFor that checks 2 types.
|
| llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff) |
| llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (diff) |
Commit
e7f350951b304f0426832b0b6482c8bedf239c23
by github[msan][aarch64] Fix cleanup of unused part of overflow area
Similar to a05e736d288a7f2009ee9d057e78713d9adeeb5f.
Reviewers: thurstond, kstoimenov
Reviewed By: thurstond
Pull Request: https://github.com/llvm/llvm-project/pull/72722
|
| llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll (diff) |
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
|
| compiler-rt/test/msan/vararg_shadow.cpp (diff) |
Commit
66e9429e750401e34e5f2d8a97c956dfa61e3582
by github[msan][aarch64] Improve argument classification
Arm64 use multiple registers (varg slots) to pass arrays.
Reviewers: kstoimenov, thurstond
Reviewed By: thurstond
Pull Request: https://github.com/llvm/llvm-project/pull/72728
|
| llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (diff) |
| compiler-rt/test/msan/vararg_shadow.cpp (diff) |
| llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll (diff) |
|
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-select.mir (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir (diff) |
| llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir (diff) |
|
| compiler-rt/test/msan/vararg_shadow.cpp (diff) |
Commit
e2210cefb18171496573957945f9bd48eb631170
by github[LV] Pre-committing tests for changing loop interleaving count computation (#70272)
Added tests for evaluating changes to loop interleaving count computation and for removing loop interleaving threshold in subsequent patches.
|
| llvm/test/Transforms/LoopVectorize/AArch64/interleave_count.ll |
| llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll (diff) |
|
| clang/lib/Format/TokenAnnotator.cpp (diff) |
|
| mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir |
Commit
b8dface221f4490933b0d39deb769e97ca134e5f
by i[ELF] -r: rename orphan SHT_REL/SHT_RELA when the relocated input section is placed in an output section
This ports https://reviews.llvm.org/D40652 (--emit-relocs) to -r and
matches GNU ld.
Close #67910
|
| lld/ELF/LinkerScript.cpp (diff) |
| lld/test/ELF/linkerscript/emit-relocs-multiple.s (diff) |
| lld/test/ELF/linkerscript/emit-reloc-section-names.s (diff) |
Commit
424c4249cc55ef515914318b246ea9e408be75ab
by github[SimplifyCFG] Add optimization for switches of powers of two (#70977)
Optimization reduces the range for switches whose cases are positive powers
of two by replacing each case with count_trailing_zero(case).
Resolves #70756
|
| llvm/test/CodeGen/AArch64/switch-unreachable-default.ll (diff) |
| llvm/test/Transforms/SimplifyCFG/RISCV/switch-of-powers-of-two.ll |
| llvm/lib/Transforms/Utils/SimplifyCFG.cpp (diff) |
Commit
6da4ecdf9285225ccc8fa4441b7e9f65e8f4f49c
by github[InstCombine] Infer shift flags with unknown shamt (#72535)
Alive2: https://alive2.llvm.org/ce/z/82Wr3q
Related patch:
https://github.com/llvm/llvm-project/commit/2dd52b4527667837cc525aa48435ab5cbfa30a0b
|
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-and-shift.ll (diff) |
| llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll (diff) |
| llvm/test/Transforms/InstCombine/sub.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll (diff) |
| llvm/test/Transforms/InstCombine/onehot_merge.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll (diff) |
| llvm/test/Transforms/InstCombine/sub-of-negatible.ll (diff) |
| llvm/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll (diff) |
| llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll (diff) |
| llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll (diff) |
| llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll (diff) |
| llvm/test/Transforms/InstCombine/binop-of-displaced-shifts.ll (diff) |
| llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll (diff) |
| llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-d.ll (diff) |
| llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll (diff) |
| llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll (diff) |
| llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll (diff) |
| llvm/test/Transforms/InstCombine/shl-sub.ll (diff) |
| llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-b.ll (diff) |
| llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-shr.ll (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp (diff) |
| llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll (diff) |
| llvm/test/Transforms/InstCombine/shift.ll (diff) |
| llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll (diff) |
Commit
f8df86e34555b5947208d597013ba73e5757f335
by ericChange libc++ builder group name to match what I am using in the infra
Also change over to using group names instead of specific runner names.
This will prevent future downtime.
|
| .github/workflows/libcxx-build-and-test.yaml (diff) |
Commit
56d0e8ccf424ddcd74a505837b8966204aaba415
by github[Github] Print diff in code format helper (#72742)
Currently, when the code format action fails, it leaves no log of the
diff in the output within the action itself. This has caused confusion
for some users of the action, especially when the comment becomes buried
in a 100+ comment review and someone isn't super familiar with the inner
workings of the CI. This patch prints the diff produced by the code
formatter to stdout so that it is viewable by clicking on the failed
action. This should have very little cost and make things slightly less
confusing for those that run into this situation.
|
| llvm/utils/git/code-format-helper.py (diff) |
Commit
303a7835ff833278a0de20cf5a70085b2ae8fee1
by github[GreedyRA] Improve RA for nested loop induction variables (#72093)
Imagine a loop of the form:
```
preheader:
%r = def
header:
bcc latch, inner
inner1:
..
inner2:
b latch
latch:
%r = subs %r
bcc header
```
It can be possible for code to spend a decent amount of time in the
header<->latch loop, not going into the inner part of the loop as much.
The greedy register allocator can prefer to spill _around_ %r though,
adding spills around the subs in the loop, which can be very detrimental
for performance. (The case I am looking at is actually a very deeply
nested set of loops that repeat the header<->latch pattern at multiple
different levels).
The greedy RA will apply a preference to spill to the IV, as it is live
through the header block. This patch attempts to add a heuristic to
prevent that in this case for variables that look like IVs, in a similar
regard to the extra spill weight that gets added to variables that look
like IVs, that are expensive to spill. That will mean spills are more
likely to be pushed into the inner blocks, where they are less likely to
be executed and not as expensive as spills around the IV.
This gives a 8% speedup in the exchange benchmark from spec2017 when
compiled with flang-new, whilst importantly stabilising the scores to be
less chaotic to other changes. Running ctmark showed no difference in
the compile time. I've tried to run a range of benchmarking for
performance, most of which were relatively flat not showing many large
differences. One matrix multiply case improved 21.3% due to removing a
cascading chains of spills, and some other knock-on effects happen which
usually cause small differences in the scores.
|
| llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir (diff) |
| llvm/lib/CodeGen/SplitKit.cpp (diff) |
| llvm/lib/CodeGen/SplitKit.h (diff) |
| llvm/lib/CodeGen/RegAllocGreedy.cpp (diff) |
| llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir (diff) |
|
| clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp (diff) |
|
| llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp (diff) |
Commit
394bba766ddd2f5ea8ac8007dcadb724f79bafc4
by github[CodeGen][DebugInfo] Add missing debug info for jump table BB (#71021)
visitJumpTable is called on FinishBasicBlock. At that time, getCurSDLoc
will always return SDLoc without DebugLoc since CurInst was set to
nullptr after visiting each instruction.
This patch passes SDLoc to buildJumpTable when visiting SwitchInst so
that visitJumpTable can use it later.
|
| llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff) |
| llvm/test/DebugInfo/X86/debug-info-jump-table.ll (diff) |
| llvm/lib/CodeGen/SwitchLoweringUtils.cpp (diff) |
| llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (diff) |
| llvm/include/llvm/CodeGen/SwitchLoweringUtils.h (diff) |
Commit
f9974f7fe15a9e97ceb7514d437bef6ee46ccc38
by github[clang-tidy] Improve alternate snake case warnings (#71385)
Improves the accuracy of `readability-identifier-naming` for cases
`Camel_Snake_Case` and `camel_Snake_Back`. Prior to this commit, these
cases matched identifiers with **only** a leading upper case letter or
leading lower case letter respectively. Now, uppercase letters can only
appear at the start of an identifier or directly following an
underscore.
---
Currently, the regex for `Camel_Snake_Case` matches any identifier that
starts with a capital letter:
```
^[A-Z]([a-z0-9]*(_[A-Z])?)*
^^^^^^^^^-- underscore + capital letter after the first capital is optional
```
This means that `Camel_Snake_Case` matches other cases - in particular
`CamelCase` and `Leading_upper_snake_case` - which causes clang-tidy to
sometimes not flag incorrect casing. It also matches `UPPER_CASE`, but I
think it's reasonable to consider this a subset of `Camel_Snake_Case`
since some users may prefer e.g. `XML_Parser` to `Xml_Parser`. It's
really easy to accidentally type an identifier that clang-tidy doesn't
catch; all you have to do is omit an underscore or forget to capitalize
a letter. The same problem also applies to `camel_Snake_Back` except
that any identifier starting with a lower case letter matches, so I went
ahead and adjusted its regex too. Fixing it also uncovered a minor error
in an existing test.
|
| clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp (diff) |
| clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp (diff) |
| clang-tools-extra/docs/ReleaseNotes.rst (diff) |
| clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-case-match.cpp |
Commit
b00e2f2a5f3e48fbbe2324b0b371e5657ccd969c
by github[LLVM][DWARF] Add support for monolithic types in .debug_names (#70515)
Enable Type Units with DWARF5 accelerator tables for monolithic DWARF.
Implementation relies on linker to tombstone offset in LocalTU list to
-1 when
it deduplciates type units using COMDAT.
|
| llvm/test/DebugInfo/X86/accel-tables-dwarf5.ll (diff) |
| llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfFile.h (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp (diff) |
| llvm/lib/DWARFLinker/DWARFStreamer.cpp (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h (diff) |
| llvm/test/DebugInfo/X86/debug-names-dwarf64.ll (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (diff) |
| llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.cpp (diff) |
| llvm/lib/DWARFLinkerParallel/DWARFEmitterImpl.h (diff) |
| llvm/test/DebugInfo/X86/debug-names-types.ll |
| llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (diff) |
| llvm/include/llvm/CodeGen/AccelTable.h (diff) |
| llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test (diff) |
| llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h (diff) |
| llvm/test/MC/WebAssembly/comdat-sections.ll (diff) |
Commit
c093383ffadff8dfadfd6bc0ab7107a0e194aa7e
by github[SelectionDAG] Fix crash for salvaging with indirect debug values (#72645)
This is a follow-up to #68981, and fix for #72630, #72447.
We may end up in SelectionDAG::salvageDebugInfo() with indirect debug
values, and attempting to salvage ADD nodes with non-constant RHS would
lead us to try to turn those indirect debug values variadic, which is
not allowed.
This triggered the following assert in the SDDbgValue constructor:
Assertion `!(IsVariadic && IsIndirect)' failed.
This also adds a lit test for salvaging when having an indirect debug
value and constant RHS, as there seems like there was no such lit test.
However, I am not sure if the use of the stack_value operation is
correct in that case (which is existing behavior before #68981), but
that at least documents the current behavior.
|
| llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff) |
| llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll |
Commit
dc4786b4877d67d73d3892c45baf6811af0e6f57
by github[mlir][affine] remove divide zero check when simplifer affineMap (#64622) (#68519)
When performing constant folding on the affineApplyOp, there is a
division of 0 in the affine map.
[related issue](https://github.com/llvm/llvm-project/issues/64622)
---------
Co-authored-by: Javier Setoain <jsetoain@users.noreply.github.com>
|
| mlir/include/mlir/IR/AffineMap.h (diff) |
| mlir/lib/Analysis/FlatLinearValueConstraints.cpp (diff) |
| mlir/test/Dialect/Affine/constant-fold.mlir (diff) |
| mlir/include/mlir/IR/AffineExprVisitor.h (diff) |
| mlir/lib/IR/AffineExpr.cpp (diff) |
| mlir/lib/Dialect/Affine/IR/CMakeLists.txt (diff) |
| mlir/lib/Dialect/Affine/IR/AffineOps.cpp (diff) |
| mlir/lib/IR/AffineMap.cpp (diff) |
Commit
3b916ad6733b04a86ca0aec57be647daf4647d5b
by craig.topper[MC] Remove duplicate Contents field from MCLEBFragment.
There's already a Contents field in the MCEncodedFragmentWithFixups
base class. The Contents field in MCLEBFragment is private and there
is no accessor for it. It is initialized in the constructor, but that
should probably initialize the base class version.
|
| llvm/include/llvm/MC/MCFragment.h (diff) |
|
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-abs.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-bitreverse.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fcmp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-implicit-def.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-phi.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ctlz.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-addo-subo.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fptoi.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-load.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-dyn-alloca.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-phi.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-global.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-bitreverse.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-select.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-frame-index.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-bswap.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-global.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-itofp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-frame-index.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fshl-fshr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mulo.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-implicit-def.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rotate.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-itofp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-load.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-dyn-alloca-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ctlz.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mulo.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-cttz.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rotate.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-const.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fptoi.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-jump-table-brjt.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-select.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-bswap.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ctpop.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-addo-subo.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ext.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-fshl-fshr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ctpop.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-cttz.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-fcmp.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-const.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv32.mir |
|
| mlir/lib/IR/AffineMap.cpp (diff) |
|
| utils/bazel/llvm-project-overlay/mlir/BUILD.bazel (diff) |
Commit
a540808de254b18b304aa0915638a0900b36d9fa
by youngsuk.kim[CGObjCGNU] Remove unneeded method 'CGObjCGNUstep2::EnforceType' (NFC)
Method CGObjCGNUstep2::EnforceType is called from 2 call-sites to perform
bitcasts which are no-ops given that opaque pointers are enabled in LLVM.
Remove the method. Opaque ptr cleanup effort (NFC).
|
| clang/lib/CodeGen/CGObjCGNU.cpp (diff) |
|
| llvm/test/CodeGen/AArch64/shuffles.ll (diff) |
Commit
48c5c1b1f9ccb1b6ea05153b5a54f691f778c78b
by github[Github] Add build Flang docs in CI if autogenerated files change (#72721)
Currently, when changes are made to the tablegen files that build the
docs, the docs build is not tested. This should rarely cause breakages,
but it's cheap to test and there isn't a major reason not to.
|
| .github/workflows/docs.yml (diff) |
|
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir (diff) |
|
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir |
| llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (diff) |
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir |
| llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll |
|
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
Commit
7fd021a0929094bc4b6407896b735b7d360df36c
by flo[LV] Don't crash on vector masks during scalar VPReductionRecipe::exec.
VPReductionRecipe may be executed for scalar VFs. Make sure to access
part 0 of the condition, as it could be an active-lane-mask, which is a
vector <1 x i1>
Fixes https://github.com/llvm/llvm-project/issues/72720.
|
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
| llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll (diff) |
|
| llvm/include/llvm/CodeGen/TargetLowering.h (diff) |
| llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff) |
|
| llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll (diff) |
Commit
b08960f18888e96d64874486354c16b4116c5f8f
by youngsuk.kim[CGObjCMac] Replace calls to ConstantAggregateBuilderBase::addBitCast (NFC)
Replace calls to `ConstantAggregateBuilderBase::addBitCast` that involve a
no-op ptr-to-ptr bitcast.
Opaque ptr cleanup effort (NFC)
|
| clang/lib/CodeGen/CGObjCMac.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRAttributes.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRCore.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRCore.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRCore.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRInterfaces.cpp (diff) |
|
| mlir/lib/Bindings/Python/IRInterfaces.cpp (diff) |
Commit
4259198d65c1454b5cb5e60a46b2cce2544f1ca5
by jeremy.morse[DebugInfo][RemoveDIs] Support finding DPValues like dbg.values (#71952)
This patch extends findDbgValue and friends to optionally fill out a vector
of DPValue pointers, containing DPValues that refer to the sought Value.
This will allow us to incrementally add instrumentation to other
optimisation passes one-at-a-time, while un-instrumented passes will not
(yet) update DPValues.
Unit tests to check this behaves in the same way as dbg.values.
|
| llvm/unittests/IR/ValueTest.cpp (diff) |
| llvm/unittests/IR/DebugInfoTest.cpp (diff) |
| llvm/include/llvm/IR/DebugInfo.h (diff) |
| llvm/lib/IR/DebugInfo.cpp (diff) |
| llvm/lib/IR/Value.cpp (diff) |
Commit
695662b00c993dc33f7196c6d156c967a0aad6af
by youngsuk.kim[clang] Remove ConstantAggregateBuilderBase::addBitCast (NFC)
* Replace all existing uses of ConstantAggregateBuilderBase::addBitCast,
as they involve a no-op ptr-to-ptr bitcast
* Remove method ConstantAggregateBuilderBase::addBitCast
Opaque ptr cleanup effort (NFC)
|
| clang/include/clang/CodeGen/ConstantInitBuilder.h (diff) |
| clang/lib/CodeGen/CGObjCGNU.cpp (diff) |
Commit
1c1227846425883a3d39ff56700660236a97152c
by jiefu[clang] Remove unused selStructPtrTy in CGObjCGNU.cpp (NFC)
/llvm-project/clang/lib/CodeGen/CGObjCGNU.cpp:3674:15: error: variable 'selStructPtrTy' set but not used [-Werror,-Wunused-but-set-variable]
llvm::Type *selStructPtrTy = SelectorTy;
^
1 error generated.
|
| clang/lib/CodeGen/CGObjCGNU.cpp (diff) |
|
| clang/lib/CodeGen/CodeGenFunction.cpp (diff) |
Commit
934245891361ab8568aba10d4381d21fe1e8b699
by github[Github] Prevent scorecard action from running on forks (#72780)
Currently, the scorecard action runs on forks. This means that every
recent fork will be periodically running a job that doesn't really make
a lot of sense to run outside the main monorepo. This patch fixes that
by restricting the job to only run in the monorepo.
|
| .github/workflows/scorecard.yml (diff) |
Commit
aafd2119fa497e234a28ad7d912910e0a3e1296d
by agrossman154[Github] Fix typo
I swore I copied the if statement from somewhere, but whatever I did to
it while moving it over dropped one of the equals signs. This patch
fixes that so the action will actually work properly.
|
| .github/workflows/scorecard.yml (diff) |
|
| clang/test/CodeGenCXX/float128-declarations.cpp (diff) |
| clang/lib/Basic/Targets/OSTargets.h (diff) |
Commit
42204c94ba9fcb0b4b1335e648ce140a3eef8a9d
by morboRevert "[TargetInstrInfo] enable foldMemoryOperand for InlineAsm (#70743)"
This reverts commit 99ee2db198d86f685bcb07a1495a7115ffc31d7e.
It's causing ICEs in the ARM tests. See the comment here:
https://github.com/llvm/llvm-project/commit/99ee2db198d86f685bcb07a1495a7115ffc31d7e
|
| llvm/include/llvm/CodeGen/TargetInstrInfo.h (diff) |
| llvm/lib/CodeGen/TargetInstrInfo.cpp (diff) |
|
| libcxx/include/__string/char_traits.h (diff) |
Commit
dfe1d35c629f2948c0e8cf29d926729b1dbc1709
by github[InstCombine] Propagate NSW/NUW flags for `(X - Y) - Z -> X - (Y + Z)` (#72693)
Alive2: https://alive2.llvm.org/ce/z/gqeaVo
Related patch:
https://github.com/llvm/llvm-project/commit/31d219d2997fed1b7dc97e0adf170d5aaf65883e
|
| llvm/test/Transforms/InstCombine/sub-from-sub.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp (diff) |
|
| llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll (diff) |
|
| llvm/test/Analysis/ValueTracking/knownbits-and-or-xor-lowbit.ll (diff) |
| llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp (diff) |
|
| llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll (diff) |
Commit
ed7c97e0ad335eec8d65c00d8f963fea3455d4cf
by goldstein.w.nRecommit "[DAGCombiner] Transform `(icmp eq/ne (and X,C0),(shift X,C1))` to use rotate or to getter constants." (2nd Try)
Added missing check that the mask and shift amount added up to correct
bitwidth as well as test cases for the bug.
Closes #71729
|
| llvm/include/llvm/CodeGen/TargetLowering.h (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.h (diff) |
| llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff) |
|
| llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll |
|
| llvm/test/Transforms/InstCombine/eq-of-parts.ll (diff) |
| llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineInternal.h (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp (diff) |
|
| mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp (diff) |
| mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp (diff) |
| mlir/lib/Dialect/Affine/Utils/Utils.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h (diff) |
| mlir/include/mlir/Dialect/Affine/LoopUtils.h (diff) |
| mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp (diff) |
| mlir/lib/Dialect/Affine/Utils/LoopFusionUtils.cpp (diff) |
| mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp (diff) |
| mlir/lib/Dialect/Affine/IR/AffineOps.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/IR/AffineOps.td (diff) |
| mlir/include/mlir/Dialect/Affine/IR/AffineOps.h (diff) |
|
| clang/test/Driver/x86_64-nacl-defines.cpp (diff) |
| clang/test/Driver/wasm64-unknown-unknown.cpp (diff) |
| clang/test/Driver/lanai-unknown-unknown.cpp (diff) |
| clang/test/Driver/wasm32-unknown-unknown.cpp (diff) |
| clang/test/Driver/mipsel-nacl-defines.cpp |
|
| mlir/lib/Dialect/Affine/Utils/Utils.cpp (diff) |
| mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h (diff) |
| mlir/lib/Dialect/Affine/IR/AffineOps.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/IR/AffineOps.h (diff) |
| mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/LoopUtils.h (diff) |
| mlir/lib/Dialect/Affine/Utils/LoopFusionUtils.cpp (diff) |
| mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp (diff) |
| mlir/include/mlir/Dialect/Affine/IR/AffineOps.td (diff) |
| mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp (diff) |
|
| llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (diff) |
Commit
797b68c0ba699994e1038ac33d3083541482bf19
by martinRevert "[MC][AsmParser] Diagnose improperly nested .cfi frames"
This reverts commit 4323da926f12672daec7f59384bd153a7cf28674.
This broke building libffi for ARM on Windows (and probably Darwin),
where one extern function intentionally falls through to another
one, while sharing one CFI region.
As long as one isn't using .subsections_via_symbols on MachO,
this probably shouldn't be a hard error.
Secondly, the tested pattern only produces an error on MachO and
COFF targets, but not for ELF, making the error case even more
inconsistent.
Reverting this commit for now, to figure out the best way forward.
|
| llvm/lib/MC/MCParser/AsmParser.cpp (diff) |
| llvm/test/MC/AArch64/cfi-bad-nesting.s |
| lld/test/COFF/gc-dwarf-eh.s (diff) |
|
| clang/lib/Format/WhitespaceManager.h (diff) |
| clang/unittests/Format/FormatTest.cpp (diff) |
|
| clang/unittests/Format/FormatTestComments.cpp (diff) |
| clang/lib/Format/TokenAnnotator.cpp (diff) |
|
| clang/unittests/Format/TokenAnnotatorTest.cpp (diff) |
| clang/lib/Format/TokenAnnotator.cpp (diff) |
|
| clang/lib/Format/TokenAnnotator.cpp (diff) |
| clang/unittests/Format/FormatTest.cpp (diff) |
| clang/unittests/Format/TokenAnnotatorTest.cpp (diff) |
|
| .mailmap (diff) |
Commit
eb7698254ab668e53133062fbc53b9635de95c4d
by github[PowerPC][EarlyIfConversion] Do not insert `isel` if subtarget doesn't support `isel` (#72211)
Some subtargets of PPC don't support `isel` instruction, early-ifcvt
should not insert this instruction.
|
| llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (diff) |
| llvm/test/CodeGen/PowerPC/early-ifcvt-no-isel.mir (diff) |
|
| clang/lib/CodeGen/CGBuiltin.cpp (diff) |
| clang/lib/CodeGen/CodeGenFunction.h (diff) |
Commit
3494c555c93c5f5cf5c36a84a819b80a4d922a82
by github[RISCV] postpone removal in initundef pass (#71661)
InitUndef pass need replace the implicit def with Undef pseudo, but
current remove method will make noreg2implicit borken.
This patch postpone the removal until all basicblock be processed.
|
| llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp (diff) |
| llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir |
| llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll (diff) |
Commit
95d584c6ac5b518a66992293b4ff63fc05a81685
by github[InstCombine] Convert or concat to fshl if opposite or concat exists (#68502)
If there are two 'or' instructions concat variables in opposite order
and the first 'or' dominates the second one, the second 'or' can be
optimized to fshl to rotate shift first 'or'. This can eliminate an shl
and expose more optimization opportunity for bswap/bitreverse.
|
| llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (diff) |
| llvm/test/Transforms/InstCombine/funnel.ll (diff) |
Commit
69f64dedb09bf39bd3ad66bcbc2c947b23342a11
by luke[RISCV] Use DemandedFields instead of checking for vmv.s.x/vmv.x.s. NFC
The property we're explicitly looking for is whether or not MI only cares about
VL zeroness and not VL itself, so we can just use DemandedFields for this. This
should simplify an upcoming change in #72352
|
| llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (diff) |
Commit
933dd03386df3c0cfedf4fe6bc984d776f1298ca
by luke[RISCV] Remove checks that MI's info is valid. NFC
It's always guaranteed to be valid since we compute it ourselves from MI.
This should simplify an upcoming change in #72352
|
| llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (diff) |
|
| .github/CODEOWNERS (diff) |
Commit
c1fe1900491ae773e45e41604af25312e5fc6559
by omair.javaidRevert "Add new API in SBTarget for loading core from SBFile (#71769)"
This reverts commit e2fb816c4f0286ddf8b1030148a343d5efc14e01.
It breaks TestLinuxCore.py on lldb-*-windows. See buildbot below:
https://lab.llvm.org/buildbot/#/builders/219/builds/7014
|
| lldb/source/API/SBTarget.cpp (diff) |
| lldb/include/lldb/API/SBTarget.h (diff) |
| lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py (diff) |
Commit
d572c4cdef4b3a2b1f57769233f33a1788f5172e
by github[PowerPC] Disable float128 on AIX in Clang (#67298)
PowerPC AIX backend does not support float128 at all. Diagnose even when
specifying -mfloat128 to avoid backend crash.
---------
Co-authored-by: Kai Luo <gluokai@gmail.com>
|
| clang/test/Sema/128bitfloat.cpp (diff) |
| clang/lib/Basic/Targets/PPC.cpp (diff) |
|
| llvm/test/CodeGen/PowerPC/select-cc-no-isel.ll |
|
| llvm/include/llvm/Target/TargetSelectionDAG.td (diff) |
| llvm/lib/Target/ARM/ARMISelLowering.cpp (diff) |
| llvm/test/CodeGen/ARM/fpenv.ll (diff) |
| llvm/lib/Target/ARM/ARMInstrVFP.td (diff) |
|
| llvm/test/MC/AArch64/SME/fa64-implies-sve2.s |
| llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll |
| llvm/lib/Target/AArch64/AArch64SchedA64FX.td (diff) |
| clang/lib/Basic/Targets/AArch64.cpp (diff) |
| llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll |
| clang/lib/Basic/Targets/AArch64.h (diff) |
| llvm/include/llvm/TargetParser/AArch64TargetParser.h (diff) |
| llvm/lib/Target/AArch64/AArch64Subtarget.cpp (diff) |
| llvm/lib/Target/AArch64/AArch64InstrInfo.td (diff) |
| llvm/unittests/TargetParser/TargetParserTest.cpp (diff) |
| llvm/lib/Target/AArch64/AArch64.td (diff) |
Commit
bf897d5d77e974486e37d33e83f50f5ea95390fa
by github[mlir][vector] Extend TransferReadDropUnitDimsPattern to support partially-static memrefs (#72142)
This patch extends TransferReadDropUnitDimsPattern to support dropping
unit dims from partially-static memrefs, for example:
%v = vector.transfer_read %base[%c0, %c0], %pad {in_bounds = [true, true]} :
memref<?x1xi8, strided<[?, ?], offset: ?>>, vector<[16]x1xi8>
Is rewritten as:
%dim0 = memref.dim %base, %c0 : memref<?x1xi8, strided<[?, ?], offset: ?>>
%subview = memref.subview %base[0, 0] [%dim0, 1] [1, 1] :
memref<?x1xi8, strided<[?, ?], offset: ?>> to memref<?xi8, #map1>
%v = vector.transfer_read %subview[%c0], %pad {in_bounds = [true]}
: memref<?xi8, #map1>, vector<[16]xi8>
Scalable vectors are now also supported, the scalable dims were being
dropped when creating the rank-reduced vector type. The xfer op can also
have a mask of type 'vector.create_mask', which gets rewritten as long
as the mask of the unit dim is a constant of 1.
|
| mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp (diff) |
| mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir (diff) |
|
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
| llvm/include/llvm/LinkAllPasses.h (diff) |
| llvm/lib/Transforms/Scalar/GuardWidening.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/include/llvm/Transforms/Scalar.h (diff) |
|
| llvm/include/llvm/LinkAllPasses.h (diff) |
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/lib/Transforms/Scalar/LoopSink.cpp (diff) |
| llvm/include/llvm/Transforms/Scalar.h (diff) |
Commit
cd11a7fba44d92ca018a2b418da69b8a680614f3
by github[NewPM] Remove LoopInstSimplifyLegacyPass (#72812)
This pass isn't used anywhere and thus has no test coverage. Remove it
for these reasons.
For whatever reason, there was no entry in
`llvm/include/llvm/LinkAllPasses.h` to remove.
|
| llvm/include/llvm/Transforms/Scalar.h (diff) |
| llvm/lib/Transforms/Scalar/LoopInstSimplify.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
|
| llvm/include/llvm/Transforms/Scalar.h (diff) |
| llvm/include/llvm/LinkAllPasses.h (diff) |
| llvm/lib/Transforms/Scalar/MergedLoadStoreMotion.cpp (diff) |
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
Commit
7e65dc72c4251cb7409545686bc2751d50d4efae
by zinenkoRevert "Apply clang-tidy fixes for misc-include-cleaner in IRCore.cpp (NFC)"
This reverts commit 0d109035c29408f06efc148d67aab7e4b2aada5d.
Changes make Python bindings unbuildable without additional cmake
modifications (or modified `$PATH`).
```
/llvm-project/mlir/lib/Bindings/Python/IRCore.cpp:33:10: fatal error: 'funcobject.h' file not found
```
This header is provided by cpython, and we are not looking for that in
cmake.
Moreover, the nature of this change is not very clear to me. Seems to
replace one include with two dozens, presumably because the code is only
using transitively included headers, but the value for readability is
dubious. LLVM is also not strictly following IWYU.
|
| mlir/lib/Bindings/Python/IRCore.cpp (diff) |
Commit
61332cb047faca2dffce9a0ae68bf0d1c0cdee39
by github[AMDGPU] Emit backend_stack_size PAL metadata (#72509)
For chain functions, PAL uses a `backend_stack_size` metadata item,
which at the moment has the same meaning as `stack_frame_size_in_bytes`.
We emit both for now in order to simplify coordination with PAL.
The new item must be emitted in the `shader_functions` section, just as
the metadata for other module entry functions. For simplicity, we mark
chain functions as module entry functions and emit the same metadata for
all of them.
|
| llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp (diff) |
| llvm/test/CodeGen/AMDGPU/amdpal-chain-metadata.ll |
| llvm/test/CodeGen/AMDGPU/amdpal-callable.ll (diff) |
| llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (diff) |
Commit
3cc523d935427baf62766e9e2cc7b65eca5925bb
by github[NewPM] Remove UnifyFunctionExitNodesLegacyPass (#72816)
UnifyFunctionExitNodesLegacyPass isn't used anywhere in upstream and
thus isn't tested at all. For these reasons, remove it.
|
| llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp (diff) |
| llvm/include/llvm/LinkAllPasses.h (diff) |
| llvm/lib/Transforms/Utils/Utils.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/include/llvm/Transforms/Utils/UnifyFunctionExitNodes.h (diff) |
Commit
72ab99500f45d8672f91fe4d75ffdc6f5146b007
by github[NewPM] Remove AssumeBundleBuilderPassLegacyPass (#72817)
This pass isn't used upstream anywhere and doesn't have have a
create...() function, thus isn't tested anywhere. Because of this,
remove it.
|
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp (diff) |
| llvm/lib/Transforms/Utils/Utils.cpp (diff) |
|
| llvm/lib/Transforms/Scalar/LowerWidenableCondition.cpp (diff) |
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/include/llvm/Transforms/Scalar.h (diff) |
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
|
| flang/lib/Semantics/check-omp-structure.cpp (diff) |
| clang/lib/AST/StmtProfile.cpp (diff) |
| clang/tools/libclang/CIndex.cpp (diff) |
| clang/lib/Serialization/ASTReader.cpp (diff) |
| clang/test/OpenMP/atomic_ast_print.cpp (diff) |
| clang/include/clang/Sema/Sema.h (diff) |
| clang/include/clang/Basic/DiagnosticSemaKinds.td (diff) |
| clang/test/OpenMP/atomic_messages.cpp (diff) |
| clang/include/clang/Basic/OpenMPKinds.h (diff) |
| clang/lib/AST/OpenMPClause.cpp (diff) |
| llvm/include/llvm/Frontend/OpenMP/OMP.td (diff) |
| clang/lib/Basic/OpenMPKinds.cpp (diff) |
| clang/lib/Sema/TreeTransform.h (diff) |
| clang/lib/Parse/ParseOpenMP.cpp (diff) |
| clang/lib/Sema/SemaOpenMP.cpp (diff) |
| clang/include/clang/AST/RecursiveASTVisitor.h (diff) |
| clang/lib/Serialization/ASTWriter.cpp (diff) |
| clang/include/clang/AST/OpenMPClause.h (diff) |
| clang/include/clang/Basic/OpenMPKinds.def (diff) |
| clang/lib/CodeGen/CGStmtOpenMP.cpp (diff) |
|
| llvm/include/llvm/InitializePasses.h (diff) |
| llvm/lib/Transforms/Scalar/Scalarizer.cpp (diff) |
| llvm/include/llvm/LinkAllPasses.h (diff) |
| llvm/lib/Transforms/Scalar/Scalar.cpp (diff) |
| llvm/include/llvm/Transforms/Scalar/Scalarizer.h (diff) |
Commit
3300bc34f7bccf29c14221fa4b651f7bc82c46d5
by github[llvm-exegesis] Fix race condition in subprocess mode (#72778)
If there were some scheduler effects where something like the parent
process got interrupted while the child process continued to run, there
would be nothing blocking it from exiting before the parent process
issued a PTRACE_ATTACH call. This would cause transient failures as this
occurred pretty rarely. This patch removes the possibility of a
transient failure by ensuring that the parent process attaches to the
child process before sending the counter file descriptor through the
socket, ensuring that the child process has at most progressed to being
blocked in the read call for the counter file descriptor.
|
| llvm/test/tools/llvm-exegesis/X86/latency/memory-annotations-livein.s (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/memory-annotations.s (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/subprocess-abnormal-exit-code.s (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/subprocess-preserved-registers.s (diff) |
| llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/subprocess.s (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/subprocess-segfault.s (diff) |
Commit
27c98958c067c341dd3f65b7218c376d333fbed5
by github[llvm-exegesis] Preserve rcx and r11 around system call (#72807)
Currently, when making the ioctl system call, we're not preserving rcx
and r11. The system call will clobber these registers, meaning that the
values of the registers in the snippet will be different than expected.
This patch fixes that be preserving the registers around the system
call, similar to how the other registers involved in the making the
system call get preserved.
Fixes #72741.
|
| llvm/tools/llvm-exegesis/lib/X86/Target.cpp (diff) |
| llvm/test/tools/llvm-exegesis/X86/latency/subprocess-preserved-registers.s (diff) |
|
| mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp (diff) |
|
| mlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp (diff) |
|
| mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp (diff) |
|
| mlir/lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp (diff) |
|
| mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp (diff) |
|
| llvm/test/CodeGen/PowerPC/aix-csr-alloc.ll |
| llvm/test/CodeGen/PowerPC/aix-csr-alloc.mir |
| llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir |
Commit
f7b5c255070ef2d8a4492a45613a6a7df0b5f0cb
by github[AArch64][SME] Remove immediate argument restriction for svldr and svstr (#68565)
The svldr_vnum and svstr_vnum builtins always modify the base register
and tile slice and provide immediate offsets of zero, even when the
offset provided to the builtin is an immediate. This patch optimises the
output of the builtins when the offset is an immediate, to pass it
directly to the instruction and to not need the base register and tile
slice updates.
|
| llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff) |
| llvm/include/llvm/IR/IntrinsicsAArch64.td (diff) |
| llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll (diff) |
| llvm/lib/Target/AArch64/AArch64ISelLowering.h (diff) |
| llvm/lib/Target/AArch64/SMEInstrFormats.td (diff) |
| clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c (diff) |
| mlir/test/Target/LLVMIR/arm-sme.mlir (diff) |
| mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td (diff) |
| llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll (diff) |
| clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c (diff) |
| clang/lib/CodeGen/CGBuiltin.cpp (diff) |
Commit
befa925acac8fd6a9266e76acdec8d8c664abdc8
by github[MachineLICM][AArch64] Hoist COPY instructions with other uses in the loop (#71403)
When there is a COPY instruction in the loop with other uses, we want to
hoist the COPY, which in turn leads to the users being hoisted as well.
Co-authored-by David Green : David.Green@arm.com
|
| llvm/test/CodeGen/AMDGPU/sdiv64.ll (diff) |
| llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll (diff) |
| llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll (diff) |
| llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll (diff) |
| llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll (diff) |
| llvm/lib/CodeGen/MachineLICM.cpp (diff) |
| llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll (diff) |
| llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll (diff) |
| llvm/test/CodeGen/X86/avx512-i1test.ll (diff) |
| llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll (diff) |
| llvm/test/CodeGen/AMDGPU/local-atomics-fp.ll (diff) |
| llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll (diff) |
| llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll (diff) |
| llvm/test/CodeGen/AMDGPU/udiv64.ll (diff) |
| llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll (diff) |
| llvm/test/CodeGen/X86/pr53842.ll (diff) |
| llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll (diff) |
| llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (diff) |
| llvm/test/CodeGen/AArch64/tbl-loops.ll (diff) |
| llvm/test/CodeGen/X86/pr38795.ll (diff) |
| llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll (diff) |
| llvm/test/CodeGen/AArch64/zext-to-tbl.ll (diff) |
| llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (diff) |
| llvm/test/CodeGen/X86/pr63108.ll (diff) |
| llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll (diff) |
| llvm/test/CodeGen/AMDGPU/srem64.ll (diff) |
| llvm/test/CodeGen/AMDGPU/urem64.ll (diff) |
|
| llvm/test/CodeGen/AArch64/neon-bitcast.ll (diff) |
| llvm/test/CodeGen/AArch64/zext-to-tbl.ll (diff) |
| llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll (diff) |
| llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff) |
| llvm/test/CodeGen/AArch64/aarch64-load-ext.ll (diff) |
| llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll |
Commit
32c3decb773b0cc7fd1736fe1b47d889c8c0011c
by github[mlir][vector] Modernize `vector.transpose` op (#72594)
* Declare arguments/results with `let` statements.
* Rename `transp` to `permutation`.
* Change type of `transp` from `I64ArrayAttr` to `DenseI64ArrayAttr`
(provides direct access to `ArrayRef<int64_t>` instead of `ArrayAttr`).
|
| mlir/lib/IR/AffineMap.cpp (diff) |
| mlir/include/mlir/Dialect/Vector/IR/VectorOps.td (diff) |
| mlir/lib/Dialect/Arith/Transforms/IntNarrowing.cpp (diff) |
| mlir/lib/Dialect/Vector/IR/VectorOps.cpp (diff) |
| mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp (diff) |
| mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp (diff) |
| mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp (diff) |
| mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp (diff) |
| mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp (diff) |
| mlir/include/mlir/IR/AffineMap.h (diff) |
| mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp (diff) |
Commit
4028dd2e93fa1697b68339b04b89f5ddbf7f9aea
by github[InstSimplify] Fold converted urem to 0 if there's no overlapping bits (#71528)
When folding urem instructions we can end up not recognizing that
the output will always be 0 due to Value*s being different, despite
generating the same data (in this case, 2 different calls to vscale).
This patch recognizes the (x << N) & (add (x << M), -1) pattern that
instcombine replaces urem with after the two vscale calls have been
reduced to one via CSE, then replaces with 0 when x is a power of 2
and N >= M.
|
| llvm/lib/Analysis/InstructionSimplify.cpp (diff) |
| llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll (diff) |
Commit
761a963dfc8f80af9c5487997d5bdacb3e2c0062
by github[DAG] narrowExtractedVectorBinOp - ensure we limit late node creation to LegalOperations only (#72130)
Avoids infinite issues in some upcoming patches to help D152928 - x86 sees a number of regressions that are addressed by extending SimplifyDemandedVectorEltsForTargetNode to cover more binop opcodes
|
| llvm/test/CodeGen/X86/kshift.ll (diff) |
| llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll (diff) |
| llvm/test/Analysis/CostModel/AArch64/vector-select.ll (diff) |
| llvm/test/CodeGen/X86/avx512-insert-extract.ll (diff) |
| llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff) |
| llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
|
| clang/include/clang/Basic/DiagnosticSemaKinds.td (diff) |
Commit
5d353423c97517ae1dc66506186e265538b0111f
by flo[LAA] Add extra test for #70819 showing incorrect Forward dep.
Add an additional test case where we currently incorrectly identify a
dependence as Foward instead of ForwardButPreventsForwarding.
Also cleans up the names in the tests a bit to improve readability.
|
| llvm/test/Analysis/LoopAccessAnalysis/forward-negative-step.ll (diff) |
|
| llvm/lib/Target/AArch64/AArch64InstrInfo.td (diff) |
| llvm/test/CodeGen/AArch64/bf16.ll (diff) |
|
| clang/lib/AST/Interp/ByteCodeExprGen.cpp (diff) |
| clang/lib/AST/Interp/ByteCodeExprGen.h (diff) |
|
| llvm/test/CodeGen/X86/vector-half-conversions.ll (diff) |
|
| llvm/lib/Target/ARM/ARMMacroFusion.cpp (diff) |
| llvm/lib/Target/PowerPC/PPCMacroFusion.cpp (diff) |
| llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp (diff) |
| llvm/lib/Target/X86/X86MacroFusion.cpp (diff) |
|
| clang/lib/AST/Interp/Interp.h (diff) |
|
| llvm/cmake/modules/AddLLVM.cmake (diff) |
Commit
57a11b7f75742ba74b563b8af75bc106a1e9d29e
by github[AMDGPU] Add live-through register set printing to GCNRegPressurePrinter pass. (#71096)
Add live-through register set printing, assuming live-through register
is in live-in and live-out sets, has no redefinitions but may have uses
in the block.
|
| llvm/test/CodeGen/AMDGPU/regpressure_printer.mir (diff) |
| llvm/lib/Target/AMDGPU/GCNRegPressure.cpp (diff) |
Commit
cd88047765a3242f1ebc8d25ec2eeb7752d44867
by github[NFC][SROA] Remove implementation details from SROA header (#72846)
This moves the SROA implementation from SROAPass into a separate SROA
class that is defined in the cpp file, and reduces the SROAPass class to
a thin NewPM wrapper. This allows to remove all implementation details
from the SROA header, and the SROALegacyPass can wrap the SROA class
instead of the NewPM SROAPass.
The trigger for this change is a GCC warning about visibility of
implementation details in the SROA header after D138238. Credits to
Nikita Popov for suggesting this reorganization.
|
| llvm/include/llvm/Transforms/Scalar/SROA.h (diff) |
| llvm/lib/Transforms/Scalar/SROA.cpp (diff) |
Commit
ba24b814f2a20a136f0a7a0b492b6ad8a62114c6
by npopov[llvm-c] Fix outdated comment (NFC)
Use the function value type instead of the element type of the
function pointer type.
Fixes https://github.com/llvm/llvm-project/issues/72798.
|
| llvm/lib/IR/Core.cpp (diff) |
|
| mlir/docs/Tools/MLIRLSP.md (diff) |
Commit
4d64a2bcd31818aa0aed0ce9e6b64898a6f0eb55
by github[LV] Refactor vector function variant selection to prepare for uniform args (#68879)
Parameters marked as uniform take a scalar value, assuming the value is
invariant in the scalar loop. In order to support this, we need to stop
asking for a vector function variant with a default shape assuming that all
arguments will become vector arguments, and instead consider all available
variants and their parameter types.
|
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
| llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp (diff) |
|
| llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll |
| llvm/test/Transforms/LoopVectorize/uniform-args-call-variants.ll |
Commit
28b5054751899c9e96c2f42f0f91f1a3d73f0381
by github[AMDGPU] Fix PromoteAlloca size check of alloca for store (#72528)
When storing a subvector, too many element were written when the
size of the alloca is smaller than the size of the vector store.
This patch checks for the minimum of the alloca vector and the
store vector to determine the number of elements to store.
|
| llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll (diff) |
| llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp (diff) |
Commit
c4c52d4199e13125fd9560f9f3b2d8a6bf2582f2
by github[mlir][ArmSME] Move vector.extract/insert lowerings to vector-to-arm-sme (NFC) (#72852)
These were placed in LegalizeForLLVMExport.cpp, which is the wrong stage
for these, as these lower to high-level ArmSME ops, not intrinsics.
|
| mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp (diff) |
| mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp (diff) |
|
| llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll |
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
Commit
f9c47e89c1d6433e3bc28e756e08ebc600a38946
by github[LV] Stability fix for outerloop vectorization (#68118)
HCFG builder doesn't correctly handle cases when non-outermost loop is
requested to be vectorized
[Original] Differential Revision: https://reviews.llvm.org/D150700
|
| llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp (diff) |
| llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll |
|
| llvm/test/CodeGen/X86/constant-pool-sharing.ll (diff) |
Commit
2fdf283c3f7977b12965183ed64c8c0d3f22fa82
by llvm-dev[X86] constant-pool-sharing.ll - add test showing failure to reuse subvectors when storing larger vector types
We do correctly use implicit zero-extension of xmm constant load -> ymm constant store though.
|
| llvm/test/CodeGen/X86/constant-pool-sharing.ll (diff) |
Commit
b0154c36d6387272f7f961c22582693d2850d21c
by github[InstrProf] Add pgo use block coverage test (#72443)
Back in https://reviews.llvm.org/D124490 we added a block coverage mode
that instruments a subset of basic blocks using single byte counters to
get coverage for the whole function.
This commit adds a test to make sure that we correctly assign branch
weights based on the coverage profile.
I noticed this test was missing after seeing that we had no coverage on
`PGOUseFunc::populateCoverage()`
https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp.html#L1383
|
| llvm/test/Transforms/PGOProfile/coverage.ll (diff) |
| llvm/lib/ProfileData/InstrProfReader.cpp (diff) |
| llvm/test/Transforms/PGOProfile/Inputs/coverage.proftext |
| llvm/lib/ProfileData/InstrProfWriter.cpp (diff) |
|
| llvm/lib/Analysis/InstructionSimplify.cpp (diff) |
|
| llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp (diff) |
| llvm/test/Transforms/InstCombine/known-signbit-shift.ll (diff) |
Commit
59d14b623357d9b0514a9575e6d92474694b2f74
by llvm-dev[X86] combineLoad - try to reuse existing constant pool entries for smaller vector constant data (REAPPLIED)
If we already have a YMM/ZMM constant that a smaller XMM/YMM has matching lower bits, then ensure we reuse the same constant pool entry.
Extends the similar combines we already have to reuse VBROADCAST_LOAD/SUBV_BROADCAST_LOAD constant loads.
This is a mainly a canonicalization, but should make it easier for us to merge constant loads in a future commit (related to both #70947 and better X86FixupVectorConstantsPass usage for #71078).
Reapplied with fix to ensure we don't 'flip-flop' between multiple matching constants - only perform the fold if the new constant pool entry is larger than the current entry.
|
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll (diff) |
| llvm/lib/Target/X86/X86ISelLowering.cpp (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll (diff) |
| llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll (diff) |
|
| .github/CODEOWNERS (diff) |
Commit
8bd06d5b65845e5e01dd899a2deb773580460b89
by github[C23] Complete support for WG14 N2508 (#71398)
In Clang 16, we implemented the ability to add a label at the end of a
compound statement. These changes complete the implementation by
allowing a label to be followed by a declaration in C.
Note, this seems to have fixed an issue with some OpenMP stand-alone
directives not being properly diagnosed as per:
https://www.openmp.org/spec-html/5.1/openmpsu19.html#x34-330002.1.3
(The same requirement exists in OpenMP 5.2 as well.)
|
| clang/test/C/C2x/n2508.c (diff) |
| clang/test/OpenMP/barrier_messages.cpp (diff) |
| clang/test/OpenMP/scan_messages.cpp (diff) |
| clang/include/clang/Parse/Parser.h (diff) |
| clang/www/c_status.html (diff) |
| clang/test/OpenMP/flush_messages.cpp (diff) |
| clang/test/OpenMP/cancel_messages.cpp (diff) |
| clang/test/OpenMP/barrier_ast_print.cpp (diff) |
| clang/test/OpenMP/taskyield_messages.cpp (diff) |
| clang/test/OpenMP/taskwait_messages.cpp (diff) |
| clang/include/clang/Basic/DiagnosticParseKinds.td (diff) |
| clang/test/OpenMP/error_message.cpp (diff) |
| clang/lib/Parse/ParseOpenMP.cpp (diff) |
| clang/docs/ReleaseNotes.rst (diff) |
| clang/lib/Parse/ParseStmt.cpp (diff) |
| clang/test/OpenMP/cancellation_point_messages.cpp (diff) |
| clang/test/OpenMP/depobj_messages.cpp (diff) |
Commit
197f30597d086e4466687fa533d3142fa404b1fc
by krasimirNFCI: update debug-names-types test to use an output file unique to the test
This makes it work in environments where the test is running in a write-protected
current directory. Updated similarly to other such tests, like
https://github.com/llvm/llvm-project/blob/8bd06d5b65845e5e01dd899a2deb773580460b89/llvm/test/tools/llvm-dwp/X86/absolute_paths.test#L3.
|
| llvm/test/DebugInfo/X86/debug-names-types.ll (diff) |
Commit
a32a2b2ceb6b4c1bbcbcb39363c8dee44daf86ab
by github[clang][driver] Add <executable>/../include/c++/v1 to include path on Darwin (#70817)
On macOS, when clang is invoked via a symlink, since the InstalledDir is
where the link is located, the C++ headers are not identified and the
default system headers from the SDK are used.
This can be undesirable if a toolchain is created by symlinking clang
into a directory and placing libc++ headers in that directory with the
intent of those headers overriding the SDK headers. This change solves
that problem by also looking for libc++ headers in the toolchain-relative
location of the executable symlink, if any.
|
| clang/test/Driver/darwin-header-search-libcxx.cpp (diff) |
| clang/lib/Driver/ToolChains/Darwin.cpp (diff) |
Commit
c38ae74b48c1cb8aedf384686eaa05815d366609
by github[libc++] Stop checking for trailing whitespace in check-generated-output (#72711)
Trailing whitespace is removed by clang-format, so if someone tries to
check-in new code with trailing whitespaces, it'll be caught by the
clang-format job. Removing this duplication helps reduce the confusion
around our numerous ways of enforcing formatting rules.
|
| libcxx/utils/ci/run-buildbot (diff) |
Commit
f609d4ba1d940c781f4fed44f7c69422d1766f09
by a.bataev[SLP]Fix PR72833: do not crash if only operand is casted but the use
instruction.
Need to check if only operand is casted, not the user instruction
itself, if the types of the operands does not match the actual type.
|
| llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) |
| llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll |
|
| flang/lib/Lower/OpenMP.cpp (diff) |
Commit
ddfed815c930979414d403e01caca23875072676
by Krzysztof.ParzyszekRevert "[OpenMP] atomic compare fail : Parser & AST support"
This reverts commit edd675ac283909397880f85ba68d0d5f99dc1be2.
This breaks clang build where every component is a shared library.
The file clang/lib/Basic/OpenMPKinds.cpp, which is a part of
libclangBasic.so, uses `getOpenMPClauseName` which isn't:
/usr/bin/ld: CMakeFiles/obj.clangBasic.dir/OpenMPKinds.cpp.o: in functio
n `clang ::getOpenMPSimpleClauseTypeName(llvm::omp::Clause, unsigned int
)':
OpenMPKinds.cpp:(.text._ZN5clang29getOpenMPSimpleClauseTypeNameEN4llvm3o
mp6ClauseEj+0x9b): undefined reference to `llvm::omp::getOpenMPClauseNam
e(llvm::omp::Clause)'
|
| clang/lib/Basic/OpenMPKinds.cpp (diff) |
| clang/include/clang/Basic/DiagnosticSemaKinds.td (diff) |
| clang/test/OpenMP/atomic_ast_print.cpp (diff) |
| clang/lib/Serialization/ASTWriter.cpp (diff) |
| clang/include/clang/Basic/OpenMPKinds.h (diff) |
| clang/include/clang/Sema/Sema.h (diff) |
| clang/include/clang/AST/RecursiveASTVisitor.h (diff) |
| clang/lib/CodeGen/CGStmtOpenMP.cpp (diff) |
| clang/lib/Serialization/ASTReader.cpp (diff) |
| clang/test/OpenMP/atomic_messages.cpp (diff) |
| clang/include/clang/AST/OpenMPClause.h (diff) |
| clang/lib/Sema/TreeTransform.h (diff) |
| clang/tools/libclang/CIndex.cpp (diff) |
| flang/lib/Semantics/check-omp-structure.cpp (diff) |
| clang/lib/AST/OpenMPClause.cpp (diff) |
| clang/lib/AST/StmtProfile.cpp (diff) |
| clang/include/clang/Basic/OpenMPKinds.def (diff) |
| llvm/include/llvm/Frontend/OpenMP/OMP.td (diff) |
| clang/lib/Parse/ParseOpenMP.cpp (diff) |
| clang/lib/Sema/SemaOpenMP.cpp (diff) |
Commit
5e36c64cb6e8f9c6c0c2db8a9a7120b28fbc36df
by david[flang] Remove extra space added with --dependent-lib option
This patch fixes a bug with the --dependent-lib option where an
extra space is added to the directive causing linking to fail.
|
| flang/test/Driver/dependent-lib.f90 (diff) |
| flang/lib/Frontend/FrontendActions.cpp (diff) |
|
| clang/lib/AST/Interp/InterpBlock.h (diff) |
| clang/lib/AST/Interp/Interp.h (diff) |
Commit
80d3a4c39f5065ef620d7b3e73935cf491f0c394
by github[DebugInfo][RemoveDIs] Add local-utility plumbing for DPValues (#72276)
This patch re-implements a variety of debug-info maintenence functions
to use DPValues instead of DbgValueInst's: supporting the "new"
non-intrinsic representation of debug-info. As per [0], we need to have
parallel implementations of various utilities for a time, and these are
the most fundamental utilities used throughout the compiler.
I've added --try-experimental-debuginfo-iterators to a variety of RUN
lines: this is a flag that turns on "new debug-info" if it's built into
LLVM, and not otherwise. This should ensure that we have the same
behaviour for the same IR inputs, but using a different internal
representation. For the most part these changes affect SROA/Mem2Reg
promotion of dbg.declares into dbg.value intrinsics (now DPValues),
we're leaving dbg.declares as instructions until later in the day.
There's also some salvaging changes made.
I believe the tests that I've added cover almost all the code being
updated here. The only thing I'm not confident about is SimplifyCFG,
which calls rewriteDebugUsers down a variety of code paths. Those
changes can't immediately get full coverage as an additional patch is
needed that updates handling of Unreachable instructions, will upload
that shortly.
[0]
https://discourse.llvm.org/t/rfc-instruction-api-changes-needed-to-eliminate-debug-intrinsics-from-ir/68939/9
|
| llvm/test/Transforms/SafeStack/X86/debug-loc2.ll (diff) |
| llvm/test/Transforms/Mem2Reg/debug-alloca-phi-2.ll (diff) |
| llvm/test/Transforms/Mem2Reg/debug-alloca-phi.ll (diff) |
| llvm/test/Transforms/SimplifyCFG/tail-merge-noreturn.ll (diff) |
| llvm/test/Transforms/InstCombine/salvage-dbg-declare.ll (diff) |
| llvm/test/Transforms/SROA/dbg-inline.ll (diff) |
| llvm/test/Transforms/SafeStack/X86/debug-loc-dynamic.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstructionCombining.cpp (diff) |
| llvm/test/Transforms/SROA/dbg-single-piece.ll (diff) |
| llvm/lib/Transforms/Utils/Local.cpp (diff) |
| llvm/test/Transforms/InstCombine/debuginfo-dce.ll (diff) |
| llvm/test/Transforms/Mem2Reg/dbg_declare_to_value_conversions.ll (diff) |
| llvm/test/DebugInfo/salvage-cast-debug-info.ll (diff) |
| llvm/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll (diff) |
| llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll (diff) |
| llvm/test/Transforms/Reassociate/undef_intrinsics_when_deleting_instructions.ll (diff) |
| llvm/test/Transforms/SafeStack/X86/debug-loc.ll (diff) |
| llvm/test/Transforms/Util/salvage-debuginfo.ll (diff) |
| llvm/include/llvm/Transforms/Utils/Local.h (diff) |
| llvm/test/Transforms/Mem2Reg/debug-alloca-vla-1.ll (diff) |
| llvm/lib/IR/BasicBlock.cpp (diff) |
| llvm/test/Transforms/Mem2Reg/dbg-inline-scope-for-phi.ll (diff) |
| llvm/test/DebugInfo/salvage-gep.ll (diff) |
| llvm/test/Transforms/Mem2Reg/ConvertDebugInfo.ll (diff) |
Commit
4a020018ce7abdee21e976f7ed5746ef2eb2c0fd
by github[NFC] Simplify the tiling implementation using cloning. (#72178)
The current implementation of tiling using `scf.for` is convoluted to
make sure that the destination passing style of the untiled program is
preserved. The addition of support to tile using `scf.forall` (adapted
from the transform operation in Linalg) in
https://github.com/llvm/llvm-project/pull/67083 used cloning of the
tiled operations to better streamline the implementation. This PR adapts
the other tiling methods to use a similar approach, making the
transformations (and handling destination passing style semantics) more
systematic.
---------
Co-authored-by: Abhishek-Varma <avarma094@gmail.com>
|
| mlir/test/lib/Interfaces/TilingInterface/TestTilingInterface.cpp (diff) |
| mlir/test/Interfaces/TilingInterface/tile-using-interface.mlir (diff) |
| mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp (diff) |
| mlir/test/Dialect/Tensor/tiling.mlir (diff) |
| mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir (diff) |
| mlir/include/mlir/Dialect/SCF/Transforms/TileUsingInterface.h (diff) |
|
| clang/lib/Headers/llvm_libc_wrappers/stdio.h (diff) |
|
| mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td (diff) |
Commit
d8447c78ab16c16eb17abab76e0bc77f58d2d9be
by github[Clang] Correct handling of negative and out-of-bounds indices (#71877)
GCC returns 0 for a negative index on an array in a structure. It also
returns 0 for an array index that goes beyond the extent of the array.
In addition. a pointer to a struct field returns that field's size, not
the size of it plus the rest of the struct, unless it's the first field
in the struct.
struct s {
int count;
char dummy;
int array[] __attribute((counted_by(count)));
};
struct s *p = malloc(...);
p->count = 10;
A __bdos on the elements of p return:
__bdos(p, 0) == 30
__bdos(p->array, 0) == 10
__bdos(&p->array[0], 0) == 10
__bdos(&p->array[-1], 0) == 0
__bdos(&p->array[42], 0) == 0
Also perform some refactoring, putting the "counted_by" calculations in
their own function.
|
| clang/test/CodeGen/attr-counted-by.c (diff) |
| clang/lib/CodeGen/CGBuiltin.cpp (diff) |
|
| compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh (diff) |
Commit
445f6f1373429fb2c86ead77ec2ff64f17948899
by github[BOLT][TEST] Remove LTO flag from a test (#72896)
The LTO flag is not needed for the test to work properly. However, it
may not build on a system where compiler and linker versions don't match
one another. Remove the LTO flag.
|
| bolt/test/lsda.cpp |
| bolt/test/lsda-section-name.cpp |
|
| mlir/test/Dialect/SparseTensor/codegen.mlir (diff) |
| mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp (diff) |
Commit
5cd24759c41864215e67c280234b6c745a4cd369
by github[libc++] Reduce the compilation time required by SIMD tests (#72602)
Testing all the SIMD widths exhaustively is nice in theory, however in
practice it leads to extremely slow tests. Given that
1. our testing resources are finite and actually pretty costly
2. we have thousands of other tests we also need to run
3. the value of executing these SIMD tests for absolutely all supported
SIMD widths is fairly small compared to cherry-picking a few relevant
widths
I think it makes a lot of sense to reduce the exhaustiveness of these
tests. I'm getting a ~4x speedup for the worst offender
(reference_assignment.pass.cpp) after this patch.
I'd also like to make this a reminder to anyone seeing this PR that
tests impact everyone's productivity. Slow unit tests contribute to
making the CI slower as a whole, and that has a direct impact on
everyone's ability to iterate quickly during PRs. Even though we have a
pretty robust CI setup in place, we should remember that it doesn't come
for free and should strive to keep our tests at a good bang for the buck
ratio.
|
| libcxx/test/std/experimental/simd/simd.reference/reference_assignment.pass.cpp (diff) |
| libcxx/test/std/experimental/simd/test_utils.h (diff) |
|
| libcxx/include/__config (diff) |
Commit
47a3ad5be1c60fc0bd40bef5b53907bb1792b6e5
by github[Libomptarget] Handle dynamic stack sizes for AMD COV5 (#72606)
Summary:
One of the changes in the AMD code-object version five was that kernels
that use an unknown amount of private stack memory now no longer default
to 16 KBs. Instead it emits a flag that indicates the runtime must
provide a value. This patch checks if we must provide such a stack, and
uses the existing handling of the stack environment variable to
configure it.
|
| openmp/libomptarget/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h (diff) |
| openmp/libomptarget/plugins-nextgen/common/PluginInterface/PluginInterface.h (diff) |
| openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp (diff) |
Commit
2404477219f87dd9fdd3ed46cc9257699af475a8
by githubLoopVectorize: Add better heuristic for vectorized epilogue skip test (#72589)
This is a follow-up to PR #72450 correcting the branch_weights used
for the test whether the vectorized epilogue loop should be skipped.
|
| llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
| llvm/test/Transforms/LoopVectorize/branch-weights.ll (diff) |
Commit
0ba5f6e6bd971d74c530e50587c69489e625ce8e
by githubFix to attribute plugins reaching an unreachable (#70877)
[0faee97](https://github.com/llvm/llvm-project/commit/0faee97a924adec76d5c7cd680c289ced51e6b5a)
broke attribute plugins. Specifically, it added a call to
`getAttributeSpellingListIndex()` in situations that reached an
unreachable statement. This patch adds a check before calling that to
avoid hitting the unreachable.
`clang/test/Frontend/plugin-attribute.cpp` has been broken since
[0faee97](https://github.com/llvm/llvm-project/commit/0faee97a924adec76d5c7cd680c289ced51e6b5a),
and this patch fixes it.
Bug: [70702](https://github.com/llvm/llvm-project/issues/70702)
|
| clang/lib/Sema/ParsedAttr.cpp (diff) |
|
| llvm/include/llvm/ProfileData/InstrProfReader.h (diff) |
| compiler-rt/test/profile/Linux/binary-id.c (diff) |
| llvm/lib/ProfileData/InstrProfReader.cpp (diff) |
Commit
70f41022546ea8b2b41ad70702124acd4ed488dc
by github[OpenACC] Implement compound construct parsing (#72692)
This patch implements the compound construct parsing, which allows
'parallel loop', 'serial loop', and 'kernel loop' to act as their own
constructs.
|
| clang/test/ParserOpenACC/parse-constructs.c (diff) |
| clang/include/clang/Basic/OpenACCKinds.h (diff) |
| clang/lib/Parse/ParseOpenACC.cpp (diff) |
Commit
f4c6947a18d5c07d5743eb435c2854e61804ad24
by ericMove all libc++ builders to one machine type.
There are ongoing issues with the libc++ bots, some of them seem
related to a new release of the gha action runner controllers.
Until I get this figured out, it's a lot easier to have 99% of the
bots using a single machine shape
|
| .github/workflows/libcxx-build-and-test.yaml (diff) |
Commit
69a5869da4906f61caf59ff021559ca7d974c5f9
by github[lldb][split-dwarf] implement GetSeparateDebugInfo for SymbolFileOnDemand (#71230)
Small change to get `image dump separate-debug-info` working when using
`symbols.load-on-demand`.
Added tests to `TestDumpDwo`, and enabled the test for all platforms. If we fail to build, we skip the test, so this shouldn't cause the test to fail on unsupported platforms.
```
bin/lldb-dotest -p TestDumpDwo
```
It's easy to verify this manually by running
```
lldb --one-line-before-file "settings set symbols.load-on-demand true" <some_target>
(lldb) image dump separate-debug-info
...
```
---------
Co-authored-by: Tom Yang <toyang@fb.com>
|
| lldb/include/lldb/Symbol/SymbolFileOnDemand.h (diff) |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/Makefile (diff) |
| lldb/test/API/commands/target/dump-separate-debug-info/oso/TestDumpOso.py (diff) |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/main.cpp |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/main.c |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/foo.cpp |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/foo.c |
| lldb/test/API/commands/target/dump-separate-debug-info/dwo/TestDumpDwo.py (diff) |
Commit
6352a07ba65301b60ace8e5e67e54f4967e375ae
by github[mlir][sparse] test four row/col major versions of BSR (#72898)
Note, this is a redo of https://github.com/llvm/llvm-project/pull/72712
which was reverted due to time outs in the bot. I have timed the tests
on various settings, and it does not even hit the top 20 of integration
tests. To be safe, I removed the SIMD version of the tests, just keeping
libgen/direcIR paths (which are the most important to test for us).
I will also keep an eye on
https://lab.llvm.org/buildbot/#/builders/264/builds after submitting to
make sure there is no repeat.
|
| mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir |
Commit
f42482def236999b0f7896c09cd714b708861c8b
by github[DebugInfo][RemoveDIs] Don't convert debug-intrinsics to Unreachable (#72380)
It might seem obvious, but it's not a good idea to convert a
debug-intrinsic instruction into an UnreachableInst, as this means
things operate differently with and without the -g option. However this
can happen due to the "mutate the next instruction" API calls we make.
With RemoveDIs eliminating debug intrinsics, this behaviour is at risk
of changing, hence this patch ensures we only ever mutate the next _non_
debuginfo instruction into an Unreachable.
The tests instrumented with the --try... flag all exercise this, I've
added some metadata to a SCCP test to ensure it's exercised.
|
| llvm/lib/Transforms/IPO/SCCP.cpp (diff) |
| llvm/test/Transforms/SimplifyCFG/dbginfo.ll (diff) |
| llvm/lib/Transforms/Utils/Local.cpp (diff) |
| llvm/test/Transforms/SCCP/ipsccp-branch-unresolved-undef.ll (diff) |
| llvm/test/Transforms/SimplifyCFG/branch-fold-dbg.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstructionCombining.cpp (diff) |
| llvm/test/Transforms/InstCombine/assume.ll (diff) |
| llvm/test/Transforms/InstCombine/unreachable-dbg-info-modified.ll (diff) |
| llvm/test/Transforms/SimplifyCFG/PR27615-simplify-cond-br.ll (diff) |
Commit
a1e2c6566305061c115954b048f2957c8d55cb5b
by github[CUDA][HIP] ignore implicit host/device attr for override (#72815)
When deciding whether a previous function declaration is an overload or
override, implicit host/device attrs should not be considered.
This fixes the failure for the following code:
`template <typename T>
class C {
explicit C() {};
};
template <> C<int>::C() {};
`
The issue was introduced by
https://github.com/llvm/llvm-project/pull/72394
sine the template specialization is treated as overload due to implicit
host/device attrs are considered for overload/override differentiation.
|
| clang/lib/Sema/SemaOverload.cpp (diff) |
| clang/test/SemaCUDA/implicit-member-target-inherited.cu (diff) |
| clang/test/SemaCUDA/trivial-ctor-dtor.cu (diff) |
Commit
0e24179797faf5d309fcc5024131c2293accff26
by github[SelectionDAG] Add support to filter SelectionDAG dumps during ISel by function names (#72696)
`-debug-only=isel-dump` is the new debug type for printing SelectionDAG
after each ISel phase. This can be furthered filter by
`-filter-print-funcs=<function names>`.
Note that the existing `-debug-only=isel` will take precedence over the
new behavior and print SelectionDAG dumps of every single function
regardless of `-filter-print-funcs`'s values.
|
| llvm/test/CodeGen/Generic/selectiondag-dump-filter.ll |
| llvm/include/llvm/CodeGen/SelectionDAGISel.h (diff) |
| llvm/docs/CodeGenerator.rst (diff) |
| llvm/docs/ReleaseNotes.rst (diff) |
| llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (diff) |
Commit
48ff35415c06cdbd9115bfe5318449afddcc7ff5
by github[clang] Add support for new loop attribute [[clang::code_align()]] (#70762)
This patch adds support for new loop attribute:
[[clang::code_align(N)]].
This attribute applies to a loop and specifies the byte alignment for a
loop.
The attribute accepts a positive integer constant initialization
expression
indicating the number of bytes for the minimum alignment boundary.
Its value must be a power of 2, between 1 and 4096 (inclusive).
|
| clang/lib/Sema/TreeTransform.h (diff) |
| clang/lib/CodeGen/CGLoopInfo.cpp (diff) |
| clang/lib/Sema/SemaTemplateInstantiate.cpp (diff) |
| clang/lib/CodeGen/CGLoopInfo.h (diff) |
| clang/docs/ReleaseNotes.rst (diff) |
| clang/include/clang/Basic/AttrDocs.td (diff) |
| clang/include/clang/Basic/Attr.td (diff) |
| clang/test/Sema/code_align.c |
| clang/lib/Sema/SemaStmtAttr.cpp (diff) |
| clang/include/clang/Sema/Sema.h (diff) |
| clang/test/CodeGen/code_align.c |
| clang/test/Sema/code_align_ast.c |
| clang/include/clang/Basic/DiagnosticSemaKinds.td (diff) |
Commit
3e6d629ccff6e3561be07f66f8f0dc2774dab279
by gulfemRevert "[clang-format][NFC] Remove a redundant isLiteral() call"
This reverts commit f6033699646b7650123a273c043a93e5eeaac6d8.
This change is labeled as NFC, but introduces a functional change
without a test, and caused a breakage as reported in
https://reviews.llvm.org/rGf6033699646b7650123a273c043a93e5eeaac6d8.
|
| clang/lib/Format/TokenAnnotator.cpp (diff) |
|
| clang/lib/CodeGen/CodeGenModule.cpp (diff) |
|
| llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned-is-known-non-negative.ll |
| llvm/test/Transforms/ConstraintElimination/transfer-unsigned-facts-to-signed-is-known-non-negative.ll |
| llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll (diff) |
Commit
523c0d3e4912d70f2f26f58c03069647165b90f7
by github[MemorySSA] Update test to use NewPM (#72915)
This test is the last holdout that still uses the legacy loop simplify
CFG pass. The issues originally pointed out in the test comments seem to
have been fixed now as there are no MemorySSA verification failures.
|
| llvm/test/Analysis/MemorySSA/update-remove-dead-blocks.ll (diff) |
Commit
c597dc3566db27b3c2ad2a4c1f5ae61693d5465b
by github[nfc][InstrProfTest]Factor out common code for value profile test (#72611)
Three existing test cases {get_icall_data_read_write, get_icall_data_read_write_with_weight,get_icall_data_read_write_big_endian} have common test data and testing
logic. Extract common code into `testICallDataReadWrite`.
- Add helper function `addValueProfData` and `testValueDataArray`. This two helper functions are used by `testICallDataReadWrite`, and possibly other test cases.
|
| llvm/unittests/ProfileData/InstrProfTest.cpp (diff) |
|
| llvm/unittests/ProfileData/InstrProfTest.cpp (diff) |
Commit
abd85cd473afedf112bf00630a22382fee4a7853
by github[libc] Remove the optional arguments for NVPTX constructors (#69536)
Summary:
We call the global constructors by function pointer. For whatever reason
the NVPTX architecture relies very specifically on the arguments to the
function pointer invocation matching what the function is implemented
as. This is problematic as most of these constructors are generated
with no arguments. This patch removes the extended arguments that GNU
and LLVM use for the constructors optionally so that it can support the
common case.
|
| libc/test/integration/startup/gpu/init_fini_array_test.cpp (diff) |
| libc/startup/gpu/nvptx/start.cpp (diff) |
Commit
dfcf9fe1408168699c27bc8e8c877bf78b8fd390
by github[flang][openacc][NFC] Check only HLFIR lowering for atomic tests (#72922)
HLFIR lowering has been set by default now and FIR lowering support will
be removed in the near future. This patch is the first of a series to
update the OpenACC lowering tests to check only the HLFIR lowering and
remove and specific FIR check lines.
|
| flang/test/Lower/OpenACC/acc-atomic-write.f90 (diff) |
| flang/test/Lower/OpenACC/acc-atomic-update-array.f90 (diff) |
| flang/test/Lower/OpenACC/acc-atomic-update-hlfir.f90 (diff) |
| flang/test/Lower/OpenACC/acc-atomic-update.f90 (diff) |
| flang/test/Lower/OpenACC/acc-atomic-capture.f90 (diff) |
| flang/test/Lower/OpenACC/acc-atomic-read.f90 (diff) |
Commit
85ee3fc7ec15f432430ee0c73fe81f3d6382d9df
by githubFix command escape bug in lldb-dap (#72902)
https://github.com/llvm/llvm-project/pull/69238 caused breakage in
VSCode debug console usage -- the user's input is always treated as
commands instead of expressions (the same behavior as if empty command
escape prefix is specified).
The bug is in one overload of `GetString()` which did not respect the
default value of "\`". But more important, I am puzzled to find out why
the regression is not caught by lldb test (testdap_evaluate). Turns out
https://github.com/llvm/llvm-project/pull/69238 specifies
commandEscapePrefix default value in test framework to be "\`" while
VSCode will default not specify any commandEscapePrefix at all. Changing
it to None will fail `testdap_evaluate`. We should align the default
behavior between DAP client and testcase.
This patches fixes the bug in `GetString()` and changed the default
value of commandEscapePrefix in testcases to be None (be consistent with
IDE).
Co-authored-by: jeffreytan81 <jeffreytan@fb.com>
|
| lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py (diff) |
| lldb/tools/lldb-dap/JSONUtils.cpp (diff) |
| lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py (diff) |
|
| llvm/test/Transforms/InstCombine/sub.ll (diff) |
Commit
dbf6f30926891dfab4d59d0ff0e960c2a31ab472
by goldstein.w.n[InstCombine] Add folds for `(X + Y) - (W + Z)`
If `Y` and `Z` are constant then we can simplify to `(X - W) + (Y -
Z)`. If `Y == Z` we can fold to `X - W`.
Note these transform exist outside of InstCombine. The purpose of this
commit is primarily to make it so that folds can generate these
simplifiable patterns without having to worry about creating an inf
loop.
|
| llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp (diff) |
| llvm/test/Transforms/InstCombine/sub.ll (diff) |
Commit
d01857803f3593c26118b7f9fe59db71234a3359
by goldstein.w.n[InstCombine] Make `isFreeToInvert` check recursively.
Some Instructions (select/min/max) are inverted by just inverting the
operands. So the answer of whether they are free to invert is really
just whether the operands are free to invert.
Differential Revision: https://reviews.llvm.org/D159056
|
| llvm/test/Transforms/InstCombine/minmax-intrinsics.ll (diff) |
| llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp (diff) |
| llvm/include/llvm/Transforms/InstCombine/InstCombiner.h (diff) |
|
| llvm/test/Transforms/InstCombine/free-inversion.ll |
|
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