Changes

Summary

  1. [ADT] Remove WrappedPairNodeDataIterator (NFC) (details)
  2. [LICM] Extract debugify test (NFC) (details)
  3. [Tests] Add missing willreturn attributes (NFC) (details)
  4. [Tests] Add additional tests for incorrect willreturn handling (NFC) (details)
  5. [RISCV] Custom lower (i32 (fptoui/fptosi X)). (details)
Commit 4ccfb1076fb7c783ac6fd8d2ae8a6492cdcc42ce by kazu
[ADT] Remove WrappedPairNodeDataIterator (NFC)

The last use was removed on Jul 16, 2020 in commit
f1d4db4f0cdcbfeaee0840bf8a4fb5dc1b9b56fd.
The file was modifiedllvm/include/llvm/ADT/iterator.h
Commit 0339fcc7284d31bb2cb3422a3f300d36d3c2fd05 by nikita.ppv
[LICM] Extract debugify test (NFC)

Only one of the tests in the file wants to check debug info, so
move it into a separate file. This allows update_test_checks to
work.
The file was addedllvm/test/Transforms/LICM/sinking-debugify.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
Commit baa51a0cef57587cfbea4fc437a7968b6daf0290 by nikita.ppv
[Tests] Add missing willreturn attributes (NFC)

To retain the spirit of these tests after an upcoming change
to mayHaveSideEffect(), add willreturn attributes to a number
of functions.
The file was modifiedllvm/test/Transforms/TailCallElim/reorder_load.ll
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/test/Transforms/SCCP/musttail-call.ll
The file was modifiedllvm/test/Transforms/LICM/funclet.ll
The file was modifiedllvm/test/Transforms/SCCP/remove-call-inst.ll
Commit c7e69e46c86c3f3785441de45db4b7bc6d26e321 by nikita.ppv
[Tests] Add additional tests for incorrect willreturn handling (NFC)

Highlight a few of the places that don't handle non-willreturn
calls correctly right now.
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
Commit c63dbd850182797bc4b76124d08e1c320ab2365d by craig.topper
[RISCV] Custom lower (i32 (fptoui/fptosi X)).

I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32)
isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if
the assertzexti32 has an additional user. If we add a one use check
it would just cause a fcvt.lu followed by a sext.w when only need
a fcvt.wu to satisfy both users.

To mitigate this I've added custom isel and new ISD opcodes for
fcvt.wu. This allows us to keep know it started life as a conversion
to i32 without needing to match multiple nodes. ComputeNumSignBits
has been taught that this new nodes produces 33 sign bits. To
prevent regressions when we need to zero extend the result of an
(i32 (fptoui X)), I've added a DAG combine to convert it to an
(i64 (fptoui X)) before type legalization. In most cases this would
happen in InstCombine, but a zero_extend can be created for function
returns or arguments.

To keep everything consistent I've added new nodes for fptosi as well.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D106346
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/rv64d-double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-half-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll