Changes

Summary

  1. Revert "[sanitizer] Try to re-enabler clangd tests after 8edce2ff049" (details)
Commit f3bccdbb1aba56f7aeda7eda39c7ea43a5ade65c by Vitaly Buka
Revert "[sanitizer] Try to re-enabler clangd tests after 8edce2ff049"

Didn't help.

This reverts commit 4609b7129317e47bbfe4f1fb9f6e25ebcbba9b67.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_functions.sh (diff)

Summary

  1. Recommit "[AggressiveInstCombine] Lower Table Based CTTZ (details)
  2. [LoongArch] Add codegen support for fmaxnum_ieee and fminnum_ieee (details)
  3. [LLVM][AArch64] Replace aarch64.sve.ld by aarch64.sve.ldN.sret (details)
  4. [InstCombine] Add test coverage for D134172 / Issue #57635 (details)
  5. [InstCombine] Precommit test for D134142 (details)
  6. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI. (details)
  7. Analysis: Pass AssumptionCache through isKnownNonZero (details)
  8. Analysis: Remove redundant assertion (details)
  9. [lld-macho] Support -dyld_env (details)
  10. [LV] Remove unused widenCallInstruction declaration (NFC). (details)
  11. [libc] Remove unneeded extra include (details)
  12. [libc] Fix TWS issues in .td files (details)
  13. [AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C (details)
Commit f0f8b4686392388e78b22339820f14a23b539937 by djordje.todorovic
Recommit "[AggressiveInstCombine] Lower Table Based CTTZ

The bug reported on the [0] has been fixed.
The issue was we have not checked if the global variables that
represent cttz tables was constant.
There is a new negative test added in negative-lower-table-based-cttz.ll
that represents this.

[0] https://reviews.llvm.org/rGdf868edee561eb973edd85ec9df41c67aa0bff6b
The file was addedllvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-non-argument-value.ll
The file was addedllvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll
The file was addedllvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-dereferencing-pointer.ll
The file was addedllvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-basics.ll
The file was modifiedllvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp (diff)
The file was addedllvm/test/Transforms/AggressiveInstCombine/lower-table-based-cttz-zero-element.ll
The file was addedllvm/test/Transforms/AggressiveInstCombine/negative-lower-table-based-cttz.ll
Commit 7328ff75bab0d559645927ddaeab39bf0f4b8d03 by gonglingqin
[LoongArch] Add codegen support for fmaxnum_ieee and fminnum_ieee

Thanks for @xry111's previous bug fixes.
See https://github.com/loongson/llvm-project/pull/1 for more details.

Differential Revision: https://reviews.llvm.org/D133478
The file was modifiedllvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td (diff)
The file was modifiedllvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td (diff)
The file was addedllvm/test/CodeGen/LoongArch/fp-max-min.ll
Commit d32b8fdbdb4b99a5cc21604db6211fc506eb1f9b by caroline.concatto
[LLVM][AArch64] Replace aarch64.sve.ld by aarch64.sve.ldN.sret

This patch removes the intrinsic aarch64.sve.ldN from tablegen in favour of
using arch64.sve.ldN.sret.

Depends on: D133023

Differential Revision: https://reviews.llvm.org/D133025
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td (diff)
The file was removedllvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-merging-stores.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll (diff)
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was addedllvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
The file was removedllvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+reg-addr-mode.ll
Commit f5a5d96394ebb1902f93bf91ab2a37b81a4cdc62 by llvm-dev
[InstCombine] Add test coverage for D134172 / Issue #57635
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll (diff)
Commit bba25c4c9f13337413e3adde89397413c50a26a2 by markus.boeck02
[InstCombine] Precommit test for D134142
The file was modifiedllvm/test/Transforms/InstCombine/select.ll (diff)
Commit 0015edeefd74ba331c328ddfb0ad32774ce90030 by llvm-dev
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (diff)
Commit 1e1aefbf70007307b0a4a29400c4cd04ec1857ba by Matthew.Arsenault
Analysis: Pass AssumptionCache through isKnownNonZero

Pass this through now that isDereferenceableAndAlignedPointer has
access to this.
The file was modifiedllvm/lib/Analysis/Loads.cpp (diff)
Commit 1a18fe65d321cb47d43682bd515afb140caccd47 by Matthew.Arsenault
Analysis: Remove redundant assertion

This assert guards the same assertion inside getTypeStoreSizeInBits
The file was modifiedllvm/lib/Analysis/Loads.cpp (diff)
Commit 016c2f5e3233e67f48c2a511962101876ef0b94c by vyng
[lld-macho] Support -dyld_env

This arg is undocumented but from looking at the code + experiment, it's used to add additional DYLD_ENVIRONMENT load commands to the output.

Differential Revision: https://reviews.llvm.org/D134058
The file was addedlld/test/MachO/dyld-env.s
The file was modifiedllvm/include/llvm/BinaryFormat/MachO.h (diff)
The file was modifiedlld/MachO/Driver.cpp (diff)
The file was modifiedlld/MachO/Writer.cpp (diff)
The file was modifiedlld/MachO/Options.td (diff)
The file was modifiedlld/MachO/Config.h (diff)
Commit dcbc8a0daafcbfbd3c9c07a4c664a1c485ee3279 by flo
[LV] Remove unused widenCallInstruction declaration (NFC).

The definition and uses have been removed a while ago. Clean up the
unused declaration.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)
Commit 6007a4a619a9902355cfa3467d3e5f9579235fc8 by jeffbailey
[libc] Remove unneeded extra include

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D134255
The file was modifiedlibc/src/time/mktime.h (diff)
Commit faeb237bac7a303ab09135cf6c35505a85c18de7 by jeffbailey
[libc] Fix TWS issues in .td files

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D134256
The file was modifiedlibc/spec/posix.td (diff)
The file was modifiedlibc/spec/stdc.td (diff)
Commit b982ba2a6e0f11340b4e75d1d4eba9ff62a81df7 by Joseph.Nash
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C

    Due to the encoding changes in GFX11, we had a hack in place that
    disables the use of VGPRs above 128. This patch removes the need for
    that hack.

    We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
    operands of VOP1, VOP2, and VOPC instructions. This register class only has the
    low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
    VOP2, and VOPC instructions are correctly limited to use the first 128
    VGPRs, while the other instructions can freely use all 256.

    We introduce new pseduo-instructions used on GFX11 which have the suffix
    t16 (True 16) to use the VGPR_32_Lo128 register class.

Reviewed By: foad, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D133723
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.i128.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (diff)
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
The file was modifiedllvm/lib/Target/AMDGPU/VOPCInstructions.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIModeRegister.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/preserve-hi16.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td (diff)
The file was addedllvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir (diff)
The file was addedllvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir (diff)
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
The file was modifiedllvm/lib/Target/AMDGPU/GCNDPPCombine.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/vopc_dpp.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-fma.mir (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir (diff)
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir (diff)
The file was removedllvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp (diff)
The file was addedllvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
The file was addedllvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
The file was addedllvm/test/CodeGen/AMDGPU/true16-ra-f128-fail.mir
The file was addedllvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (diff)