Changes

[Sanitizers][PGO] missing return statement

[X86][Atom] Add missing UOps override to AtomWriteResPair multiclass

Make it easier to describe microcoded instructions.

[X86][Atom] MUL/DIV instructions require both ports, not either.

Noticed while trying to improve multiplication costs for vectorization via the D103695 helper script. Confirmed with Intel AoM.

[libc++][doc] Update format status.

Marked the entries solely depending on D103357 or D96664 as complete.
Initial work on implementing P2216 has started.

[Sanitizers] netbsd build fix due to wordexp interception.

[mlir] Async: check awaited operand error state after sync await

Previously only await inside the async function (coroutine after lowering to async runtime) would check the error state

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D109229

[X86][SLM] Fix MUL uops, latency and throughput

These were all set to the same best case mul i32 values (which seems to be the only version of MUL that SLM actually performs well with).

Noticed while trying to improve multiplication costs for vectorization via the D103695 helper script. Confirmed with Intel AoM / Agner / InstLatX64.

[X86][SLM] RMW instructions don't require an extra uop

For RMW instructions, the load and store hold the MEC for an extra cycle, but within the same single uop. This is alluded to in the Intel AOM:

"The MEC also owns the MEC RSV, which is responsible for scheduling of all loads and stores. Load and
store instructions go through addresses generation phase in program order to avoid on-the-fly memory
ordering later in the pipeline. Therefore, an unknown address will stall younger memory instructions."

Noticed while trying to get a cheap SLM test box up and running with llvm-exegesis - RMW arithmetic is always 1uop - and matches what Agner / InstLatX64 report as well.

[X86][SLM] WriteVecIMul instructions only take 1uop

The xmm variant have half the throughput (and +1cy latency) of the mmx variants, but are still 1uop.

I still need to do more thorough testing of SLM on test-suite before fixing the obvious bad numbers for WritePMULLD.

But this helps the D103695 helper script get to more accurate numbers for vXi32 multiplies of extended operands (i.e. we can use PMADDWD, PMULLW/PMULHW etc). Matches what Intel AoM / Agner / llvm-exegesis reports.

[NFC] Added tests for PR51565

Revert rG994da657076900f5ad7fe593c3b5e5f89ab3d53d "[X86][SLM] WriteVecIMul instructions only take 1uop"

This changed some codegen tests that I forgot about in my rebase, I'll recommit shortly with a fix.