SuccessChanges

Summary

  1. [DebugInfo] UnwindTable::create() should not add empty rows to CFI unwind table (details)
  2. [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose (details)
  3. Replace a remaining CRLF with LF. NFC. (details)
  4. [X86] Support AMX fast register allocation (details)
  5. Revert "[X86] Support AMX fast register allocation" (details)
  6. Fix build after 34a8a437b (details)
  7. [X86] Support AMX fast register allocation (details)
  8. [mlir] Debug print pattern before and after matchAndRewrite call (details)
  9. [VectorCombine] Simplify to scalar store if only one element updated (details)
  10. [libc++] Use Xcode's CMake if it's present (details)
  11. [X86] Improve costmodel for scalar byte swaps (details)
  12. Revert "[LICM] Hoist loads with invariant.group metadata" (details)
  13. [MLIR][NFC] Remove unused MLIRContext declaration (details)
  14. [MLIR] Add memref dialect dependency for affine fusion pass (details)
  15. [libc++] Move handling of the target triple to the DSL (details)
  16. [X86] combineHorizOpWithShuffle - generalize HOP(SHUFFLE(X),SHUFFLE(Y)) -> SHUFFLE(HOP(X,Y)) fold. (details)
  17. [GlobalISel] Ensure MachineIRBuilder::getDebugLoc() returns a const reference. NFCI. (details)
  18. [VPlan] Add test for sink scalars and merging using VPlan. (details)
  19. [libc++] NFC: Refactor Lit annotations (details)
  20. [lld/mac] Copy some of the commit message of d5a70db193 into a comment (details)
  21. [MCA][RegisterFile] Refactor the move elimination logic to address PR50258. (details)
  22. [lld-macho] Explicitly undefine literal exported symbols (details)
  23. [llvm-mca][View] Update the Register File statistics. (details)
  24. [Hexagon] Propagate metadata in Hexagon Vector Combine (details)
  25. [test] Fix tools/gold/X86/new-pm.ll after D101797 (details)
  26. [NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes (details)
  27. [NFCI][X86] Mark Znver3 scheduling model as complete (details)
  28. [NFC][LoopIdiom] Add some tests for 'lshr until zero' ('count active bits') "on steroids" idiom (details)
  29. [lld-macho][NFC] Purge stale test-output trees prior to split-file (details)
  30. [libc++][doc] Update the Format library status. (details)
  31. [SROA] Regenerate test checks (NFC) (details)
  32. [SelectionDAG] Regenerate test checks (NFC) (details)
  33. [X86] AMD Zen 3: XCHG is a zero-cycle instruction (details)
  34. [NFC][X86] Znver3: drop obsolete fixme (details)
  35. [SCEV] Add additional loop guard and/or tests (NFC) (details)
  36. [SCEV] Handle and/or in applyLoopGuards() (details)
  37. [ARM] Fix postinc of vst1xN (details)
  38. [NFC][X86][MCA] AMD Zen3: add GPR zero-idiom dependency breaking tests (details)
  39. [X86] AMD Zen 3: same-register XOR/SUB are GPR dependency breaking zero-idioms (details)
  40. [NFC][X86][MCA] AMD Zen 3: add tests for SBB dependency breaking (details)
  41. [X86] AMD Zen 3: same-reg SBB is a dependency-breaking instruction (details)
  42. [NFC][X86][MCA] AMD Zen 3: add tests for CMP dependency breaking (details)
  43. [X86] AMD Zen 3: same-reg CMP is a zero-cycle dependency-breaking instruction (details)
  44. [Demangle][Rust] Print special namespaces (details)
  45. [lld-macho] Don't reference entry symbol for non-executables (details)
  46. [lld/mac] Fix alignment on subsections (details)
  47. [lld-macho] Add llvm-otool as a test dependency (details)
  48. Support NativeCodeCall binding in rewrite pattern. (details)
  49. [RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter. (details)
  50. [NFC][Coroutines] Fix two tests by removing hardcoded SSA value. (details)
  51. [SimplifyCFG] Ignore ephemeral values when counting insts for threading (details)
  52. [ORC] Generalize materialization dispatch to task dispatch. (details)
  53. [ORC] Use the new dispatchTask API to run query callbacks. (details)
  54. [AArch64][SVE] Remove index_vector node. (details)
  55. [mlir] Fix compile error. (details)
  56. [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion (details)
  57. [amdgpu-arch] Guard hsa.h with __has_include (details)
  58. [AMDGPU][OpenMP] Disable tests when amdgpu-arch fails (details)
  59. [libc] Allow target architecture customization (details)
  60. [AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S (details)
  61. [mlir] OpenMP-to-LLVM: properly set outer alloca insertion point (details)
  62. AMDGPU/GlobalISel: Add regbankselect test for vgpr(dest) sgpr(address) load (details)
  63. AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad (details)
  64. [libc] Simplifies multi implementations and benchmarks (details)
  65. [MLIR][Shape] Concretize broadcast result type if possible (details)
  66. [compiler-rt] Handle None value when polling addr2line pipe (details)
  67. Fixed bug in buffer deallocation pass using unranked memref types. (details)
  68. [OpenMP][MLIR]Add support for guided, auto and runtime scheduling (details)
  69. [clang][PreProcessor] Cutoff parsing after hitting completion point (details)
  70. HexagonVectorCombine.cpp - don't negate a bool value. NFCI. (details)
  71. [AArch64][SVE] Fix isel failure for FP-extending loads (details)
  72. [GlobalISel] Fix wrong invocation of `getParamStackAlign` (NFC) (details)
  73. [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics (details)
  74. [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics (details)
  75. clang: Fix tests after 7f78e409d028 if clang is not called clang-13 (details)
  76. [NFC][llvm-dwarfdump] Code clean up for inlined var loc stats (details)
  77. [clangd] Fix data type of WorkDoneProgressReport::percentage (details)
  78. [Constant] Allow ConstantAggregateZero a scalable element count (details)
  79. X86LoadValueInjectionLoadHardening.cpp - use const-reference in for-range loops to avoid unnecessary copies. NFCI. (details)
  80. X86FlagsCopyLowering.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
  81. [TableGen] Remove redundant `Error:` in msg (NFC) (details)
  82. [OPENMP]Fix PR48851: the locals are not globalized in SPMD mode. (details)
  83. [AArch64][SVE] Improve SVE codegen for fixed length BITCAST (details)
  84. [libc++][AIX] Define _LIBCPP_ELAST (details)
  85. [SLP]Do not count perfect diamond matches for gathers several times. (details)
  86. [PowerPC] Enable safe for 32bit vins* P10 instructions (details)
  87. [libomptarget] Add support for target allocators to dynamic cuda RTL (details)
  88. Revert "[PassManager] add helper function to hold set of vector passes" (details)
  89. [clang][AArch32] Correctly align HA arguments when passed on the stack (details)
  90. [NFC] Synchronize reserved identifier code between macro and variables / symbols (details)
  91. [X86] Fix position-independent TType encoding (details)
  92. [libc++][NFC] Remove _VSTD:: when not needed. (details)
  93. [llvm-objdump][MachO] Print a newline before lazy bind/bind/weak/exports trie (details)
  94. [X86][SSE] Merge equal X32/X64 check prefixes. NFCI. (details)
  95. [X86][SSE] Add tests for missing shuffle(pack(x,y),pack(z,w)) -> permute(pack()) folds. (details)
  96. [llvm-symbolizer] Update Command Guide (details)
  97. [llvm-nm] Help option output should be consistent with the command guide (details)
  98. [ORC] Update SpeculativeJIT example for dispatchTask changes in 5344c88dcb2. (details)
  99. [clang] Support -fpic -fno-semantic-interposition for AArch64 (details)
  100. [Demangle][Rust] Parse basic types (details)
  101. [RISCV] Correct VL for fixed length masked scatter. (details)
  102. [X86][SSE] Add examples of failures to remove a permute(pack(pack(),pack())) shuffle by reordering the packed operands. (details)
  103. [mlir][CAPI] Add CAPI bindings for the sparse_tensor dialect. (details)
  104. [cmake] Enable -Wmisleading-indentation (details)
  105. [lld][WebAssembly] Disallow exporting of TLS symbols (details)
  106. [mlir][Python] Upstream the PybindAdaptors.h helpers and use it to implement sparse_tensor.encoding. (details)
  107. [Dependence Analysis] Enable delinearization of fixed sized arrays (details)
  108. [lld-macho] Improve an external weak def test (details)
  109. [X86][SSE] canonicalizeShuffleMaskWithHorizOp - add TODO for better 256/512-bit shuffle+hop folding support. NFC. (details)
  110. [X86][AVX] Add example of failure to remove a 256-bit permute(hadd(hadd(),hadd())) shuffle by reordering the packed operands. (details)
  111. [NFC][X86][MCA] AMD Zen 3: add tests for sub-32-bit CMP dep breaking (details)
  112. [X86] AMD Zen 3: sub-32-bit CMP also break dependencies (details)
  113. [mlir][Python] Re-export cext sparse_tensor module to the public namespace. (details)
Commit 223852d76fccc85cc5a844feec94781e8c5320ff by VenkataRamanaiah.Nalamothu
[DebugInfo] UnwindTable::create() should not add empty rows to CFI unwind table

UnwindTable::parseRows() may return successfully if the CFIProgram has either
no CFI instructions or only DW_CFA_nop instructions and the UnwindRow return
argument will be empty. But currently, the callers are not checking for this case
which is leading to incorrect dumps in the unwind tables in such cases i.e.

  CFA=unspecified

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D101892
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugFrameTest.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
Commit 34a8a437bf20e0a340c19ed1fdb9cca584d43da1 by aeubanks
[NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose

Printing pass manager invocations is fairly verbose and not super
useful.

This allows us to remove DebugLogging from pass managers and PassBuilder
since all logging (aside from analysis managers) goes through
instrumentation now.

This has the downside of never being able to print the top level pass
manager via instrumentation, but that seems like a minor downside.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D101797
The file was modifiedlld/test/wasm/lto/new-pass-manager.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/lib/Target/BPF/BPFTargetMachine.h
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetMachine.h
The file was modifiedllvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
The file was modifiedllvm/test/Other/new-pm-pgo-preinline.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/test/Transforms/SROA/dead-inst.ll
The file was modifiedlld/test/COFF/lto-new-pass-manager.ll
The file was modifiedlld/test/ELF/lto/new-pass-manager.ll
The file was modifiedllvm/include/llvm/CodeGen/MachinePassManager.h
The file was modifiedllvm/lib/LTO/LTOBackend.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Analysis/CGSCCPassManager.cpp
The file was modifiedllvm/unittests/Analysis/CGSCCPassManagerTest.cpp
The file was modifiedpolly/lib/Support/RegisterPasses.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-loop-invalidation.ll
The file was modifiedllvm/test/Transforms/SCCP/preserve-analysis.ll
The file was modifiedllvm/lib/Target/BPF/BPFTargetMachine.cpp
The file was modifiedllvm/test/Transforms/Inline/clear-analyses.ll
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopPassManager.cpp
The file was modifiedclang/test/CodeGenCoroutines/coro-newpm-pipeline.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/lto-newpm-pipeline.c
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
The file was modifiedllvm/unittests/IR/PassManagerTest.cpp
The file was modifiedllvm/unittests/IR/PassBuilderCallbacksTest.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetMachine.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
The file was modifiedllvm/test/Other/pass-pipeline-parsing.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopPassManager.h
The file was modifiedllvm/lib/CodeGen/MachinePassManager.cpp
The file was modifiedllvm/test/Other/new-pm-O0-defaults.ll
The file was modifiedllvm/test/Other/new-pass-manager.ll
The file was modifiedllvm/test/Transforms/LoopRotate/pr35210.ll
The file was modifiedllvm/unittests/Transforms/Scalar/LoopPassManagerTest.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/tools/gold/X86/new-pm.ll
The file was modifiedllvm/lib/Transforms/IPO/Inliner.cpp
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
The file was modifiedllvm/test/Transforms/SCCP/ipsccp-preserve-analysis.ll
The file was modifiedllvm/test/Other/new-pass-manager-cgscc-fct-proxy.ll
The file was modifiedllvm/include/llvm/IR/PassManager.h
The file was modifiedllvm/include/llvm/Transforms/IPO/Inliner.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
The file was modifiedllvm/test/Other/loop-pm-invalidation.ll
Commit 631da3b15203b672e237031f964a53f3bb194f9b by michael.hliao
Replace a remaining CRLF with LF. NFC.
The file was modifiedllvm/include/llvm/IR/Metadata.def
Commit 77e2e5e07d01fe0b83c39d0c527c0d3d2e659146 by xiang1.zhang
[X86] Support AMX fast register allocation
The file was modifiedclang/include/clang/Basic/BuiltinsX86_64.def
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-precfg.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
The file was modifiedllvm/lib/Target/X86/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was addedllvm/lib/Target/X86/X86PreAMXConfig.cpp
The file was modifiedllvm/lib/Target/X86/X86.h
The file was modifiedllvm/lib/Target/X86/X86LowerAMXType.cpp
The file was addedllvm/lib/Target/X86/X86FastTileConfig.cpp
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-lower.ll
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was addedllvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir
The file was modifiedllvm/include/llvm/CodeGen/TargetPassConfig.h
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
The file was modifiedllvm/tools/opt/opt.cpp
Commit bebafe01a74619f19bd7830ff02a8647f1af54d6 by xiang1.zhang
Revert "[X86] Support AMX fast register allocation"

This reverts commit 77e2e5e07d01fe0b83c39d0c527c0d3d2e659146.
The file was modifiedllvm/lib/Target/X86/CMakeLists.txt
The file was modifiedllvm/lib/Target/X86/X86LowerAMXType.cpp
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/lib/Target/X86/X86.h
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was removedllvm/lib/Target/X86/X86PreAMXConfig.cpp
The file was removedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-precfg.ll
The file was modifiedclang/include/clang/Basic/BuiltinsX86_64.def
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetPassConfig.h
The file was removedllvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was modifiedllvm/tools/opt/opt.cpp
The file was removedllvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was removedllvm/lib/Target/X86/X86FastTileConfig.cpp
The file was removedllvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
The file was removedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-lower.ll
Commit 72bd0116e3a1a70fb52fc47c056349b290ce2204 by aeubanks
Fix build after 34a8a437b
The file was modifiedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
Commit d4bdeca5765ac2e81e217a5fa873d1ffbf0e95b0 by xiang1.zhang
[X86] Support AMX fast register allocation

Differential Revision: https://reviews.llvm.org/D100026
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-precfg.ll
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
The file was addedllvm/lib/Target/X86/X86FastTileConfig.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetPassConfig.h
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
The file was modifiedllvm/lib/Target/X86/CMakeLists.txt
The file was modifiedllvm/lib/Target/X86/X86.h
The file was modifiedllvm/lib/Target/X86/X86LowerAMXType.cpp
The file was addedllvm/lib/Target/X86/X86PreAMXConfig.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
The file was modifiedclang/include/clang/Basic/BuiltinsX86_64.def
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
The file was modifiedllvm/lib/Target/X86/X86InstrAMX.td
The file was addedllvm/test/CodeGen/X86/AMX/amx-fast-tile-config.mir
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was addedllvm/test/CodeGen/X86/AMX/amx-configO2toO0-lower.ll
The file was modifiedllvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/tools/opt/opt.cpp
Commit e2a77644817fed9eb5a91d9e6cf4bc0c175f70e1 by ivan.butygin
[mlir] Debug print pattern before and after matchAndRewrite call

Motivation: we have passes with lot of rewrites and when one one them segfaults or asserts, it is very hard to find waht exactly pattern failed without debug info.

Differential Revision: https://reviews.llvm.org/D101443
The file was modifiedmlir/lib/Rewrite/PatternApplicator.cpp
The file was modifiedmlir/include/mlir/IR/PatternMatch.h
Commit 2db4979c0fe05eac82ca770516057b7b9c4433e3 by qiucofan
[VectorCombine] Simplify to scalar store if only one element updated

This patch simplifies load-insertelt-store pattern into
getelementptr-store.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D98240
The file was addedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was removedllvm/test/Transforms/InstCombine/load-insert-store.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/opt-pipeline.ll
The file was modifiedllvm/test/Other/opt-LTO-pipeline.ll
Commit c42007e266a38374f705564225dc35c5aacba7f4 by Louis Dionne
[libc++] Use Xcode's CMake if it's present

This resolves issues when the CMake in use on the host is too old to
configure libc++ properly, but Xcode has a sufficiently recent version.
It is technically possible for the reverse issue to happen, where the
Xcode version would be too old and the user-installed version would be
better, however in the context of our build bots, we use AppleClang on
Apple platforms, and the CMake shipped with Xcode should work with the
AppleClang shipped alongside that Xcode.

Differential Revision: https://reviews.llvm.org/D102083
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit b1c38207e9ca6aba883a8000239163520ee6ed83 by lebedev.ri
[X86] Improve costmodel for scalar byte swaps

Currently we model i16 bswap as very high cost (`10`),
which doesn't seem right, with all other being at `1`.

Regardless of `MOVBE`, i16 reg-reg bswap is lowered into
(an extending move plus) rot-by-8:
https://godbolt.org/z/8jrq7fMTj
I think it should at worst have throughput of `1`:

Since i32/i64 already have cost of `1`,
`MOVBE` doesn't improve their costs any further.

BUT, `MOVBE` must have at least a single memory operand,
with other being a register. Which means, if we have
a bswap of load, iff load has a single use,
we'll fold bswap into load.

Likewise, if we have store of a bswap, iff bswap
has a single use, we'll fold bswap into store.

So i think we should treat such a bswap as free,
unless of course we know that for the particular CPU
they are performing badly.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D101924
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/test/Analysis/CostModel/X86/load-bswap.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/bswap-store.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/bswap.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit 1acd9a1a29ac30044ecefb6613485d5d168f66ca by lebedev.ri
Revert "[LICM] Hoist loads with invariant.group metadata"

This appears to miscompile google benchmark's GetCacheSizesFromKVFS()
when compiling with -fstrict-vtable-pointers.
Runnable reproducer: https://godbolt.org/z/f9ovKqTzb
The "f.fail()" crashes with BUS error, it is compiled into testb,
and the adress it is testing is non-sensical.

This reverts commit 4c89bcadf6cae8320a1925eb9cbeb8c8c1f5f58b.
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
The file was removedllvm/test/Transforms/LICM/invariant.group.ll
Commit 73df48158bf5460b5e3497ccec0df4c62c570fad by uday
[MLIR][NFC] Remove unused MLIRContext declaration

Remove unused MLIRContext declaration. NFC.

Differential Revision: https://reviews.llvm.org/D102103
The file was modifiedmlir/lib/Support/MlirOptMain.cpp
Commit 9610a2d753dbba385e8c2c005e2497e3add99472 by uday
[MLIR] Add memref dialect dependency for affine fusion pass

For `AffineLoopFusion` pass, add `memref` dialect as a dependent
dialect. Since the fusion pass can create `memref::AllocOp`s, the
dialect must be registered in its dependent dialects.

The missing dependency was not discovered until now because the above
said op creation happes only when the input already has
`memref::AllocOp`s in it, and all dialects in the input are
automatically added to the context.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D102104
The file was modifiedmlir/include/mlir/Transforms/Passes.td
Commit 74d096e5587969e0d1458ea2175515f6f02e7df3 by Louis Dionne
[libc++] Move handling of the target triple to the DSL

This fixes a long standing issue where the triple is not always set
consistently in all configurations. This change also moves the
back-deployment Lit features to using the proper target triple
instead of using something ad-hoc.

This will be necessary for using from scratch Lit configuration files
in both normal testing and back-deployment testing.

Differential Revision: https://reviews.llvm.org/D102012
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The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/streambuf.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/int.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_init_list_args.pass.cpp
The file was modifiedlibcxxabi/test/catch_multi_level_pointer.pass.cpp
The file was modifiedlibcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char32_t_char8_t_always_noconv.pass.cpp
The file was modifiedlibcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/system_category.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_time_point.pass.cpp
The file was modifiedlibcxxabi/test/catch_pointer_nullptr.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long.pass.cpp
The file was modifiedlibcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/seekg_off.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf_chart.pass.cpp
The file was modifiedlibcxx/test/std/numerics/rand/rand.device/eval.pass.cpp
The file was modifiedlibcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char16_t_char8_t.pass.cpp
The file was modifiedlibcxx/test/std/utilities/optional/optional.specalg/make_optional.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp
The file was modifiedlibcxx/test/std/utilities/charconv/charconv.to.chars/integral.pass.cpp
The file was modifiedlibcxx/test/libcxx/selftest/dsl/dsl.sh.py
The file was modifiedlibcxx/test/std/utilities/variant/variant.visit/robust_against_adl.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_pointer_size_chart.pass.cpp
The file was modifiedlibcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/locale.codecvt.members/char16_t_char8_t_out.pass.cpp
The file was modifiedlibcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/getline_pointer_size.pass.cpp
The file was modifiedlibcxxabi/test/exception_object_alignment.pass.cpp
The file was modifiedlibcxx/test/std/localization/locale.categories/category.ctype/locale.codecvt/types_char32_t_char8_t.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_adopt_lock.pass.cpp
The file was modifiedlibcxxabi/test/lit.site.cfg.in
The file was modifiedlibcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp
The file was modifiedlibcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp
Commit 4524d8b7552c1d2dcb941c708620fb1f1b998cd1 by llvm-dev
[X86] combineHorizOpWithShuffle - generalize HOP(SHUFFLE(X),SHUFFLE(Y)) -> SHUFFLE(HOP(X,Y)) fold.

For 128-bit types, generalize the fold to recognise duplicate operands in either shuffle.
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit ab5ee342b92b4661cfec3cdd647c9a5c18e346dd by llvm-dev
[GlobalISel] Ensure MachineIRBuilder::getDebugLoc() returns a const reference. NFCI.

Avoids a lot of unnecessary tracking increments/decrements of the underlying TrackingMDNodeRef.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
Commit 2bf34c0a93ff212c97cdc86dff9b615faacfe386 by flo
[VPlan] Add test for sink scalars and merging using VPlan.

Add a couple of tests with scalars that can be sunk to their predicated
users.

This pre-commits tests for D100258.
The file was addedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
The file was addedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Commit 20544746402a94fece90dd2500cdaf62320310cc by Louis Dionne
[libc++] NFC: Refactor Lit annotations

Annotations for c++03 mode are useless, since we only run these tests
in C++11 and C++14.
The file was modifiedlibcxx/test/std/thread/futures/futures.task/futures.task.members/ctor_func_alloc.pass.cpp
The file was removedlibcxx/test/std/thread/futures/futures.task/futures.task.nonmembers/uses_allocator.pass.cpp
The file was addedlibcxx/test/std/thread/futures/futures.task/futures.task.nonmembers/uses_allocator.compile.pass.cpp
Commit 7b6dd265ce8320fee8741ec86edae5d40d7b7b86 by thakis
[lld/mac] Copy some of the commit message of d5a70db193 into a comment
The file was modifiedlld/MachO/UnwindInfoSection.cpp
Commit 9ceea66602d9c11690004020a6e7a2b0f5291bd5 by andrea.dibiagio
[MCA][RegisterFile] Refactor the move elimination logic to address PR50258.

This patch lifts the restriction on the number of read/write registers for a
move elimination candidate.  With this patch, move elimination candidates with
exactly two reads and two writes are treated like register swap operations for
the purpose of move elimination.

This patch currently doesn't affect any upstream model. However, it should help
unblock the progress on PR50258.
The file was modifiedllvm/lib/MCA/HardwareUnits/RegisterFile.cpp
The file was modifiedllvm/lib/MCA/Stages/DispatchStage.cpp
The file was modifiedllvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
Commit 5be8502271ac5644a7873fa801ecf537f8087d7f by gkm
[lld-macho] Explicitly undefine literal exported symbols

Symbols explicitly exported via command-line options `--exported_symbol SYM` and `--exported_symbols_list FILE` must be defined. Before this fix, lazy symbols defined in archives would be left to languish. We now force them to be included in the linked output.

Differential Revision: https://reviews.llvm.org/D102100
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/test/MachO/export-options.s
Commit de1843e51a76c5628dc93c0507a4fb8e7be52482 by andrea.dibiagio
[llvm-mca][View] Update the Register File statistics.

Correctly track the number of move eliminated in the
Register File statistics.
The file was modifiedllvm/tools/llvm-mca/Views/RegisterFileStatistics.cpp
Commit 561026936bd244f31a1b8dbe953680b20994ec2f by kparzysz
[Hexagon] Propagate metadata in Hexagon Vector Combine
The file was addedllvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Commit 492173d42b32cb91d5d0d72d5ed84fcab80d059a by i
[test] Fix tools/gold/X86/new-pm.ll after D101797
The file was modifiedllvm/test/tools/gold/X86/new-pm.ll
Commit d5494931f2acd6a5b3ca349ed54813226b0c9040 by lebedev.ri
[NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
Commit f8589292084b41fc70da93fb1e23bb576bd1f8f3 by lebedev.ri
[NFCI][X86] Mark Znver3 scheduling model as complete

To the best of my knowledge, all instructions are modelled,
and have reasonable values to them; flipping the switch
doesn't cause any diff for MCA tests, so either we're good,
or we have test coverage gaps.

I'm not really sure why no other X86 sched model is marked as complete.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 4aec8f4ce0f564aa68c23b9e29c2e3a945eec947 by lebedev.ri
[NFC][LoopIdiom] Add some tests for 'lshr until zero' ('count active bits') "on steroids" idiom
The file was addedllvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll
The file was addedllvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero-debuginfo.ll
The file was addedllvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero-cost.ll
Commit 4b8962940322fe732126ec583013ecb5b6a1112e by gkm
[lld-macho][NFC] Purge stale test-output trees prior to split-file

Enforce standard practice

Differential Revision: https://reviews.llvm.org/D102112
The file was modifiedlld/test/MachO/indirect-symtab.s
The file was modifiedlld/test/MachO/nonweak-definition-override.s
The file was modifiedlld/test/MachO/weak-binding.s
The file was modifiedlld/test/MachO/dylib-stub.yaml
The file was modifiedlld/test/MachO/invalid/undefined-symbol.s
The file was modifiedlld/test/MachO/tlv-dylib.s
The file was modifiedlld/test/MachO/why-load.s
The file was modifiedlld/test/MachO/invalid/abs-duplicate.s
The file was modifiedlld/test/MachO/u.s
The file was modifiedlld/test/MachO/adhoc-codesign.s
The file was modifiedlld/test/MachO/invalid/range-check.s
The file was modifiedlld/test/MachO/private-extern.s
The file was modifiedlld/test/MachO/invalid/bad-got-to-dylib-tlv-reference.s
The file was modifiedlld/test/MachO/thin-archive.s
The file was modifiedlld/test/MachO/flat-namespace.s
The file was modifiedlld/test/MachO/weak-import.s
The file was modifiedlld/test/MachO/t.s
The file was modifiedlld/test/MachO/U-dynamic-lookup.s
The file was modifiedlld/test/MachO/dependency-info.s
The file was modifiedlld/test/MachO/common-symbol-coalescing.s
The file was modifiedlld/test/MachO/entry-symbol.s
The file was modifiedlld/test/MachO/lc-linker-option.ll
The file was modifiedlld/test/MachO/weak-header-flags.s
Commit 6ae15756a5a67b3791e91e2258d17b4dfa0ce87f by koraq
[libc++][doc] Update the Format library status.

- Move LWG-3218 to the chrono section.
- Mark the several parts 'In progress'.
The file was modifiedlibcxx/docs/FormatIssuePaperStatus.csv
The file was modifiedlibcxx/docs/FormatProposalStatus.csv
Commit 7549399d0e0a961054f9d47fecbe8807b22ac25f by nikita.ppv
[SROA] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/SROA/basictest.ll
The file was modifiedllvm/test/Transforms/SROA/pointer-offset-size.ll
The file was modifiedllvm/test/Transforms/SROA/slice-width.ll
The file was modifiedllvm/test/Transforms/SROA/scalable-vectors.ll
Commit ad5f3f525828e1e499e94a5065bada5b5df936cb by thatlemon
[SelectionDAG] Regenerate test checks (NFC)
The file was modifiedllvm/test/CodeGen/X86/arg-copy-elide.ll
Commit a21df76db6c41dc87d027e9eb34695d7763f809e by lebedev.ri
[X86] AMD Zen 3: XCHG is a zero-cycle instruction

As measured by exegesis and confirmed by reference docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
Commit 675daef58b5e7e9fddbb5878bb88399b1c634949 by lebedev.ri
[NFC][X86] Znver3: drop obsolete fixme
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 2a08d7409bf920b0b81708cf2bce0c1179262006 by nikita.ppv
[SCEV] Add additional loop guard and/or tests (NFC)

Add tests for and/and, and/or, or/or, or/and combinations.
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Commit d26ca78c18ed21713d7d0a44fb75f1989575ab9d by nikita.ppv
[SCEV] Handle and/or in applyLoopGuards()

applyLoopGuards() already combines conditions from multiple nested
guards. However, it cannot use multiple conditions on the same guard,
combined using and/or. Add support for this by recursing into either
`and` or `or`, depending on the direction of the branch.

Differential Revision: https://reviews.llvm.org/D101692
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 76786037c68163c48d7d829bb654de6c8298bbb0 by david.green
[ARM] Fix postinc of vst1xN

These nodes are not handled correctly by CombineBaseUpdate. For the
moment, similar to 5f1cad4d296a20025f0b mark them as unsupported.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/arm-vst1.ll
Commit ab794852ed41d75039aeb122e4268fa32ef1a68f by lebedev.ri
[NFC][X86][MCA] AMD Zen3: add GPR zero-idiom dependency breaking tests
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-gpr.s
Commit eed8552787d8e2e7c4fd257a8b5ddd78682a55fa by lebedev.ri
[X86] AMD Zen 3: same-register XOR/SUB are GPR dependency breaking zero-idioms

As measured by exegesis and confirmed in reference docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-gpr.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 8d0e2d2b0f0f555549255ee812f7ff5297b79420 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for SBB dependency breaking
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
Commit 11b0568dce5a72d45780d07398650693537bfa67 by lebedev.ri
[X86] AMD Zen 3: same-reg SBB is a dependency-breaking instruction

As confirmed by exegesis measurements, and ref docs.
It does actually execute.

While there, bump latency for MULX32rr, that seems to match measurements.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/resources-bmi2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 9a31efa2f51b8150935a9b90eac6ab4eaa613841 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for CMP dependency breaking
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
Commit be23d5e81439e701c67c767b06fe4c7afcde6af9 by lebedev.ri
[X86] AMD Zen 3: same-reg CMP is a zero-cycle dependency-breaking instruction

As measured by exegesis, and confirmed by ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 78e949159d105b7947dbae973080ea343e8f9eda by dblaikie
[Demangle][Rust] Print special namespaces

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101821
The file was modifiedllvm/include/llvm/Demangle/RustDemangle.h
The file was modifiedllvm/lib/Demangle/RustDemangle.cpp
The file was modifiedllvm/test/Demangle/rust.test
Commit 0f8854f7f5d3e98f32eef7cfd09d5b8915a7d301 by jezng
[lld-macho] Don't reference entry symbol for non-executables

This would cause us to pull in symbols (and code) that should
be unused.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D102137
The file was modifiedlld/MachO/Config.h
The file was modifiedlld/test/MachO/bundle-loader.s
The file was modifiedlld/test/MachO/entry-symbol.s
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/MachO/Driver.cpp
Commit 7f673fcaa9a2cb4600f244792f8521ff19aa806c by thakis
[lld/mac] Fix alignment on subsections

On a section with alignment of 16, subsections aligned to 16-byte
boundaries should keep their 16-byte alignment.

Fixes PR50274. (The same bug could have happened with -order_file
previously.)

Differential Revision: https://reviews.llvm.org/D102139
The file was modifiedlld/test/MachO/weak-definition-gc.s
The file was modifiedlld/MachO/InputFiles.cpp
Commit 75f74f267350c71058a05904f9ee9cc72a061b6f by jezng
[lld-macho] Add llvm-otool as a test dependency

This unbreaks my local build, which is configured to build only parts of
LLVM.
The file was modifiedlld/test/CMakeLists.txt
Commit 34b5482b334f2a3960ef079667adb5b3df20aa7d by chiahungduan
Support NativeCodeCall binding in rewrite pattern.

We are able to bind the result from native function while rewriting
pattern. In matching pattern, if we want to get some values back, we can
do that by passing parameter as return value placeholder. Besides, add
the semantic of '$_self' in NativeCodeCall while matching, it'll be the
operation that defines certain operand.

Differential Revision: https://reviews.llvm.org/D100746
The file was modifiedmlir/test/mlir-tblgen/rewriter-errors.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was modifiedmlir/docs/DeclarativeRewrites.md
The file was modifiedmlir/lib/TableGen/Pattern.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/test/lib/Dialect/Test/TestPatterns.cpp
The file was modifiedmlir/test/mlir-tblgen/pattern.mlir
Commit 446ed6394bd36631508056ffac08bd740d401a00 by zakk.chen
[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.

RISCVAsmPrinter already has MCSubtargetInfo.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D101889
The file was modifiedllvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Commit 9ffd4924e8e1a056760256c4cd5ffde38ccdf010 by Yuanfang Chen
[NFC][Coroutines] Fix two tests by removing hardcoded SSA value.
The file was modifiedclang/test/CodeGenCoroutines/coro-params.cpp
The file was modifiedclang/test/CodeGenCoroutines/coro-dest-slot.cpp
Commit 220f6e5271f2e6b39bf4e083c03cd3f91bb43685 by tejohnson
[SimplifyCFG] Ignore ephemeral values when counting insts for threading

Ignore ephemeral values (only feeding llvm.assume intrinsics) when
computing the instruction count to decide if a block is small enough for
threading. This is similar to the handling of these values in the
InlineCost computation. These instructions will eventually be removed
and shouldn't count against code size (similar to the existing ignoring
of phis).

Without this change, when enabling -fwhole-program-vtables, which causes
type test / assume sequences to be inserted by clang, we can get
different threading decisions. In particular, when building with
instrumentation FDO it can affect the optimizations decisions before FDO
matching, leading to some mismatches.

Differential Revision: https://reviews.llvm.org/D101494
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/unprofitable-pr.ll
Commit 5344c88dcb2845f6a12cd0992deab1448b4d1419 by Lang Hames
[ORC] Generalize materialization dispatch to task dispatch.

Generalizing this API allows work to be distributed more evenly. In particular,
query callbacks can now be dispatched (rather than running immediately on the
thread that satisfied the query). This avoids the pathalogical case where an
operation on one thread satisfies many queries simultaneously, causing large
amounts of work to be run on that thread while other threads potentially sit
idle.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Commit 7f9a89f9a2cc55dbfc315aa11416fe3609918199 by Lang Hames
[ORC] Use the new dispatchTask API to run query callbacks.

Dispatching query callbacks, rather than running them on the current thread,
will allow them to be distributed across multiple threads.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Commit b3aeb138924577f0c7f1a665723edb6b4858fb6f by JunMa
[AArch64][SVE] Remove index_vector node.

Since index_vector is lowered into step_vector in D100816, we can just remove
index_vector, use step_vector for codegen directly.

Differential Revision: https://reviews.llvm.org/D101593
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 9ba661f91276dd8cc728f9b2e82905b78c0119b4 by akuegel
[mlir] Fix compile error.

Inside a templated function, other class members need to be called with
this->.
Otherwise we get: explicit qualification required to use member
'setDebugName' from dependent base class.
The file was modifiedmlir/include/mlir/IR/PatternMatch.h
Commit 6db0cedd238590023398bb20dad94773b56c4c74 by fraser
[LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion

This patch extends VectorLegalizer::ExpandSELECT to permit expansion
also for scalable vector types. The only real change is conditionally
checking for BUILD_VECTOR or SPLAT_VECTOR legality depending on the
vector type.

We can use this to fix "cannot select" errors for scalable vector
selects on the RISCV target. Note that in future patches RISCV will
possibly custom-lower vector SELECTs to VSELECTs for branchless codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D102063
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/select-fp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/select-int.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
Commit c711aa0f6f9d9400fbe619c7f0d6d4aa723b3a64 by Pushpinder.Singh
[amdgpu-arch] Guard hsa.h with __has_include

This patch is suppose to fix the issue of hsa.h not found.
Issue was reported in D99949

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D102067
The file was modifiedclang/tools/amdgpu-arch/AMDGPUArch.cpp
Commit 9586937ef513b5b9b134322c6c81dcdd03ca784a by Pushpinder.Singh
[AMDGPU][OpenMP] Disable tests when amdgpu-arch fails

This patch prevents runtime tests running on systems without amdgpu.

Reviewed By: protze.joachim, tianshilei1992

Differential Revision: https://reviews.llvm.org/D102054
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
Commit ed4f4edea20caa13a468ab279a0df20b9ba667fb by gchatelet
[libc] Allow target architecture customization

This patch provides a way to specify the default target cpu optimizations to use when compiling llvm-libc.
This ensures we don't rely on current compiler's default and allows compiling and cross compiling for a particular target.

Differential Revision: https://reviews.llvm.org/D101991
The file was modifiedlibc/cmake/modules/LLVMLibCTestRules.cmake
The file was modifiedlibc/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCLibraryRules.cmake
The file was modifiedlibc/cmake/modules/LLVMLibCObjectRules.cmake
Commit 7f78e409d0280c62209e1a7dc8c6d1409acc9184 by Pushpinder.Singh
[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S

Previously clang would print a binary blob into the bundled file
for amdgcn. With this patch, it will instead print textual IR as
expected.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D102065
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit 72d013dd73f4b59eb421d7dbbfd0b2bccbb6fc7b by zinenko
[mlir] OpenMP-to-LLVM: properly set outer alloca insertion point

Previously, the OpenMP to LLVM IR conversion was setting the alloca insertion
point to the same position as the main compuation when converting OpenMP
`parallel` operations. This is problematic if, for example, the `parallel`
operation is placed inside a loop and would keep allocating on stack on each
iteration leading to stack overflow.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D101307
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
The file was modifiedmlir/test/Target/LLVMIR/openmp-llvm.mlir
Commit d13ce17bb4008b2907e6e85882a9295dce9f6b0a by petar.avramovic
AMDGPU/GlobalISel: Add regbankselect test for vgpr(dest) sgpr(address) load

Pre-commit for D101992.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
Commit f6985a197ef9065a64d0bb819bfd90d1862da45b by petar.avramovic
AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad

Large loads on target that does not useFlatForGlobal have to be split
in regbankselect. This did not happen in case when destination had vgpr
bank and address had sgpr bank.
Instead of checking if address bank is sgpr check bank of the destination.

Differential Revision: https://reviews.llvm.org/D101992
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 541f107871bc9c020925a6e5342542a47c902d12 by gchatelet
[libc] Simplifies multi implementations and benchmarks

This is a follow up on D101524 which:
- simplifies cpu features detection and usage,
- flattens target dependent optimizations so it's obvious which implementations are generated,
- provides an implementation targeting the host (march/mtune=native) for the mem* functions,
- makes sure all implementations are unittested (provided the host can run them),
- makes sure all implementations are benchmarkable (provided the host can run them).

Differential Revision: https://reviews.llvm.org/D101895
The file was modifiedlibc/src/string/CMakeLists.txt
The file was modifiedlibc/test/src/string/CMakeLists.txt
The file was removedlibc/src/string/x86_64/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
The file was removedlibc/src/string/aarch64/CMakeLists.txt
Commit a81e45b8bcb8eb274ad73357e10e2cdf8a314a8c by frgossen
[MLIR][Shape] Concretize broadcast result type if possible

As a canonicalization, infer the resulting shape rank if possible.

Differential Revision: https://reviews.llvm.org/D102068
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/Shape.h
Commit 831cf15ca6892e2044447f8dc516d76b8a827f1e by david.spickett
[compiler-rt] Handle None value when polling addr2line pipe

According to:
https://docs.python.org/3/library/subprocess.html#subprocess.Popen.poll

poll can return None if the process hasn't terminated.

I'm not quite sure how addr2line could end up closing the pipe without
terminating but we did see this happen on one of our bots:
```
<...>scripts/asan_symbolize.py",
line 211, in symbolize
    logging.debug("addr2line exited early (broken pipe), returncode=%d"
% self.pipe.poll())
TypeError: %d format: a number is required, not NoneType
```

Handle None by printing a message that we couldn't get the return
code.

Reviewed By: delcypher

Differential Revision: https://reviews.llvm.org/D101891
The file was modifiedcompiler-rt/lib/asan/scripts/asan_symbolize.py
Commit fc253e69f9b988e8b2d4c940946146696b2acf5a by julian.gross
Fixed bug in buffer deallocation pass using unranked memref types.

In the buffer deallocation pass, unranked memref types are not properly supported.
After investigating this issue, it turns out that the Clone and Dealloc operation
does not support unranked memref types in the current implementation.
This patch adds the missing feature and enables the transformation of any memref
type.

This patch solves this bug: https://bugs.llvm.org/show_bug.cgi?id=48385

Differential Revision: https://reviews.llvm.org/D101760
The file was modifiedmlir/test/Transforms/buffer-deallocation.mlir
The file was modifiedmlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
The file was modifiedmlir/test/Conversion/StandardToSPIRV/alloc.mlir
The file was modifiedmlir/test/Dialect/MemRef/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
Commit 7280f4b279a6ecaea813b7dc63ee68eb95880115 by andrzej.warzynski
[OpenMP][MLIR]Add support for guided, auto and runtime scheduling

When using parallel loop construct, the OpenMP specification allows for
guided, auto and runtime as scheduling variants (as well as static and
dynamic which are already supported).

This adds the translation from MLIR to LLVM-IR for these scheduling
variants.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D101435
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
The file was modifiedmlir/test/Target/LLVMIR/openmp-llvm.mlir
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
Commit 761f3d16753ecea625173729dd8c53df022cd4ab by kadircet
[clang][PreProcessor] Cutoff parsing after hitting completion point

This fixes a crash caused by Lexers being invalidated at code
completion points in
https://github.com/llvm/llvm-project/blob/main/clang/lib/Lex/PPLexerChange.cpp#L520.

Differential Revision: https://reviews.llvm.org/D102069
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was addedclang/test/CodeCompletion/crash-if-directive.cpp
Commit ea64200b6197d8db97a11db15a5906fc1eb5ef4a by llvm-dev
HexagonVectorCombine.cpp - don't negate a bool value. NFCI.

Silences MSVC warning.
The file was modifiedllvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Commit 407a33889de69c54bf4c0945f94a8417cf08e250 by sander.desmalen
[AArch64][SVE] Fix isel failure for FP-extending loads

DAGCombiner tries to combine a (fpext (load)) to (fround (extload))
but SVE has no FP-extending loads. By marking these as expand,
the combine no longer happens.

This also fixes a similar issue for fptrunc, where the source type
is not a legal type.

Reviewed By: bsmith, kmclaughlin

Differential Revision: https://reviews.llvm.org/D102053
The file was modifiedllvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fpext-load.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit f3139b20a0bf56b3a5e20542363a799619b98ec9 by momchil.velikov
[GlobalISel] Fix wrong invocation of `getParamStackAlign` (NFC)

The function template `CallLowering::setArgFlags` is invoked both
for arguments and return values. In the latter case, it calls
`getParamStackAlign` with argument index `~0u`. Nothing wrong
happens now, as the argument is safely incremented back to 0
inside `getParamStackAlign` (the type is `unsigned`), but in
principle it's fragile and may become incorrect.

Differential Revision: https://reviews.llvm.org/D102004
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit f8f953c2a6b3ee6bd50f1bc1bc81880c0d40eb6c by bradley.smith
[AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics

When using predicated arithmetic intrinsics, if the predicate used is all
lanes active, use an unpredicated form of the instruction, additionally
this allows for better use of immediate forms.

This also includes a new complex isel pattern which allows matching an
all active predicate when the types are different but the predicate is a
superset of the type being used. For example, to allow a b8 ptrue for a
b32 predicate operand.

This only includes instructions where the unpredicated/predicated forms
are mismatched between variants, meaning that the removal of the
predicate is done during instruction selection in order to prevent
spurious re-introductions of ptrue instructions.

Co-authored-by: Paul Walker <paul.walker@arm.com>

Differential Revision: https://reviews.llvm.org/D101062
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 65c89cd1a62ad1f2e9b879edc10a806f13c21892 by bradley.smith
[AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics

When using predicated intrinsics, if the predicate used is all lanes active,
use an unpredicated form of the instruction, additionally this allows for
better use of immediate forms.

This only includes instructions where the unpredicated/predicated forms
matched in such a way that instruction selection would not introduce extra
ptrue instructions. This allows us to convert the intrinsics directly to
architecture independent ISD nodes.

Depends on D101062

Differential Revision: https://reviews.llvm.org/D101828
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 08de6e3adaf6e991f5a40357f4634e5b70ec3fde by thakis
clang: Fix tests after 7f78e409d028 if clang is not called clang-13

We might release a new version at some point after all.
In fact, use the same pattern the other CHECK lines in this test
use, for consistency.
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit 9ad9f0c731702dddd401b5ec0c4bca8394dd43e8 by djtodoro
[NFC][llvm-dwarfdump] Code clean up for inlined var loc stats

This is preparation for the https://reviews.llvm.org/D101025.
The D101025 will start calculating var locstats for concrete fns
that refere to an abstract origin as well.
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
Commit f088af37e6b570dd070ae4e6fc14e22d21cda3be by kadircet
[clangd] Fix data type of WorkDoneProgressReport::percentage

According to the specification, this should be an unsigned integer.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D101616
The file was modifiedclang-tools-extra/clangd/Protocol.h
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
Commit 3212a08a8c811441ca68009118758998750ce905 by fraser
[Constant] Allow ConstantAggregateZero a scalable element count

A ConstantAggregateZero may be created from a scalable vector type.
However, it still assumed fixed number of elements when queried for
them. This patch changes ConstantAggregateZero to correctly report its
element count.

This change fixes a couple of issues. Firstly, it fixes a crash in
Constant::getUniqueValue when called on a scalable-vector
zeroinitializer constant.

Secondly, it fixes a latent bug in GlobalISel's IRTranslator in which
translating a scalable-vector zeroinitializer would hit the assertion in
ConstantAggregateZero::getNumElements when casting to a FixedVectorType,
rather than reporting an error more gracefully. This is currently
hypothetical as the IRTranslator has deeper issues preventing the use of
scalable vector types.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D102082
The file was modifiedllvm/include/llvm/IR/Constants.h
The file was addedllvm/test/Transforms/InstCombine/scalable-select.ll
The file was modifiedllvm/lib/IR/Constants.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Commit 9243a584d3863d8baae59f6ab0d3c46c7d7b857c by llvm-dev
X86LoadValueInjectionLoadHardening.cpp - use const-reference in for-range loops to avoid unnecessary copies. NFCI.
The file was modifiedllvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
Commit 605f90475fc663433250f45f39dcb24cdb8c9e9b by llvm-dev
X86FlagsCopyLowering.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI.
The file was modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Commit fefd03a89129ab13d2b3aa04ad2d6d52f8ba794d by qixingxue
[TableGen] Remove redundant `Error:` in msg (NFC)

Since calling `PrintFatalError` will automatically add `error: `
prefix in the message printed, there is no need having an extra
`ERROR:` prefix in the argument passed.

Differential Revision: https://reviews.llvm.org/D102151
Reviewed By: Paul-C-Anagnostopoulos
The file was modifiedllvm/utils/TableGen/ExegesisEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
Commit 230953d5771f6f3ce6bf86b8bb6ae4d5eb75a218 by a.bataev
[OPENMP]Fix PR48851: the locals are not globalized in SPMD mode.

Follow the more general patch for now, do not try to SPMDize the kernel
if the variable is used and local.

Differential Revision: https://reviews.llvm.org/D101911
The file was modifiedclang/test/OpenMP/nvptx_SPMD_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit 635164b95a8e5d8c0c40804c7ffa3981a82b917a by bradley.smith
[AArch64][SVE] Improve SVE codegen for fixed length BITCAST

Expanding a fixed length operation involves wrapping the operation in an
insert/extract subvector pair, as such, when this is done to bitcast we
end up with an extract_subvector of a bitcast. DAGCombine tries to
convert this into a bitcast of an extract_subvector which restores the
initial fixed length bitcast, causing an infinite loop of legalization.

As part of this patch, we must make sure the above DAGCombine does not
trigger after legalization if the created bitcast would not be legal.

Differential Revision: https://reviews.llvm.org/D101990
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 4677d795b2042e783952fdcdaefaf2ca6bfb72a6 by jasonliu
[libc++][AIX] Define _LIBCPP_ELAST

The aim is to define _LIBCPP_ELAST for AIX since strerror/strerror_r
can't handle out-of-range errno values.

Differential Revision: https://reviews.llvm.org/D100986
The file was modifiedlibcxx/src/include/config_elast.h
Commit 30463bc3f1839e8a238be4c137e2356f3cca2771 by a.bataev
[SLP]Do not count perfect diamond matches for gathers several times.

Need to remove the old code for avoiding double counting of the gather
nodes with perfect diamond matches within the tree after we started
detecting perfect/shuffled matching in the previous patch D100495. We
may skip the cost for such nodes completely.

Differential Revision: https://reviews.llvm.org/D102023
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 0c41f77857fccf2a20d48ca96ce61d3c4d1634e6 by zarko
[PowerPC] Enable safe for 32bit vins* P10 instructions

Correctly emit `vins`instructions that are safe in 32bit mode.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101383
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 6da348569cd20632d8ee2213fbab59850e133eb0 by jonathanchesterfield
[libomptarget] Add support for target allocators to dynamic cuda RTL

[libomptarget] Add support for target allocators to dynamic cuda RTL

Follow on to D102000 which introduced new calls into libcuda. This patch adds
the corresponding entry points to dynamic_cuda, fixing the build for systems
that do not have the cuda toolkit installed.

Function types and enum from https://docs.nvidia.com/cuda/cuda-driver-api/group__CUDA__MEM.html

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D102169
The file was modifiedopenmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.cpp
The file was modifiedopenmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h
Commit 822be4bec894134fa63ed4d2d289f353f3cfcc19 by spatel
Revert "[PassManager] add helper function to hold set of vector passes"

This reverts commit fefcb1f878c2dad435af604955661ca02a5302de.
It was supposed to be NFC, but as noted in the post-commit
comments in D102002, that was not true: SimplifyCFG uses
different parameters and there's a difference in an
extension point / callback.
The file was modifiedllvm/include/llvm/Transforms/IPO/PassManagerBuilder.h
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 5c7b43aa8298a389b906d72c792941a0ce57782e by momchil.velikov
[clang][AArch32] Correctly align HA arguments when passed on the stack

Analogously to https://reviews.llvm.org/D98794 this patch uses the
`alignstack` attribute to fix incorrect passing of homogeneous
aggregate (HA) arguments on AArch32. The EABI/AAPCS was recently
updated to clarify how VFP co-processor candidates are aligned:
https://github.com/ARM-software/abi-aa/commit/4488e34998514dc7af5507236f279f6881eede62

Differential Revision: https://reviews.llvm.org/D100853
The file was addedllvm/test/CodeGen/ARM/ha-alignstack-call.ll
The file was addedllvm/test/CodeGen/ARM/ha-alignstack.ll
The file was modifiedllvm/lib/Target/ARM/ARMCallingConv.cpp
The file was addedclang/test/CodeGen/arm-ha-alignstack.c
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
Commit 91a919e8994a2c47b3feaf906f83122776ae2cae by sguelton
[NFC] Synchronize reserved identifier code between macro and variables / symbols

Differential Revision: https://reviews.llvm.org/D102164
The file was modifiedclang/lib/Lex/PPDirectives.cpp
Commit b0ef2070bc7da2b458fb15b9413d9e90abc71759 by harald
[X86] Fix position-independent TType encoding

The logic for x86_64 position-independent TType encodings was backwards,
using 8 bytes where 4 were wanted and 4 where 8 were wanted. For regular
x86_64, this was mostly harmless, exception tables are allowed to use
8-byte encodings even when it is not needed. For the large code model,
and for X32, however, the generated exception tables were wrong. For the
large code model, we cannot assume that the address will fit in 4 bytes.
For X32, we cannot use 64-bit relocations.

Fixes PR50148.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D102132
The file was modifiedllvm/test/CodeGen/X86/gcc_except_table_bb_sections.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Commit cfef7c918b8297ffb1d882d6b31fe68f876607db by koraq
[libc++][NFC] Remove _VSTD:: when not needed.

Reviewed By: #libc, Quuxplusone

Differential Revision: https://reviews.llvm.org/D102133
The file was modifiedlibcxx/include/iomanip
The file was modifiedlibcxx/include/set
The file was modifiedlibcxx/include/concepts
The file was modifiedlibcxx/include/compare
The file was modifiedlibcxx/include/format
The file was modifiedlibcxx/include/functional
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/__memory/shared_ptr.h
Commit 7a0231ae59e7221fa10ff99a69f634107ac5a517 by i
[llvm-objdump][MachO] Print a newline before lazy bind/bind/weak/exports trie

This adds a separator between two pieces of information.

Reviewed By: #lld-macho, alexshap

Differential Revision: https://reviews.llvm.org/D102114
The file was modifiedlld/test/MachO/tlv.s
The file was modifiedlld/test/MachO/local-got.s
The file was modifiedlld/test/MachO/x86-64-stubs.s
The file was modifiedllvm/test/tools/llvm-objdump/MachO/rebase.test
The file was modifiedllvm/test/tools/llvm-objdump/MachO/lazy-bind.test
The file was modifiedllvm/test/tools/llvm-objdump/MachO/exports-trie.test
The file was modifiedllvm/test/tools/llvm-objdump/MachO/bind.test
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
Commit b483c0afb39e6d9f02e5fcc3b3cee0c99b4f977a by llvm-dev
[X86][SSE] Merge equal X32/X64 check prefixes. NFCI.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
Commit 1d802e16650785f6c37a5805d8787abdd611507e by llvm-dev
[X86][SSE] Add tests for missing shuffle(pack(x,y),pack(z,w)) -> permute(pack()) folds.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
Commit 2aa5f9b45a493eac5cb2951875af485b7e1b105c by gbreynoo
[llvm-symbolizer] Update Command Guide

The option --use-symbol-table is now a noop and does not appear in the
help text, however it still appears in the command guide. This change
removes it from the command guide and updates the description of
--output-style .

Differential Revision: https://reviews.llvm.org/D102078
The file was modifiedllvm/docs/CommandGuide/llvm-symbolizer.rst
Commit c74176ee31fad6ccaa1d8771be2cc2b7e9fa988a by gbreynoo
[llvm-nm] Help option output should be consistent with the command guide

The nm command guide shows the short options used as aliases but these
are not found in the help text unless --show-hidden is used, other tools
show aliases with --help. This change fixes the help output to be
consistent with the command guide.

Differential Revision: https://reviews.llvm.org/D102072
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
Commit 08d18af26105fb77665199365c5f3124e0278826 by Lang Hames
[ORC] Update SpeculativeJIT example for dispatchTask changes in 5344c88dcb2.
The file was modifiedllvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
Commit 68a20c7f36d1d51cc46c0bd17384c16bc7818fa2 by i
[clang] Support -fpic -fno-semantic-interposition for AArch64

-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```

-fpic (var and fun are dso_preemptable)
```
test:                                   // @test
        adrp    x8, :got:var
        ldr     x8, [x8, :got_lo12:var]
        ldr     w0, [x8]
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
        b       fun
```

vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:                                   // @test
.Ltest$local:
        adrp    x8, .Lvar$local
        ldr     w0, [x8, :lo12:.Lvar$local]
// The assembler either resolves .Lfun$local at assembly time, or produces a
// relocation referencing a non-preemptible section symbol (which can avoid PLT).
        b       .Lfun$local
```

Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.

Depends on D101872

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D101873
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/fsemantic-interposition.c
Commit 2961f86317f8560c948af8f38581e1ea5a9cfebf by dblaikie
[Demangle][Rust] Parse basic types

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102142
The file was modifiedllvm/lib/Demangle/RustDemangle.cpp
The file was modifiedllvm/include/llvm/Demangle/RustDemangle.h
The file was modifiedllvm/test/Demangle/rust.test
Commit 80b9510806cf11c57f2dd87191d3989fc45defa8 by craig.topper
[RISCV] Correct VL for fixed length masked scatter.

We were incorrectly calling getVectorNumElements on a scalable
vector type. This shouldn't be allowed. This gives a warning on
EVT, but not MVT.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
Commit 22f834210adb79ef266968c55f1e562c0047d18f by llvm-dev
[X86][SSE] Add examples of failures to remove a permute(pack(pack(),pack())) shuffle by reordering the packed operands.
The file was addedllvm/test/CodeGen/X86/horizontal-shuffle-4.ll
Commit bcfa7baec8bbf45b98bcde60305efa23df7399e6 by stellaraccident
[mlir][CAPI] Add CAPI bindings for the sparse_tensor dialect.

* Adds dialect registration, hand coded 'encoding' attribute and test.
* An MLIR CAPI tablegen backend for attributes does not exist, and this is a relatively complicated case. I opted to hand code it in a canonical way for now, which will provide a reasonable blueprint for building out the tablegen version in the future.
* Also added a (local) CMake function for declaring new CAPI tests, since it was getting repetitive/buggy.

Differential Revision: https://reviews.llvm.org/D102141
The file was addedmlir/test/CAPI/sparse_tensor.c
The file was modifiedmlir/test/CMakeLists.txt
The file was addedmlir/include/mlir-c/Dialect/SparseTensor.h
The file was modifiedmlir/lib/CAPI/Dialect/CMakeLists.txt
The file was addedmlir/lib/CAPI/Dialect/SparseTensor.cpp
The file was modifiedmlir/test/CAPI/CMakeLists.txt
Commit f44c6f20f5e9976357b4851c4432d96b4e4d3521 by davelee.com
[cmake] Enable -Wmisleading-indentation

Enable `-Wmisleading-indentation` to balance with the LLVM style of optional parentheses.

Differential Revision: https://reviews.llvm.org/D102092
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit bda8b8488442215e0557a53016a8d9c0a36b90c5 by sbc
[lld][WebAssembly] Disallow exporting of TLS symbols

Cross module TLS is currently not supported by our ABI.  This
change makes explicitly exporting a TLS symbol into an error
and prevents implicit exporting (via --export-all).

See https://github.com/emscripten-core/emscripten/issues/14120

Differential Revision: https://reviews.llvm.org/D102044
The file was addedlld/test/wasm/tls-export.s
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Symbols.h
The file was modifiedlld/wasm/OutputSegment.h
The file was modifiedlld/wasm/InputChunks.h
The file was modifiedlld/wasm/Relocations.cpp
The file was modifiedlld/wasm/Symbols.cpp
Commit f13893f66a228400bf9bdf14be425e3dc6da0034 by stellaraccident
[mlir][Python] Upstream the PybindAdaptors.h helpers and use it to implement sparse_tensor.encoding.

* The PybindAdaptors.h file has been evolving across different sub-projects (npcomp, circt) and has been successfully used for out of tree python API interop/extensions and defining custom types.
* Since sparse_tensor.encoding is the first in-tree custom attribute we are supporting, it seemed like the right time to upstream this header and use it to define the attribute in a way that we can support for both in-tree and out-of-tree use (prior, I had not wanted to upstream dead code which was not used in-tree).
* Adapted the circt version of `mlir_type_subclass`, also providing an `mlir_attribute_subclass`. As we get a bit of mileage on this, I would like to transition the builtin types/attributes to this mechanism and delete the old in-tree only `PyConcreteType` and `PyConcreteAttribute` template helpers (which cannot work reliably out of tree as they depend on internals).
* Added support for defaulting the MlirContext if none is passed so that we can support the same idioms as in-tree versions.

There is quite a bit going on here and I can split it up if needed, but would prefer to keep the first use and the header together so sending out in one patch.

Differential Revision: https://reviews.llvm.org/D102144
The file was removedmlir/lib/Bindings/Python/DialectLinalg.h
The file was addedmlir/lib/Bindings/Python/Dialects.h
The file was addedmlir/include/mlir/Bindings/Python/PybindAdaptors.h
The file was modifiedmlir/lib/Bindings/Python/DialectLinalg.cpp
The file was addedmlir/test/python/dialects/sparse_tensor/dialect.py
The file was modifiedmlir/lib/Bindings/Python/MainModule.cpp
The file was addedmlir/lib/Bindings/Python/DialectSparseTensor.cpp
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
Commit 7086025d6567562d31fadbaccf08b4fd72ec2100 by andrew.kaylor
[Dependence Analysis] Enable delinearization of fixed sized arrays

Patch by Artem Radzikhovskyy!

Allow delinearization of fixed sized arrays if we can prove that the GEP indices do not overflow the array dimensions. The checks applied are similar to the ones that are used for delinearization of parametric size arrays. Make sure that the GEP indices are non-negative and that they are smaller than the range of that dimension.

Changes Summary:

- Updated the LIT tests with more exact values, as we are able to delinearize and apply more exact tests
- profitability.ll - now able to delinearize in all cases, no need to use -da-disable-delinearization-checks flag and run the test twice
- loop-interchange-optimization-remarks.ll - in one of the cases we are able to delinearize without using -da-disable-delinearization-checks
- SimpleSIVNoValidityCheckFixedSize.ll - removed unnecessary "-da-disable-delinearization-checks" flag. Now can get the exact answer without it.
- SimpleSIVNoValidityCheckFixedSize.ll and PreliminaryNoValidityCheckFixedSize.ll - made negative tests more explicit, in order to demonstrate the need for "-da-disable-delinearization-checks" flag

Differential Revision: https://reviews.llvm.org/D101486
The file was modifiedllvm/lib/Analysis/DependenceAnalysis.cpp
The file was modifiedllvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/Coupled.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/Invariant.ll
The file was modifiedllvm/test/Transforms/LoopInterchange/profitability.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/PreliminaryNoValidityCheckFixedSize.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/Separability.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
The file was modifiedllvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheckFixedSize.ll
Commit 1f44fee521c84f5917d323d15301ab27c358178e by i
[lld-macho] Improve an external weak def test

The rebase table entry is untested.

Reviewed By: #lld-macho, int3

Differential Revision: https://reviews.llvm.org/D102150
The file was modifiedlld/test/MachO/weak-binding.s
Commit e32374ed5cb27494c67817f12d1e1cec05486f40 by llvm-dev
[X86][SSE] canonicalizeShuffleMaskWithHorizOp - add TODO for better 256/512-bit shuffle+hop folding support. NFC.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a9196db905aaa35599ecd70e9f33d276bff355bb by llvm-dev
[X86][AVX] Add example of failure to remove a 256-bit permute(hadd(hadd(),hadd())) shuffle by reordering the packed operands.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-4.ll
Commit ecff974b66a5b365c7834fe4cd8309b36859437c by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests for sub-32-bit CMP dep breaking
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
Commit 08cf2776acff6f2dc9998ef15e0bea7a8aeca0c3 by lebedev.ri
[X86] AMD Zen 3: sub-32-bit CMP also break dependencies

They measure as having the same effect as 32-bit CMP.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/dependency-breaking-gpr.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit f38633d1bbf5842f37ad722a2f0edfdfd80733a2 by stellaraccident
[mlir][Python] Re-export cext sparse_tensor module to the public namespace.

* This was left out of the previous commit accidentally.

Differential Revision: https://reviews.llvm.org/D102183
The file was addedmlir/python/mlir/dialects/sparse_tensor.py
The file was modifiedmlir/test/python/dialects/sparse_tensor/dialect.py
The file was modifiedmlir/python/mlir/_cext_loader.py