SuccessChanges

Summary

  1. [AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv (details)
  2. [TargetLowering] move "o" and "X" constraint handling to base class (details)
  3. [AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP (details)
  4. [lld] Delete unused includes. NFC (details)
  5. [test] Make global in split-gep-and-gvn.ll not constant (details)
  6. [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte. (details)
  7. Update a test for auto-update format change (details)
  8. [RISCV] Fix mistake in comment. NFC (details)
  9. [libc++][NFC] Move incrementable_traits and indirectly_readable_traits into separate headers. (details)
  10. [LICM] Make capture check more precise (details)
  11. [gn build] Port e0adf7e06a9e (details)
  12. [flang] Define missing & needed IEEE_ARITHMETIC symbols (details)
  13. [CUDA][HIP] Allow non-ODR use of host var in device (details)
  14. [AArch64] Peephole rule to remove redundant cmp after cset. (details)
  15. [AMDGPU] Remove error check for indirect calls and add missing queue-ptr (details)
  16. [compiler-rt][asan] use full vm range on apple silicon macs (details)
  17. [lldb] Print the fixed address if symbolication fails in DumpDataExtractor (details)
  18. [lldb] Update breakpoint_function_callback.test for different error message (details)
  19. [PowerPC] Disable relative lookup table converter pass for AIX (details)
  20. [lldb] Stop unsetting LLDB_DEBUGSERVER_PATH from TestLaunchProcessPosixSpawn (details)
  21. [mlir][python] ExecutionEngine can dump to object file (details)
  22. [libcxx] Base MSVC autolinking on _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS (details)
  23. [WebAssembly] Use v128.const instead of splats for constants (details)
  24. [libcxx] [test] Ifdef out tests that rely on perms::none on directories for triggering errors (details)
  25. [AST] Update introspection API to use const-ref for copyable types (details)
  26. [InstCombine] Add tests for multiuse shr eq zero (NFC) (details)
  27. [InstCombine] Fold multiuse shr eq zero (details)
  28. [rs4gc] Fix a latent bug around attribute stripping for intrinsics (details)
  29. [AST] Fix comparison to of SourceRanges in container (details)
  30. [funcattrs] Consistently check call site attributes (details)
  31. [ARM] Use ProcResGroup in Cortex-M7 scheduling model (details)
  32. [CodeGen] Use ProcResGroup information in SchedBoundary (details)
  33. [SLP]Add detection of shuffled/perfect matching of tree entries. (details)
Commit 91bbb914e01715b4b16d49c399b05310aa916cfe by Jessica Paquette
[AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv

It turns out we actually import a bunch of selection code for intrinsics. The
imported code checks that the register banks on the G_INTRINSIC instruction
are correct. If so, it goes ahead and selects it.

This adds code to AArch64RegisterBankInfo to allow us to correctly determine
register banks on intrinsics which have known register bank constraints.

For now, this only handles @llvm.aarch64.neon.uaddlv. This is necessary for
porting AArch64TargetLowering::LowerCTPOP.

Also add a utility for getting the intrinsic ID from a G_INTRINSIC instruction.
This seems a little nicer than having to know about how intrinsic instructions
are structured.

Differential Revision: https://reviews.llvm.org/D100398
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-uaddlv.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
Commit c440b97d89994feb965a9026bc121d154f7b4584 by ndesaulniers
[TargetLowering] move "o" and "X" constraint handling to base class

These constraints are machine agnostic; there's no reason to handle
these per-arch. If arches don't support these constraints, then they
will fail elsewhere during instruction selection. We don't need virtual
calls to look these up; TargetLowering::getInlineAsmMemConstraint should
only be overridden by architectures with additional unique memory
constraints.

Reviewed By: echristo, MaskRay

Differential Revision: https://reviews.llvm.org/D100416
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
Commit 65f257a2152ce855f4e25faed9b43ac21933c14a by Jessica Paquette
[AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP

This is a partial port of AArch64TargetLowering::LowerCTPOP.

This custom lowering tries to uses NEON instructions to give a more efficient
CTPOP lowering when possible.

In the non-NEON/noimplicitfloat case, this should use the generic lowering
(see: https://godbolt.org/z/GcaPvWe4x). I think that's worth implementing after
implementing the widening code for s16/s8 though.

Differential Revision: https://reviews.llvm.org/D100399
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop-no-implicit-float.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
Commit 03769d9308fee79aa97149561bdbb6e3263789bd by i
[lld] Delete unused includes. NFC
The file was modifiedlld/tools/lld/lld.cpp
Commit 5561b48b7072ac79113b9b0a363995db45e75a2a by aeubanks
[test] Make global in split-gep-and-gvn.ll not constant

An upcoming change will cause loads from a constant zeroinitializer
global to be constant folded, breaking this test.
The file was modifiedllvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
Commit 7ed01a420a2deb609b6b111d968a4dc673c68f19 by craig.topper
[RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.

As noted in the FIXME there's a sort of agreement that the any
extra bits stored will be 0.

The generated code is pretty terrible. I was really hoping we
could use a tail undisturbed trick, but tail undisturbed no
longer applies to masked destinations in the current draft
spec.

Fingers crossed that it isn't common to do this. I doubt IR
from clang or the vectorizer would ever create this kind of store.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100618
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
Commit 89a93889daa11a12ec22446cc05fa39493e94fb8 by listmail
Update a test for auto-update format change
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
Commit 87afefcd22c53f7bdc68b5a13492e7f2bfc9837a by craig.topper
[RISCV] Fix mistake in comment. NFC
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit e0adf7e06a9e329327db2c5e9809e1cbf2e7208d by Louis Dionne
[libc++][NFC] Move incrementable_traits and indirectly_readable_traits into separate headers.

Differential Revision: https://reviews.llvm.org/D100682
The file was modifiedlibcxx/include/iterator
The file was addedlibcxx/include/__iterator/readable_traits.h
The file was modifiedlibcxx/include/concepts
The file was modifiedlibcxx/include/CMakeLists.txt
The file was addedlibcxx/include/__iterator/concepts.h
The file was addedlibcxx/include/__iterator/incrementable_traits.h
Commit d440f9a326f06df067b26adf48df3d52e9a07b7b by nikita.ppv
[LICM] Make capture check more precise

During store promotion, we check whether the pointer was captured
to exclude potential reads from other threads. However, we're only
interested in captures before or inside the loop. Check this using
PointerMayBeCapturedBefore against the loop header.

Differential Revision: https://reviews.llvm.org/D100706
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
The file was modifiedllvm/test/Transforms/LICM/promote-capture.ll
Commit 03b98114ce5ca4d9b47df021083ad9c12f8738d1 by llvmgnsyncbot
[gn build] Port e0adf7e06a9e
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit 71d868cf9011673cae847502e651393a18631b8a by pklausler
[flang] Define missing & needed IEEE_ARITHMETIC symbols

Define IEEE_IS_NAN, IEEE_IS_FINITE, & IEEE_REM.

Differential Revision: https://reviews.llvm.org/D100599
The file was modifiedflang/runtime/numeric.cpp
The file was modifiedflang/include/flang/Evaluate/real.h
The file was modifiedflang/module/__fortran_builtins.f90
The file was modifiedflang/lib/Evaluate/fold-logical.cpp
The file was modifiedflang/unittests/RuntimeGTest/Numeric.cpp
The file was modifiedflang/runtime/numeric.h
The file was modifiedflang/lib/Evaluate/intrinsics.cpp
The file was modifiedflang/module/ieee_arithmetic.f90
Commit d8805574c183484f055552855fa82d2e8932415e by Yaxun.Liu
[CUDA][HIP] Allow non-ODR use of host var in device

Reviewed by: Artem Belevich, Richard Smith

Differential Revision: https://reviews.llvm.org/D98193
The file was modifiedclang/test/SemaCUDA/device-use-host-var.cu
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was addedclang/test/CodeGenCUDA/device-use-host-var.cu
The file was modifiedclang/lib/Headers/__clang_hip_math.h
The file was modifiedclang/test/Headers/hip-header.hip
Commit 2ec16103c68528669080040629961217662353cd by Pavel.Iliin
[AArch64] Peephole rule to remove redundant cmp after cset.

Comparisons to zero or one after cset instructions can be safely
removed in examples like:

cset w9, eq          cset w9, eq
cmp  w9, #1   --->   <removed>
b.ne    .L1          b.ne    .L1

cset w9, eq          cset w9, eq
cmp  w9, #0   --->   <removed>
b.ne    .L1          b.eq    .L1

Peephole optimization to detect suitable cases and get rid of that
comparisons added.

Differential Revision: https://reviews.llvm.org/D98564
The file was modifiedllvm/test/CodeGen/AArch64/f16-instructions.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/csinc-cmp-removal.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
Commit 6a4d9cb7e04d50d45819848ed8dc19c03242b8ca by Madhur.Amilkanthwar
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr

This patch removes -fixed-abi check for indirect calls
and also adds queue-ptr which is required for indirect calls to work.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D100633
The file was modifiedllvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-constant.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/unsupported-calls.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 94ba3b6e3bb3c9774f7a77c6759f12b3b7cf8690 by code
[compiler-rt][asan] use full vm range on apple silicon macs

We previously shrunk the mmap range size on ios, but those settings got inherited by apple silicon macs.
Don't shrink the vm range on apple silicon Mac since we have access to the full range.

Also don't shrink vm range for iOS simulators because they have the same range as the host OS, not the simulated OS.

rdar://75302812

Reviewed By: delcypher, kubamracek, yln

Differential Revision: https://reviews.llvm.org/D100234
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
Commit f7414759d739fc102f72432562e9aeb0a7424e66 by Jonas Devlieghere
[lldb] Print the fixed address if symbolication fails in DumpDataExtractor

When formatting memory with as eFormatAddressIn and symbolication fails,
fix the code address and print the symbol it points to, if any.
The file was modifiedlldb/source/Core/DumpDataExtractor.cpp
Commit a7712091ea7a2b4a7b5c4764af7545a7574b651b by Jonas Devlieghere
[lldb] Update breakpoint_function_callback.test for different error message

Adjust for the Lua error message printed by Lua 5.4.3.
The file was modifiedlldb/test/Shell/ScriptInterpreter/Lua/breakpoint_function_callback.test
Commit d88d8c5b8607bff56d0ccd6a500157487c5819e7 by Jinsong Ji
[PowerPC] Disable relative lookup table converter pass for AIX

XCOFF hasn't implemented lowerRelativeReference.
So we need to disable new pass introduced by https://reviews.llvm.org/D94355 for
AIX for now.

Reviewed By: gulfem

Differential Revision: https://reviews.llvm.org/D100584
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
Commit cc68799056da5c2159fa51425f998588ac650171 by Jonas Devlieghere
[lldb] Stop unsetting LLDB_DEBUGSERVER_PATH from TestLaunchProcessPosixSpawn

We no longer need this after Pavel's change to automatically find debug
servers to test. (3ca7b2d)
The file was modifiedlldb/test/API/macosx/posix_spawn/TestLaunchProcessPosixSpawn.py
Commit 1dc533cea4ae6b9f72f7df53516c9f5c152ce35a by nicolas.vasilache
[mlir][python] ExecutionEngine can dump to object file

Differential Revision: https://reviews.llvm.org/D100786
The file was modifiedmlir/lib/Bindings/Python/ExecutionEngine.cpp
The file was modifiedmlir/include/mlir-c/ExecutionEngine.h
The file was modifiedmlir/lib/CAPI/ExecutionEngine/ExecutionEngine.cpp
Commit 6c5b0d6beaaa634efce700e0c9cbd098e1c2e8a3 by martin
[libcxx] Base MSVC autolinking on _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS

Previously the decision of which library to try to autolink was
based on _DLL, however the _DLL define (which is set by the compiler)
is tied to whether using a dynamically linked CRT or not, and the choice
of dynamic or static CRT is entirely orthogonal to whether libc++ is
linked dynamically or statically.

If _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS isn't defined, then all
declarations are decorated with dllimport, and there's no doubt that
the DLL version of the library is what must be linked.

_LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS is defined if building with
LIBCXX_ENABLE_SHARED disabled, and thus the static library is what
should be linked.

If defining _LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS manually but wanting
to link against the DLL version of the library, that's not a canonical
configuration, and then it's probably reasonable to manually define
_LIBCPP_NO_AUTO_LINK too, and manually link against the desired
library.

This fixes, among other issues, running tests for the library if
built with LIBCXX_ENABLE_STATIC disabled.

Differential Revision: https://reviews.llvm.org/D100539
The file was modifiedlibcxx/include/__config
Commit e657c84fa10e36ccf9b36bfeba26219ffbb39773 by tlively
[WebAssembly] Use v128.const instead of splats for constants

We previously used splats instead of v128.const to materialize vector constants
because V8 did not support v128.const. Now that V8 supports v128.const, we can
use v128.const instead. Although this increases code size, it should also
increase performance (or at least require fewer engine-side optimizations), so
it is an appropriate change to make.

Differential Revision: https://reviews.llvm.org/D100716
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-offset.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/implicit-def.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Commit f9ddb81d79b2c6d0cf7e509f04f70f5c0c0560b3 by martin
[libcxx] [test] Ifdef out tests that rely on perms::none on directories for triggering errors

On Windows, one can't use perms::none on a directory to trigger
failures to read the directory entries.

These remaining tests can't use GetWindowsInaccessibleDir() sensibly,
e.g. for tests that rely on toggling accessibility back and forth during
the test, or where the semantics of the dir provided by
GetWindowsInaccessibleDir() doesn't allow for running the ifdeffed tests
meaningfully.

Differential Revision: https://reviews.llvm.org/D97538
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.obs/file_size.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.rec.dir.itr/rec.dir.itr.members/increment.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.remove/remove.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.status/status.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.mods/refresh.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.create_directory/create_directory_with_attributes.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.remove_all/remove_all.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.mods/replace_filename.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.obs/file_type_obs.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.obs/hard_link_count.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.symlink_status/symlink_status.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.last_write_time/last_write_time.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_entry/directory_entry.obs/last_write_time.pass.cpp
The file was modifiedlibcxx/test/support/test_macros.h
Commit abacaef1816254fc425fa81d137a8d54215d5913 by steveire
[AST] Update introspection API to use const-ref for copyable types

Differential Revision: https://reviews.llvm.org/D100720
The file was modifiedclang/unittests/Introspection/IntrospectionTest.cpp
The file was modifiedclang/include/clang/Tooling/NodeIntrospection.h
The file was modifiedclang/lib/Tooling/CMakeLists.txt
The file was modifiedclang/lib/Tooling/DumpTool/generate_cxx_src_locs.py
Commit 3d385cc90ea8bcbef5f80b671e6ae3c6d838895f by nikita.ppv
[InstCombine] Add tests for multiuse shr eq zero (NFC)

The exact case is folded, the inexact one is not.
The file was modifiedllvm/test/Transforms/InstCombine/icmp-shr.ll
Commit 9423f78240a216e3f38b394a41fe3427dee22c26 by nikita.ppv
[InstCombine] Fold multiuse shr eq zero

The single-use case is handled implicity by converting the icmp
into a mask check first. When comparing with zero in particular,
we don't need the one-use restriction, as we only produce a single
icmp.

https://alive2.llvm.org/ce/z/MSixcm
https://alive2.llvm.org/ce/z/GwpG0M
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/ctlz-loop.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp_sdiv_with_and_without_range.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp-shr.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 01801d5274101273f85b85221392a4e2e2bc574b by listmail
[rs4gc] Fix a latent bug around attribute stripping for intrinsics

This change fixes a latent bug which was exposed by a change currently in review (https://reviews.llvm.org/D99802#2685032).

The story on this is a bit involved.  Without this change, what ended up happening with the pending review was that we'd strip attributes off intrinsics, and then selectiondag would fail to lower the intrinsic.  Why?  Because the lowering of the intrinsic relies on the presence of the readonly attribute.  We don't have a matcher to select the case where there's a glue node needed.

Now, on the surface, this still seems like a codegen bug.  However, here it gets fun.  I was unable to reproduce this with a standalone test at all, and was pretty much struck until skatkov provided the critical detail.  This reproduces only when RS4GC and codegen are run in the same process and context.  Why?  Because it turns out we can't roundtrip the stripped attribute through serialized IR!

We'll happily print out the missing attribute, but when we parse it back, the auto-upgrade logic has a side effect of blindly overwriting attributes on intrinsics with those specified in Intrinsics.td.  This makes it impossible to exercise SelectionDAG from a standalone test case.

At this point, I decided to treat this an RS4GC bug as a) we don't need to strip in this case, and b) I could write a test which shows the correct behavior to ensure this doesn't break again in the future.

As an aside, I'd originally set out to handle libfuncs too - since in theory they might have the same issues - but backed away quickly when I realized how the semantics of builtin, nobuiltin, and no-builtin-x all interacted.  I'm utterly convinced that no part of the optimizer handles that correctly, and decided not to open that can of worms here.
The file was addedllvm/test/Transforms/RewriteStatepointsForGC/X86/intrinsic-attributes.ll
The file was modifiedllvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
The file was addedllvm/test/Transforms/RewriteStatepointsForGC/X86/lit.local.cfg
Commit 782c3e23ba09ca7b01034d0fbf0b34044c1c79a3 by steveire
[AST] Fix comparison to of SourceRanges in container

Differential Revision: https://reviews.llvm.org/D100723
The file was modifiedclang/lib/Tooling/NodeIntrospection.cpp
The file was modifiedclang/unittests/Introspection/IntrospectionTest.cpp
Commit 3c54762226ed9bcb84dfdef9f8e6e6a2c6a971a0 by listmail
[funcattrs] Consistently check call site attributes

This is mostly stylistic cleanup after D100226, but not entirely. When skimming the code, I found one case where we weren't accounting for attributes on the callsite at all. I'm also suspicious we had some latent bugs related to operand bundles (which are supposed to be able to *override* attributes on declarations), but I don't have concrete test cases for those, just suspicions.

Aside: The only case left in the file which directly checks attributes on the declaration is the norecurse logic. I left that because I didn't understand it; it looks obviously wrong, so I suspect I'm misinterpreting the intended semantics of the attribute.

Differential Revision: https://reviews.llvm.org/D100689
The file was modifiedllvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll
The file was modifiedllvm/test/Transforms/FunctionAttrs/noreturn.ll
The file was modifiedllvm/lib/Transforms/IPO/FunctionAttrs.cpp
Commit 78a871abf7018f4a288b773c9c89f99cd5c66b9c by david.green
[ARM] Use ProcResGroup in Cortex-M7 scheduling model

Used to model structural hazards on FP issue, where some
instructions take up 2 issue slots and others one as well
as similar structural hazards on load issue, where some
instructions take up two load lanes and others one.

Differential Revision: https://reviews.llvm.org/D98977
The file was modifiedllvm/test/tools/llvm-mca/ARM/m7-int.s
The file was modifiedllvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/ARM/m7-fp.s
The file was addedllvm/test/CodeGen/ARM/cortex-m7-wideops.mir
The file was modifiedllvm/lib/Target/ARM/ARMScheduleM7.td
Commit ca8eef7e3da8f750d7c7aa004fe426d1d34787ea by david.green
[CodeGen] Use ProcResGroup information in SchedBoundary

When the ProcResGroup has BufferSize=0,

1. if there is a subunit in the list of write resources for the
   scheduling class, do not attempt to schedule the ProcResGroup.
2. if there is not a subunit in the list of write resources for the
   scheduling class, choose a subunit to use instead of the ProcResGroup.
3. having both the ProcResGroup and any of its subunits in the resources
   implied by a InstRW is not supported.

Used to model parallel uses from a pool of resources.

Differential Revision: https://reviews.llvm.org/D98976
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/test/CodeGen/ARM/cortex-m7-wideops.mir
Commit d6fde913790db898e72e27b51defbc7442f3418a by a.bataev
[SLP]Add detection of shuffled/perfect matching of tree entries.

SLP supports perfect diamond matching for the vectorized tree entries
but do not support it for gathered entries and does not support
non-perfect (shuffled) matching with 1 or 2 tree entries. Patch adds
support for this matching to improve cost of the vectorized tree.

Differential Revision: https://reviews.llvm.org/D100495
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll