SuccessChanges

Summary

  1. tsan: remove unused caller_pc from TsanInterceptorContext (details)
  2. tsan: remove mallopt calls (details)
  3. [clan-format] detect function definitions more conservatively (details)
  4. [scudo] Make Vector() constexpr (details)
  5. [RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG. (details)
  6. [VectorCombine] Add tests where the index is guaranteed non-poison. (details)
  7. [ELF] Add --export-dynamic-symbol-list (details)
  8. [MCA][NFC] Add tests for PR51318 and PR51322. (details)
  9. [MLIR][Linalg] Extend detensoring control flow model. (details)
  10. [llvm] Fix header guards (NFC) (details)
  11. [AArch64] Prefer fmov over orr v.16b when copying f32/f64 (details)
  12. [NFC][tsan] Rename _inl.h to .inc (details)
  13. tsan: fix a typo in debug output (details)
  14. [AArch64][SME] Fix out of date comment (details)
  15. [llvm-profgen] Support perf script without parsing MMap events (details)
  16. [NFC][MLIR] Split large fusion test file into 4 test files (details)
  17. Reorder mmt4d r.h.s operand layout (details)
Commit 7779f49bc1f00eff3aba590a8e960d22a595f69f by dvyukov
tsan: remove unused caller_pc from TsanInterceptorContext

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107340
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit ac2bc4e0fc4c0c9d4903b49b445451d5d42356db by dvyukov
tsan: remove mallopt calls

mallopt calls are left-over from the times we used
__libc_malloc/__libc_free for internal allocations.
Now we have own internal allocator, so this is not needed.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107342
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit f6bc614546e169bb1b17a29c422ebace038e6c62 by krasimir
[clan-format] detect function definitions more conservatively

https://reviews.llvm.org/D105964 updated the detection of function
definitions. It had the unfortunate effect to start marking object
definitions with attribute-like macros as function definitions.

This addresses this issue.

Reviewed By: owenpan

Differential Revision: https://reviews.llvm.org/D107269
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit 23a94af44939b094f9ba2d6bb969f5a48b78fa8c by kostyak
[scudo] Make Vector() constexpr

A `Vector` that doesn't require an initial `reserve()` (eg: with a
default, or small enough capacity) can have a constant initializer.

This changes the code in a few places to make that possible:
- mark a few other functions as `constexpr`
- do without any `reinterpret_cast`
- allow to skip `reserve` from `init`

Differential Revision: https://reviews.llvm.org/D107308
The file was modifiedcompiler-rt/lib/scudo/standalone/vector.h
Commit deaeb16d88e92be644a157d499e9862cde4f22aa by craig.topper
[RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG.

Return false from runOnFunction if nothing changed. Curiously
we already returned a bool from detectAndFoldOffset, but didn't
use it.

Fix a couple breaks after returns that I saw while auditing
detectAndFoldOffset.

Differential Revision: https://reviews.llvm.org/D107303
The file was modifiedllvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
Commit ccf1038a92971d9f3faa9b7940430d3891bab2b8 by flo
[VectorCombine] Add tests where the index is guaranteed non-poison.

Tests for PR50949.
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
Commit 44361e5b90986ebe64c2263cefe504bf9b170eac by i
[ELF] Add --export-dynamic-symbol-list

This is available in GNU ld 2.35 and can be seen as a shortcut for multiple
--export-dynamic-symbol, or a --dynamic-list variant without the symbolic intention.

In the long term, this option probably should be preferred over --dynamic-list.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D107317
The file was modifiedlld/ELF/Options.td
The file was modifiedlld/docs/ReleaseNotes.rst
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/docs/ld.lld.1
The file was modifiedlld/test/ELF/export-dynamic-symbol.s
Commit f0658c7a429b9e356da1670b280ab943ad0b0b94 by andrea.dibiagio
[MCA][NFC] Add tests for PR51318 and PR51322.

Also, regenerate existing X86 tests using update_mca_test.py.
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-stats-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-stats-2.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-views-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-views-1.s
Commit f984a805f3f92ea3066ea13ba2684a7947d95225 by kareem.ergawy
[MLIR][Linalg] Extend detensoring control flow model.

This patch extends the PureControlFlowDetectionModel to consider
detensoring br and cond_br operands.

See: https://github.com/google/iree/issues/1159#issuecomment-884322687,
for a disccusion on the need for such extension.

Reviewed By: silvas

Differential Revision: https://reviews.llvm.org/D107358
The file was addedmlir/test/Dialect/Linalg/detensorize_br_operands.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Detensorize.cpp
Commit eec96db184fee4a3e67e9eb97efc29bc7452007c by kazu
[llvm] Fix header guards (NFC)

Identified with llvm-header-guard.
The file was modifiedllvm/include/llvm/TextAPI/Target.h
The file was modifiedllvm/include/llvm/Analysis/ObjCARCUtil.h
The file was modifiedllvm/include/llvm/AsmParser/LLLexer.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
The file was modifiedllvm/include/llvm/TextAPI/Architecture.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Shared/WrapperFunctionUtils.h
The file was modifiedllvm/include/llvm/TextAPI/Platform.h
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/ELF_riscv.h
The file was modifiedllvm/include/llvm/TextAPI/TextAPIReader.h
The file was modifiedllvm/include/llvm/TextAPI/InterfaceFile.h
The file was modifiedllvm/include/llvm/TextAPI/PackedVersion.h
The file was modifiedllvm/include/llvm/AsmParser/LLToken.h
The file was modifiedllvm/include/llvm/TextAPI/ArchitectureSet.h
The file was modifiedllvm/include/llvm/TextAPI/TextAPIWriter.h
The file was modifiedllvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
The file was modifiedllvm/include/llvm/TextAPI/Symbol.h
Commit bd07c2e266f65acb0204198ae1a441bf10499cb2 by david.green
[AArch64] Prefer fmov over orr v.16b when copying f32/f64

This changes the lowering of f32 and f64 COPY from a 128bit vector ORR to
a fmov of the appropriate type. At least on some CPU's with 64bit NEON
data paths this is expected to be faster, and shouldn't be slower on any
CPU that treats fmov as a register rename.

Differential Revision: https://reviews.llvm.org/D106365
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-copy.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec-libcalls.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-combiner.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-aapcs.ll
The file was modifiedllvm/test/CodeGen/AArch64/mla_mls_merge.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/sqrt-fastmath.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
The file was modifiedllvm/test/CodeGen/AArch64/neon-mla-mls.ll
The file was modifiedllvm/test/CodeGen/AArch64/fadd-combines.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
The file was modifiedllvm/test/CodeGen/AArch64/f16-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
Commit 6538aa8ce9b0806f0d343e0029c9a982d5971092 by Vitaly Buka
[NFC][tsan] Rename _inl.h to .inc

Differential Revision: https://reviews.llvm.org/D107319
The file was addedcompiler-rt/lib/tsan/rtl/tsan_interface.inc
The file was removedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/tsan/BUILD.gn
The file was removedcompiler-rt/lib/tsan/rtl/tsan_update_shadow_word_inl.h
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was addedcompiler-rt/lib/tsan/rtl/tsan_update_shadow_word.inc
Commit e34d1942a05eaf93834754d4f433ebf3afbdb4a0 by dvyukov
tsan: fix a typo in debug output

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D107368
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_java.cpp
Commit 86e4d0059374d69ddde265cf6c69d32ce4499d63 by cullen.rhodes
[AArch64][SME] Fix out of date comment

Missed in 3a349d22692c.
The file was modifiedllvm/test/MC/AArch64/SME/feature.s
Commit fe3ba90830f6ee84f9bb305606dec38451c4c884 by wlei
[llvm-profgen] Support perf script without parsing MMap events

This change supports to run without parsing MMap binary loading events instead it always assumes binary is loaded at the preferred address. This is used when we have assured no binary load address changes or we have pre-processed the addresses resolution. Warn if there's interior mmap event but without leading mmap events.

Reviewed By: hoy

Differential Revision: https://reviews.llvm.org/D107097
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was modifiedllvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test
The file was addedllvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
Commit 24b0df868604b079aebd30ca2ae2a11a30d3b97e by sumesh.uk
[NFC][MLIR] Split large fusion test file into 4 test files

mlir/test/transforms/loop-fusion.mlir is too big and is split into mlir/test/transforms/loop-fusion.mlir,  mlir/test/transforms/loop-fusion-2.mlir, mlir/test/transforms/loop-fusion-3.mlir
and mlir/test/transforms/loop-fusion-4.mlir. Further tests can be added in mlir/test/transforms/loop-fusion-4.mlir

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D106473
The file was addedmlir/test/Transforms/loop-fusion-2.mlir
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
The file was addedmlir/test/Transforms/loop-fusion-4.mlir
The file was addedmlir/test/Transforms/loop-fusion-3.mlir
Commit 53d6988171aed2c71d920b940264774f73248ca1 by ataei
Reorder mmt4d r.h.s operand layout

Switch r.h.s operand layout (n1, k1, n0, k0) -> (n1, k1, k0, n0)
which is more consistant with scalar-vector products vectorization
and elementates operand transpose.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D107307
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py