Changes

[Zorg] Add AArch64 SVE Vector-Length-Agnostic bots

... and update AArch64 SVE Vector-Length-Specific bots to use new options.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D107436

[InstCombine] rotate(X,Z) eq/ne rotate(Y,Z) ---> X eq/ne Y (PR51565)

```

----------------------------------------
define i1 @src(i8 %x, i8 %y, i8 %z) {
%0:
  %f = fshl i8 %x, i8 %x, i8 %z
  %f2 = fshl i8 %y, i8 %y, i8 %z
  %r = icmp eq i8 %f, %f2
  ret i1 %r
}
=>
define i1 @tgt(i8 %x, i8 %y, i8 %z) {
%0:
  %r = icmp eq i8 %x, %y
  ret i1 %r
}
Transformation seems to be correct!

```

https://alive2.llvm.org/ce/z/qAZp8f

Solves PR51565

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D109271

[AsmPrinter] Remove unneeded MCSubtargetInfo temporary after D14346. NFC

The temporary object was used as a workaround when the target parser may
change STI. D14346 made the MCSubtargetInfo argument to
createMCAsmParser const, so we no longer need the temporary object.

[NFC] Added testcases for new binop with select transformation

[CMake] Re-enable use --gc-sections on OpenBSD

Most archs have switched to lld.

[verify-uselistorder] Support -force-opaque-pointers

By creating LLVMContext after parsing parameters.

[lld-macho] Initialize LTO backend with diagnostic handler

Failing to do so results in `std::bad_function_call` being
thrown when a pass tries to emit a diagnostic.

I've copied the relevant test over from LLD-ELF's test suite.

Reviewed By: #lld-macho, thevinster

Differential Revision: https://reviews.llvm.org/D109274

[SLP][Test] Add tests for PR47624 and PR49933

Add tests monitoring issues fix. They should be fixed when
https://reviews.llvm.org/D57059 ("Initial support for the vectorization
of the non-power-of-2 vectors") is landed.

[test] Cleanup legacy PM tests in llvm/test/DebugInfo

[test] Cleanup legacy PM tests in llvm/test/Analyis/ScalarEvolution

[test] Cleanup tests with -enable-new-pm in llvm/test/Analysis

[M68k][test] Migrate the remaining fixup and relaxation tests

Migrate the tests regarding fixup and relaxation on branch and call
targets.
This patch wraps up the migration from `test/CodeGen/M68k/Encoding` to
`test/MC/M68k`.

[test] Fixup tests with -analyze in llvm/test/Transforms

[OpenMP][OpenMPIRBuilder] Implement loop unrolling.

Recommit of 707ce34b06190e275572c3c46843036db1bab6d1. Don't introduce a
dependency to the LLVMPasses component, instead register the required
passes individually.

Add methods for loop unrolling to the OpenMPIRBuilder class and use them in Clang if `-fopenmp-enable-irbuilder` is enabled. The unrolling methods are:

 * `unrollLoopFull`
 * `unrollLoopPartial`
 * `unrollLoopHeuristic`

`unrollLoopPartial` and `unrollLoopHeuristic` can use compiler heuristics to automatically determine the unroll factor. If possible, that is if no CanonicalLoopInfo is required to pass to another method, metadata for LLVM's LoopUnrollPass is added. Otherwise the unroll factor is determined using the same heurstics as user by LoopUnrollPass. Not requiring a CanonicalLoopInfo, especially with `unrollLoopHeuristic` allows greater flexibility.

With full unrolling and partial unrolling with known unroll factor, instead of duplicating instructions by the OpenMPIRBuilder, the full unroll is still delegated to the LoopUnrollPass. In case of partial unrolling the loop is first tiled using the existing `tileLoops` methods, then the inner loop fully unrolled using the same mechanism.

Reviewed By: jdoerfert, kiranchandramohan

Differential Revision: https://reviews.llvm.org/D107764

[libc][Obvious] Fix typos

[libc][Obvious] Reorder CMakelists alphabetically.

[DAG] Add tests for select_cc and setcc with constant patterns.

[InstCombine] stpcpy(d,s) -> strcpy(d,s) if the result is not used

[DAG] Fold setcc eq with ashr to compare to zero.

Pulled out of D109149, this folds set_cc seteq (ashr X, BW-1), -1 ->
set_cc setlt X, 0 to prevent some regressions later on when folding
select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C

Differential Revision: https://reviews.llvm.org/D109214

[DAG] Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C

Given a select_cc producing a constant and a invertion of the constant
for a comparison more than zero, we can produce an xor with ashr
instead, which produces smaller code. The ashr either sets all bits or
clear all bits depending on if the value is negative. This is then xor'd
with the constant to optionally negate the value.
https://alive2.llvm.org/ce/z/DTFaBZ

This includes a OneUseCheck on the Cmp, which seems to make thinks a
little worse and will be removed in a followup.

Differential Revision: https://reviews.llvm.org/D109149

[CostModel][X86] Add vXi32 multiply pattern tests

Add tests for vXi32 multiplies where the operands have been extended from vXi8/vXi16

[CostModel][X86] Add generic costs for vXi32 MUL -> v2Xi16 PMADDDW folds

Based off the improved fold in D108522

This should eventually allow us to replace the SLM only cost patterns with generic versions.

[DAG] Remove oneuse check in select_cc setgt X, -1, C, ~C fold

This appears to produce better code, even if the condition may need to
be replicated.

[clang-tidy] Drop unnecessary const from return types (NFC)

Identified with readability-const-return-type.

[test] Remove -loop-guard-widening legacy PM tests

[test] Remove some legacy PM tests in llvm/test/Instrumentation

[test] Remove some legacy PM tests in llvm/test/Instrumentation/AddressSanitizer

[Bazel] Add missing dependency after 650bbc56203c947bb85176c40ca9c7c7a91c3c57

[libc++][compare] Implement three_way_comparable[_with] concepts

Implementation of `three_way_comparable` and `three_way_comparable_with` concepts from <compare> header.

Please note that I have temporarily removed `<compare>` header from `<utility>` due to cyclic dependency that prevents using `<concepts>` header in `<compare>` one.

I tried to quickly resolve those issues including applying suggestions from @cjdb and dive deeper by myself but the problem seems more complicated that we thought initially.

I am in progress to prepare the patch with resolving this cyclic dependency between headers but for now I decided to put all that I have to the review to unblock people that depend on that functionality. At first glance the patch with resolving cyclic dependency is not so small (unless I find the way to make it smaller and cleaner) so I don't want to mix everything to one review.

Reviewed By: ldionne, cjdb, #libc, Quuxplusone

Differential Revision: https://reviews.llvm.org/D103478

[gn build] Port 8ce2675b1363

[AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z

Currently, we use SExtValue to decide whether to invert tbz or tbnz.
However, for the case zext (xor x, c), we should use ZExt rather
than SExt otherwise we will generate totally opposite branches.

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D108755

[AArch64] Remove an uneeded !NeedsWinCFI check. NFC

[mlir][docs] Complement list of supported scf ops

[clang-nvlink-wrapper] Add documentation in clang docs

Add documentation of clang-nvlink-wrapper tool in clang.
Add it to the release notes of clang. Fix a small MSVC
warning.

Differential Revision: https://reviews.llvm.org/D109225

[Flang] Ported test_errors.sh to Python

To enable Flang testing on Windows, shell scripts have to be ported to Python. In this patch the "test_errors.sh" script is ported to python ("test_errors.py"). The RUN line of existing tests was changed to make use of the python script.

Used python regex in place of awk/sed.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D107575

[RuntimeDyld] Implemented relocation for ELF::R_X86_64_GOTPC32

Differential Revision: https://reviews.llvm.org/D95512

[RuntimeDyld] Implemented relocation of TLS symbols in ELF

Differential Revision: https://reviews.llvm.org/D105466

Revert "[compiler-rt][Profile] Disable test on Arm/AArch64 Linux"

This reverts commit 8b86f8a3256a59cbaa12858cb0842025d48f549f.

The inconsistent behaviour has been fixed with
5e50d3073a5ead122a731580ded3f1cb3c21ee54.

[mlir][linalg] Fix `FoldInitTensorWithDimOp` if dim(init_tensor) is static.

It looks like it was a typo. Instead of `*maybeConstantIndex`,
`initTensorOp.getStaticSize(*maybeConstantIndex)` should be used to access the
dim size of the tensor. There is a test for that in `canonicalize.mlir`, but it
was working correctly because `ReplaceStaticShapeDims` was canonicalizing DimOp
before `FoldInitTensorWithDimOp`. So, to make the patterns more "orthogonal",
this case is disabled.

Differential Revision: https://reviews.llvm.org/D109247

[hwasan] Test use-after-scope with -fno-exceptions.

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D109224

[OpenCL] Supports optional generic address space semantics in C++ for OpenCL 2021

Adds support for a feature macro `__opencl_c_generic_adress_space`
in C++ for OpenCL 2021 enabling a respective optional core feature
from OpenCL 3.0. Testing is only performed in SemaOpenCL because
generic address space functionality is yet to be implemented in
C++ for OpenCL 2021.

This change aims to achieve compatibility between C++ for OpenCL
2021 and OpenCL 3.0.

Differential Revision: https://reviews.llvm.org/D108461

[X86] Add CRC32 feature.

d8faf03807ac implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this
instruction and allows it to be used with general-regs-only.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D105462

[gn build] Port 12fa608af44a

[Sanitizer] Intercept clock_getcpuid/pthread_getcpuid on netbsd.

Reviewed By: mgorny

Differential Revision: https://reviews.llvm.org/D109278

[VectorUtils] Teach findScalarElement to return splat value.

If the vector is a splat of some scalar value, findScalarElement()
can simply return the scalar value if it knows the requested lane
is in the vector.

This is only needed for scalable vectors, because the InsertElement/ShuffleVector
case is already handled explicitly for the fixed-width case.

This helps to recognize an InstCombine fold like:
  extractelt(bitcast(splat(%v))) -> bitcast(%v)

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D107254

[Clang] Add __ibm128 type to represent ppc_fp128

Currently, we have no front-end type for ppc_fp128 type in IR. PowerPC
target generates ppc_fp128 type from long double now, but there's option
(-mabi=(ieee|ibm)longdouble) to control it and we're going to do
transition from IBM extended double-double ppc_fp128 to IEEE fp128 in
the future.

This patch adds type __ibm128 which always represents ppc_fp128 in IR,
as what GCC did for that type. Without this type in Clang, compilation
will fail if compiling against future version of libstdcxx (which uses
__ibm128 in headers).

Although all operations in backend for __ibm128 is done by software,
only PowerPC enables support for it.

There's something not implemented in this commit, which can be done in
future ones:

- Literal suffix for __ibm128 type. w/W is suitable as GCC documented.
- __attribute__((mode(IF))) should be for __ibm128.
- Complex __ibm128 type.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D93377

[lldb] [llgs server] Support creating core dumps on NetBSD

Add a new SaveCore() process method that can be used to request a core
dump.  This is currently implemented on NetBSD via the PT_DUMPCORE
ptrace(2) request, and enabled via 'savecore' extension.

Protocol-wise, a new qSaveCore packet is introduced.  It accepts zero
or more semicolon-separated key:value options, invokes the core dump
and returns a key:value response.  Currently the only option supported
is "path-hint", and the return value contains the "path" actually used.
The support for the feature is exposed via qSaveCore qSupported feature.

Differential Revision: https://reviews.llvm.org/D101285

[lldb] Silence compiler warning after fae0dfa6421ea6c02f86ba7292fa782e1e2b69d1

lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4765:13: warning: enumeration value 'Ibm128' not handled in switch [-Wswitch]
    switch (llvm::cast<clang::BuiltinType>(qual_type)->getKind()) {
            ^

[AArch64] NFC: Regenerate CHECK lines for sve-masked-gather/scatter-legalize.ll

sve-masked-gather-legalize.ll said the check lines were generated by
the update_llc_test_checks script, but that was not the case.
This patch ensures both tests are generated with the script.

Change-Id: If6f0331ef01ace84017497a484161d1724ac0744

[lldb] Silence compiler warnings from 37cbd817d3e2b8c673862e2eb262cad6dd3dd244

lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp:3638:30: error: moving a temporary object prevents copy elision [-Werror,-Wpessimizing-move]
    return SendErrorResponse(std::move(ret.takeError()));
                             ^
lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp:3638:30: note: remove std::move call here
    return SendErrorResponse(std::move(ret.takeError()));
                             ^~~~~~~~~~               ~
lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp:3622:8: error: unused variable 'cf' [-Werror,-Wunused-variable]
  bool cf = packet_str.consume_front("qSaveCore");

[OpenCL] Fix condition macro name in test

[X86][mingw] Modify the alignment of __m128/__m256/__m512 vector type for mingw

This is a follow up patch after D78564 and D108887.

Martin helped to confirm the alignment in GCC mingw is the same as the
size of vector. https://reviews.llvm.org/D108887#inline-1040893

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D109265

[AArch64][sve] Prevent incorrect function call on fixed width vector

The isEssentiallyExtractHighSubvector function currently calls
getVectorNumElements on a type that in specific cases might be scalable.
Since this function only has correct behaviour at the moment on scalable
types anyway, the function can just return false when given a fixed type.

Differential Revision: https://reviews.llvm.org/D109163

[Flang] Port test_folding.sh to Python

To enable Flang testing on Windows,
shells scripts have to be ported to Python.
The following changes have been made:
Ported `test_folding.sh` to Python;
Additional changes to the tests themselves
to use the new script.

LIBPGMATH support for testing
not available at this point.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D108217

[AArch64][MC] Merge FeaturePMU into FeaturePerfMon

FeaturePMU was created in AArch64 to accommodate one missing system
register, PMMIR_EL1, in commit ffcd7698aea7bcbb2b4edffc484793e1ff47b85d.

However, the Performance Monitors extension already had a target
feature, which is called FeaturePerfMon. Therefore, FeaturePMU is
redundant.

This patch removes FeaturePMU and merges its contents into
FeaturePerfMon.

Reviewed By: dnsampaio

Differential Revision: https://reviews.llvm.org/D109246

[Flang] Port test_modfile.sh to Python

To enable Flang testing on Windows, shell scripts have
to be ported to Python. The following changes have been made:
"test_modfile.sh" has been ported to Python, and
the relevant tests relying on it.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D107956

[InstCombine] add test for shift-trunc-shift with extra uses; NFC

The transform doesn't check for extra uses, so we
have more instructions than we started with.

[InstCombine] early exit to reduce indentation; NFC

[InstCombine] fix one-use condition for shift transform

This transform is written in a confusing style,
and I suspect it is at fault for a more serious
bug noted in PR51567.

But it's been around forever, so I'm making the
minimal change to fix another bug - it could
increase instructions because it was not checking
uses.

[InstCombine] refactor to reduce indent; NFC

This transform should be updated to use better
variable names and code comments. It could
also create the shift-of-shift directly instead
of relying on another combine for that.

[InstCombine] fix infinite loop from shift transform

I'm not sure if there is a better way or another bug
still here, but this is enough to avoid the loop from:
https://llvm.org/PR51657

The test requires multiple blocks and datalayout to
trigger the problem path.

[SelectionDAGBuilder]  Bugfix in visitInlineAsm()

In case of a virtual register tied to a phys-def, the register class needs to
be computed. Make sure that this works generally also with fast regalloc by
using TLI.getRegClassFor() whenever possible, and make only the case of
'Untyped' use getMinimalPhysRegClass().

Fixes https://bugs.llvm.org/show_bug.cgi?id=51699.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D109291

[flang][plugins] Make `PluginParseTreeAction` an abstract class

There's no point in providing a default implementation for
`PluginParseTreeAction`. This patch makes it abstract forcing users to
specialise it in order to use it.

Differential Revision: https://reviews.llvm.org/D108518

[Support] Qualify auto (NFC)

Identified with readability-qualified-auto.

[lldb] Support SaveCore() from gdb-remote client

Extend PluginManager::SaveCore() to support saving core dumps
via Process plugins.  Implement the client-side part of qSaveCore
request in the gdb-remote plugin, that creates the core dump
on the remote host and then uses vFile packets to transfer it.

Differential Revision: https://reviews.llvm.org/D101329

DebugInfo: Add a FIXME/suggestion about using sibling/parent index to DWARFDebugInfoEntry

As a reminder if someone comes looking to improve iteration or parent
navigation performance of DWARFDebugInfoEntry.

[X86] Pre-commit test cases for D109295. NFC

[NFC] Added tests for D109283

[IRSim] Adding support for recognizing branch similarity

The current IRSimilarityIdentifier does not try to find similarity across blocks, this patch provides a mechanism to compare two branches against one another, to find similarity across basic blocks, rather than just within them.

This adds a step in the similarity identification process that labels all of the basic blocks so that we can identify the relative branching locations. Within an IRSimilarityCandidate we use these relative locations to determine whether if the branching to other relative locations in the same region is the same between branches. If they are, we consider them similar.

We do not consider the relative location of the branch if the target branch is outside of the region. In this case, both branches must exit to a location outside the region, but the exact relative location does not matter.

Reviewers: paquette, yroux

Differential Revision: https://reviews.llvm.org/D106989

[lldb] Fix pessimizing move warning

lldb/source/Core/PluginManager.cpp:695:21: warning: moving a temporary object prevents copy elision [-Wpessimizing-move]
      return Status(std::move(ret.takeError()));
                    ^
lldb/source/Core/PluginManager.cpp:695:21: note: remove std::move call here
      return Status(std::move(ret.takeError()));
                    ^~~~~~~~~~               ~

[DAGCombine] Prevent the transform of combine for multi-use operand

The test is based on a miscompile example in:
https://llvm.org/PR51321

Differential Revision: https://reviews.llvm.org/D107692

[SCEV] Fix applyLoopGuards() with range check idiom (PR51760)

Due to a typo, this replaced %x with umax(C1, umin(C2, %x + C3))
rather than umax(C1, umin(C2, %x)). This didn't make a difference
for the existing tests, because the result is only used for range
calculation, and %x will usually have an unknown starting range,
and the additional offset keeps it unknown. However, if %x already
has a known range, we may compute a result range that is too
small.

[ARM] Add tests for MVE narrowing intrinsic demand bits.

[X86] Simplify two hasFP(F). NFC

[X86] Simplify condition guarding emitCalleeSavedFrameMoves. NFC

[X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.

This is a more general version of D109273. Though it doesn't
peek through bitcasts or rearange broadcasts.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D109295

[mlir][linalg] linalg.tiled_loop peeling

Differential Revision: https://reviews.llvm.org/D108270

[RuntimeDyld] Guard UsedTLSStorage to x86 ELF only

UsedTLSStorage is only used in allocateTLSSection,
guarded in x87 ELF only.
So clang will emit error with -Werror on.

.../llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp:288:12:
error: private field 'UsedTLSStorage' is not used
[-Werror,-Wunused-private-field]
  unsigned UsedTLSStorage = 0;
           ^

[OpenMP][libomptarget] Change synchronize_ty return type to int32_t

Plugins always return int32_t. Stay consistent with other functions which return error status.

Differential Revision: https://reviews.llvm.org/D109341

[clang] Add '-ast-dump-filter=' support

Before this patch, we only support syntax like
`clang -cc1 -ast-dump -ast-dump-filter main a.c`
or
`clang -Xclang -ast-dump -Xclang -ast-dump-filter -Xclang main a.c`
when using ast-dump-filter.

It is helpful to also support `-ast-dump-filter=` syntax, so we can do
something like
`clang -cc1 -ast-dump -ast-dump-filter=main a.c`
or
`clang -Xclang -ast-dump -Xclang -ast-dump-filter=main a.c`

It is more cleaner when passing arguments through `-Xclang` in this case.

Also, **clang-check** do support this syntax, and I think people might
be confiused when they found they can't use `ast-dump-filter` with
clang.

[OpenMP][libomptarget] Change device vector elements to unique_ptr type

Using std::vector<DeviceTy> requires implementing copy constructor and copied assign operator for DeviceTy.
Indeed DeviceTy should never be copied. After changing to std::vector<std::unique_ptr<DeviceTy>>,
All the unsafe copy constructor and copy assign operator implementations can be removed.
Compilers mark them deleted due to mutex or underlying objects and this is the desired behavior.

Differential Revision: https://reviews.llvm.org/D109276

[clangd] Omit type hints that are too long

Differential Revision: https://reviews.llvm.org/D108972

[clangd] Omit default template arguments from type hints

Differential Revision: https://reviews.llvm.org/D108975

[llvm-exegesis] Add unit test in preparation for DD109275

[ARM][test] Add new tests for (mul (add r, c0), c1)

Reviewed By: RKSimon, dmgreen

Differential Revision: https://reviews.llvm.org/D109123

[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)

Prevent the folding in DAGCombine if it leads to worse code.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D109124

[compiler-rt] Document that builtins is known to work on OpenBSD.

Differential Revision: https://reviews.llvm.org/D109346

Mention OpenBSD in the documentation

[RuntimeDyld] Don't use bitwise operation on SymbolRef::Type

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D109292

[SelectionDAG][VP] Fix MemSDNode::getBasePtr

Found while working on D108987. When interpreting VP nodes as
`MemSDNode` nodes, this function would return the incorrect indices.
This was due to `VP_GATHER` and having no "passthru", and both
`VP_GATHER` and `VP_SCATTER` having their mask operands *after* the base
pointer, unlike `MGATHER` and `MSCATTER`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D109308

[AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts.

When expanding pseudo insts, in order to create a new machine instr, we use BuildMI,
which will add implicit operands by default. And transferImpOps will also copy implicit
operands from old ones. Finally, duplicate implicit operands are added to the same inst.
Sometimes this can cause correctness issues. Like below inst,
    renamable $w18 = nsw SUBSWrr renamable $w30, renamable $w14, implicit-def dead $nzcv
After expanding, it will become
    $w18 = SUBSWrs renamable $w13, renamable $w14, 0, implicit-def $nzcv, implicit-def dead $nzcv
A redundant implicit-def $nzcv is added, but the dead flag is missing.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D109069

[OpenCL] Disallows static kernel functions in C++ for OpenCL

It is disallowed in OpenCL C to declare static kernel functions and
C++ for OpenCL is expected to inherit such behaviour. Error is now
correctly reported in C++ for OpenCL when declaring a static kernel
function.

Differential Revision: https://reviews.llvm.org/D109150

[exegesis][X86] ParallelSnippetGenerator: don't accidentally create serialized instructions

In the case of no tied variables, we pick random defs, and then random uses that don't alias with defs we just picked.
Sounds good, except that an X86 instruction may have implicit reg uses,
e.g. for `MULX` it's `EDX`/`RDX`: `Intel SDM, 4-162 Vol. 2B MULX — Unsigned Multiply Without Affecting Flags`
> Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand
> (the third operand) and stores the low half of the result in the second destination (second operand), the high half
> of the result in the first destination operand (first operand), without reading or writing the arithmetic flags.

And indeed, every once in a while `llvm-exegesis` happened to pick EDX as a def while measuring throughput,
and producing garbage output:
```
$ ./bin/llvm-exegesis -num-repetitions=1000000 -mode=inverse_throughput -repetition-mode=min --loop-body-size=4096 -dump-object-to-disk=false -opcode-name=MULX32rr --max-configs-per-opcode=65536
---
mode:            inverse_throughput
key:
  instructions:
    - 'MULX32rr EDX R11D R12D'
  config:          ''
  register_initial_values:
    - 'R12D=0x0'
    - 'EDX=0x0'
cpu_name:        znver3
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 1000000
measurements:
  - { key: inverse_throughput, value: 4.00014, per_snippet_value: 4.00014 }
error:           ''
info:            instruction has no tied variables picking Uses different from defs
assembled_snippet: 415441BC00000000BA00000000C4C223F6D4C4C223F6D4C4C223F6D4C4C223F6D4415CC3415441BC00000000BA0000000049B80200000000000000C4C223F6D4C4C223F6D44983C0FF75F0415CC3
...
```
```
$ ./bin/llvm-exegesis -num-repetitions=1000000 -mode=inverse_throughput -repetition-mode=min --loop-body-size=4096 -dump-object-to-disk=false -opcode-name=MULX32rr --max-configs-per-opcode=65536
---
mode:            inverse_throughput
key:
  instructions:
    - 'MULX32rr R13D EDX ECX'
  config:          ''
  register_initial_values:
    - 'ECX=0x0'
    - 'EDX=0x0'
cpu_name:        znver3
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 1000000
measurements:
  - { key: inverse_throughput, value: 3.00013, per_snippet_value: 3.00013 }
error:           ''
info:            instruction has no tied variables picking Uses different from defs
assembled_snippet: 4155B900000000BA00000000C4626BF6E9C4626BF6E9C4626BF6E9C4626BF6E9415DC34155B900000000BA0000000049B80200000000000000C4626BF6E9C4626BF6E94983C0FF75F0415DC3
...
```
Oops! Not only does that not look fun, i did hit that pitfail during AMD Zen 3 enablement.
While i have since then addressed this in rGd4d459e7475b4bb0d15280f12ed669342fa5edcd,
i suspect there may be other buggy results lying around, so we should at least stop producing them.

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D109275

[RISCV][VP] Custom lower VP_SCATTER and VP_GATHER

This patch adds support for the `VP_SCATTER` and `VP_GATHER` nodes by
lowering them to RVV's `vsox`/`vlux` instructions, respectively. This
process is almost identical to the existing `MSCATTER`/`MGATHER` support.

One extra change was made to `SelectionDAGLegalize` so that
`VP_SCATTER`'s operation action is derived from its stored "value"
operand rather than its return type (which is always the chain).

Reviewed By: craig.topper, rogfer01

Differential Revision: https://reviews.llvm.org/D108987

[RISCV][VP] Custom lower VP_STORE and VP_LOAD

This patch adds support for the vector-predicated `VP_STORE` and
`VP_LOAD` nodes. We do this in the same way we lower `MSTORE` and
`MLOAD`: to regular load/store instructions via intrinsics.

One necessary change was made to `SelectionDAGLegalize` so that
`VP_STORE` nodes' operation actions are taken from the stored "value"
operands, in the same vein as `STORE` or `MSTORE`.

Reviewed By: craig.topper, rogfer01

Differential Revision: https://reviews.llvm.org/D108999

[AMDGPU][GlobalISel] Legalize memcpy family of intrinsics

Legalize G_MEMCPY, G_MEMMOVE, G_MEMSET and G_MEMCPY_INLINE.

Corresponding intrinsics are replaced by a loop that uses loads/stores in
AMDGPULowerIntrinsics pass unless their length is a constant lower then
MemIntrinsicExpandSizeThresholdOpt (default 1024). Any G_MEM* instruction that
reaches legalizer should have a const length argument and should be expanded
into appropriate number of loads + stores.

Differential Revision: https://reviews.llvm.org/D108357

[KnownBits] Add support for X*X self-multiplication

Add KnownBits handling and unit tests for X*X self-multiplication cases which guarantee that bit1 of their results will be zero - see PR48683.

https://alive2.llvm.org/ce/z/NN_eaR

The next step will be to add suitable test coverage so this can be enabled in ValueTracking/DAG/GlobalISel - currently only a single Analysis/ScalarEvolution test is affected.

Differential Revision: https://reviews.llvm.org/D108992

Mention OpenBSD in the documentation

[NFC] Added test for stpcpy -> strcpy transformation with AS != 0

[llvm-exegesis] Analysis tests should run even without libpfm (PR51687)

Move inverse_throughput, latency and uops to sub-directories (like we already do for lbr), which require libpfm, so we can relax the lit limits for analysis tests in the x86 root directory.

Differential Revision: https://reviews.llvm.org/D109353

[SVE][NFC] Add SVE cost model tests for gathers/scatters

We previously didn't have any tests to defend the cost model
for gathers and scatters using SVE without a vscale_range
attribute. I've added tests to existing files:

  Analysis/CostModel/AArch64/sve-gather.ll
  Analysis/CostModel/AArch64/sve-scatter.ll

Differential Revision: https://reviews.llvm.org/D109055

[OpenMP] Change monotonicity of dynamic schedule

This patch changes the default monotonicity of dynamic schedule from
monotonic to non-monotonic when no modifier is specified.

Differential Revision: https://reviews.llvm.org/D109026

[AArch64][SVE] Implement all-inactive predicate with PFALSE.

Instead of using a WHILE XZR, XZR instruction, just emit a PFALSE.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D109311

[clang][Driver] Pick the last --driver-mode in case of multiple ones

This was an accidental behaviour change in D106789 and this patch
restores it back to original state.

Differential Revision: https://reviews.llvm.org/D109361

[llvm-exegesis][x86] Limit llvm-exegesis analysis tests to x86_64 triple hosts

Attempting to fix an issue with test failures on arm m1 apple macintoshes reported on D109353

[AggresiveInstCombine] Add wrapper calls for `KnownBits` computing

Precommit before `AssumptionCache` adding: reviews.llvm.org/D109141

Differential Revision: https://reviews.llvm.org/D109288

[AggressiveInstCombine][Test] Add test for assumptions

[AggressiveInstCombine] Add `AssumptionCache` to aggressive instcombine

Add support for @llvm.assume() to TruncInstCombine allowing
optimizations based on these intrinsics while computing known bits.

[X86] X86InstrFMA.td - remove unused template parameters. NFC.

Identified in D109359

[X86] X86InstrVecCompiler.td - remove unused template parameters. NFC.

Identified in D109359

[X86] X86InstrSSE.td - remove unused template parameters. NFC.

Identified in D109359

[AMDGPU][GlobalISel] Legalization of G_ROTL and G_ROTR

Add implementation for the legalization of G_ROTL and G_ROTR machine
instructions. They are very similar to funnel shift instructions, the only
difference is funnel shifts have 3 operands, whereas rotate instructions have
two operands, the first being the register that is being rotated and the second
being the number of shifts. The legalization of G_ROTL/G_ROTR is just lowering
them into funnel shift instructions if they are legal.

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D105347

[AMDGPU][GlobalISel] Legalize G_MUL for non-standard types

Legalizing G_MUL for non-standard types (like i33) generated an error. Putting
minScalar and maxScalar instead of clampScalar. Also using new rule, instead
of widening to the next power of 2, widen to the next multiple of the passed
argument (32 in this case), so instead of widening i65 to i128, we widen it to
i96.

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D109228

[amdgpu] Enable selection of `s_cselect_b64`.

Differential Revision: https://reviews.llvm.org/D109159

[MC] Add MCSubtargetInfo to MCAlignFragment

In preparation for passing the MCSubtargetInfo (STI) through to writeNops
so that it can use the STI in operation at the time, we need to record the
STI in operation when a MCAlignFragment may write nops as padding. The
STI is currently unused, a further patch will pass it through to
writeNops.

There are many places that can create an MCAlignFragment, in most cases
we can find out the STI in operation at the time. In a few places this
isn't possible as we are in initialisation or finalisation, or are
emitting constant pools. When possible I've tried to find the most
appropriate existing fragment to obtain the STI from, when none is
available use the per module STI.

For constant pools we don't actually need to use EmitCodeAlign as the
constant pools are data anyway so falling through into it via an
executable NOP is no better than falling through into data padding.

This is a prerequisite for D45962 which uses the STI to emit the
appropriate NOP for the STI. Which can differ per fragment.

Note that involves an interface change to InitSections. It is now
called initSections and requires a SubtargetInfo as a parameter.

Differential Revision: https://reviews.llvm.org/D45961

[MC] Use local MCSubtargetInfo in writeNops

On some architectures such as Arm and X86 the encoding for a nop may
change depending on the subtarget in operation at the time of
encoding. This change replaces the per module MCSubtargetInfo retained
by the targets AsmBackend in favour of passing through the local
MCSubtargetInfo in operation at the time.

On Arm using the architectural NOP instruction can have a performance
benefit on some implementations.

For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to
limit the chances of this causing problems in the future. I've not
done this for other targets such as X86 as there is more frequent use
of the MCSubtargetInfo and it looks to be for stable properties that
we would not expect to vary per function.

This change required threading STI through MCNopsFragment and
MCBoundaryAlignFragment.

I've attempted to take into account the in tree experimental backends.

Differential Revision: https://reviews.llvm.org/D45962