SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. [sanitizer] Add scudo tests on QEMU (details)
  2. [sanitizer] Improve naming of bot steps (details)
  3. [sanitizer] Fix typo in bot script (details)
  4. [sanitizer] Enabled QEMU bot failures (details)
Commit 204ef6a78f9dac27b936a358366c7980a9b24730 by Vitaly Buka
[sanitizer] Add scudo tests on QEMU
The file was addedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_standard.sh
Commit 525a9eb729da80ff14aff677c395dbeb131111f3 by Vitaly Buka
[sanitizer] Improve naming of bot steps
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit 15b3be560b439041f67a6ef9e9f1d553b8fe8f9b by Vitaly Buka
[sanitizer] Fix typo in bot script
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit d4933e72e558fd05fbef781e1f108d2f1ff2b88c by Vitaly Buka
[sanitizer] Enabled QEMU bot failures
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4 (details)
  2. [sanitizer] Use COMPILER_RT_EMULATOR with gtests (details)
  3. [scudo] Mark ARM64 as supported platform (details)
  4. [scudo][NFC] Fix cast warning (details)
  5. [clangd] Omit parameter hint if parameter name comment is present (details)
  6. [clangd] Omit parameter hint for setter functions (details)
  7. [clangd] Rename HeuristicResolver::resolveCallExpr() to resolveTypeOfCallExpr() (details)
  8. [ORC] Avoid invalidating iterators in EHFrameRegistrationPlugin. (details)
  9. [DebugInfo][AIX] Set target debugger-tune default to dbx (details)
  10. [RISCV] [1/2] Add IR intrinsic for Zbe extension (details)
  11. [RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs. (details)
  12. [RISCV] Optimize addition with immediate (details)
  13. [RISCV] Cleanup setOperationAction calls for INTRINSIC_WO_CHAIN/INTRINSIC_W_CHAIN (details)
  14. [RISCV] Implement the vmmv.m/vmnot.m builtin. (details)
  15. [RISCV] Implement the vfabs.v/vfneg.v builtin. (details)
  16. [RISCV] Implement the pseudo compare builtin. (details)
  17. [RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin. (details)
  18. [OpenCL] Add inc/dec/cmpxchg C++ legacy atomics with generic (details)
Commit 7b312e228c36fc10cec4ecbd98a289f213a97518 by lebedev.ri
[NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4

`X86TTIImpl::getInterleavedMemoryOpCostAVX2()` currently contains data
only for a handful of tuples. For now, at least add tests for a few more.

I'm guessing that we care how well the patterns codegen since
we use their presumed cost for vectorization decisions,
so i've added codegen tests too.

There's one really easy caveat for these codegen tests:
for interleaved load tests, we really have to ensure that the
deinterleaved vectors are escaped separately. Similarly for stores.
The file was addedllvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
The file was addedllvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
The file was addedllvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
The file was addedllvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
The file was addedllvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
The file was addedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was addedllvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
Commit 51b4a7ef52aa5c1877bb63a23724ac74dd9fc953 by Vitaly Buka
[sanitizer] Use COMPILER_RT_EMULATOR with gtests

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D100998
The file was modifiedcompiler-rt/unittests/lit.common.unit.cfg.py
The file was modifiedcompiler-rt/unittests/lit.common.unit.configured.in
The file was modifiedllvm/utils/lit/lit/formats/googletest.py
Commit 98a7563261ffae7466bbc49c684fd38c4b54ee7e by Vitaly Buka
[scudo] Mark ARM64 as supported platform
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit 337a024bba1dcf7d1dddc1a3f2750a9c777bbaa9 by Vitaly Buka
[scudo][NFC] Fix cast warning
The file was modifiedcompiler-rt/lib/scudo/standalone/linux.cpp
Commit 753b247d71d7e74dd6998735848a2d9e0b6317de by zeratul976
[clangd] Omit parameter hint if parameter name comment is present

Differential Revision: https://reviews.llvm.org/D100715
The file was modifiedclang-tools-extra/clangd/unittests/InlayHintTests.cpp
The file was modifiedclang-tools-extra/clangd/InlayHints.cpp
Commit 6f6cf2da8d9453f2bd57978be1e5d0765ea50a36 by zeratul976
[clangd] Omit parameter hint for setter functions

Differential Revision: https://reviews.llvm.org/D100731
The file was modifiedclang-tools-extra/clangd/InlayHints.cpp
The file was modifiedclang-tools-extra/clangd/unittests/InlayHintTests.cpp
Commit c624e701491c320cf5c662006082a8e956c30e8d by zeratul976
[clangd] Rename HeuristicResolver::resolveCallExpr() to resolveTypeOfCallExpr()

Differential Revision: https://reviews.llvm.org/D100741
The file was modifiedclang-tools-extra/clangd/HeuristicResolver.cpp
The file was modifiedclang-tools-extra/clangd/HeuristicResolver.h
Commit c1baf946e6cf611ae871e34db5cfea0f94f4b5a0 by Lang Hames
[ORC] Avoid invalidating iterators in EHFrameRegistrationPlugin.

In EHFrameRegistrationPlugin::notifyTransferringResources if SrcKey had
eh-frames associated but DstKey did not we would create a new entry for DskKey,
invalidating the iterator for SrcKey in the process. This commit fixes that by
removing SrcKey first in this case.
The file was modifiedllvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Commit 2c9028170eeb6749373f2f93ad6abdc0164c36a3 by Jinsong Ji
[DebugInfo][AIX] Set target debugger-tune default to dbx

https://reviews.llvm.org/D99400 set clang DefaultDebuggerTuning for AIX
to dbx. However, we still need to update the target default so that llc
and other tools will get the same default debuggertuning, and avoid
passing extra options in LTO.

Reviewed By: #powerpc, shchenz, dblaikie

Differential Revision: https://reviews.llvm.org/D101197
The file was modifiedllvm/test/DebugInfo/XCOFF/function-sections.ll
The file was addedllvm/test/DebugInfo/PowerPC/debugger-tune.ll
The file was modifiedllvm/test/DebugInfo/XCOFF/empty.ll
The file was modifiedllvm/test/DebugInfo/XCOFF/explicit-section.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit 8cf54c7ff50cc4db79b2bc633e7d9d96509ef000 by craig.topper
[RISCV] [1/2] Add IR intrinsic for Zbe extension

RV32/64:
bcompress
bdecompress

RV64 ONLY:
bcompressw
bdecompressw

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101143
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was addedllvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c
The file was addedllvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
The file was modifiedclang/include/clang/Basic/BuiltinsRISCV.def
Commit 8f5cd4940515899b06d6d1ecf593fbd6e08cce20 by craig.topper
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.

This teaches DAG combine that shift amount operands for grev, gorc
shfl, unshfl only read a few bits.

This also teaches DAG combine that grevw, gorcw, shflw, unshflw,
bcompressw, bdecompressw only consume the lower 32 bits of their
inputs.

In the future we can teach SimplifyDemandedBits to also propagate
demanded bits of the output to the inputs in some cases.
The file was modifiedllvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 60ed86d3507bf908e0079f78b246ae096321ae03 by powerman1st
[RISCV] Optimize addition with immediate

Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D101244
The file was modifiedllvm/test/CodeGen/RISCV/add-imm.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
Commit 837442de9c60f539dd901a2cc389a413d132b1bc by craig.topper
[RISCV] Cleanup setOperationAction calls for INTRINSIC_WO_CHAIN/INTRINSIC_W_CHAIN

We have several extensions that need i32 to be Custom for
INTRINSIC_WO_CHAIN with RV64 so enable it for all RV64.

For V extension, make i32 Custom for RV64 and i64 Custom for RV32.
When the i32 or i64 is legal, the operation action doesn't matter.
LegalizeDAG checks MVT::Other rather than the real type.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 4b2434172cc15ccd32c5c9110a3a4df18b8fba5e by kai.wang
[RISCV] Implement the vmmv.m/vmnot.m builtin.

Differential Revision: https://reviews.llvm.org/D100821
The file was modifiedclang/include/clang/Basic/riscv_vector.td
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c
Commit bfb3fca7e110a367c9589495575913d83bea7095 by kai.wang
[RISCV] Implement the vfabs.v/vfneg.v builtin.

Differential Revision: https://reviews.llvm.org/D100822
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
The file was modifiedclang/include/clang/Basic/riscv_vector.td
Commit 645c5f27a84d795fc658b49c702d77cc6145bfec by kai.wang
[RISCV] Implement the pseudo compare builtin.

Differential Revision: https://reviews.llvm.org/D100823
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
The file was modifiedclang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
The file was modifiedclang/include/clang/Basic/riscv_vector.td
Commit bd32c2d64842c8d474bcce0e73dcd8918b3e0f2f by kai.wang
[RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin.

Differential Revision: https://reviews.llvm.org/D100824
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c
The file was modifiedclang/include/clang/Basic/riscv_vector.td
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c
Commit 18772de1ecb1a23b483e29987ae708ab641b1134 by sven.vanhaastregt
[OpenCL] Add inc/dec/cmpxchg C++ legacy atomics with generic

Mirror the remaining C++ for OpenCL specific builtins from opencl-c.h
to the TableGen builtin functions.

Fixes PR50041 (part 2).
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td