SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Fixed bug introduced by D100497 - local variable jobs_flag referenced before assignment. (details)
  2. [zorg] Fix AnnotatedBuilder.py extra_args bug (details)
Commit 9710f7832a344854c51248164a0a4c55f2b6c1d1 by gkistanova
Fixed bug introduced by D100497 - local variable jobs_flag referenced before assignment.
The file was modifiedzorg/buildbot/builders/LibcxxAndAbiBuilder.py
Commit b766b0b8afb3cf857a9b0314aa807786d00372ee by enye.shi
[zorg] Fix AnnotatedBuilder.py extra_args bug

Do not assign WithProperties("--jobs=%(jobs:-)s") to
extra_args, because extra_args_with_props will perform
WithProperties(...) on all of the args in extra_args.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D101575
The file was modifiedzorg/buildbot/builders/AnnotatedBuilder.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [gn build] Port df323ba445f7 (details)
  2. [lldb] Make the NSSet formatter faster and less prone to infinite recursion (details)
  3. [CMake] Set correct CXX_FLAGS for relative-vtables variants (details)
  4. [libc++] Fixes std::to_chars for bases != 10. (details)
  5. [lld][WebAssembly] Add `--export-if-defined` (details)
  6. [SimplifyCFG] Common code sinking: fix application of profitability check (details)
  7. [AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects (details)
  8. RegAlloc: do not consider liveins to EH-pad successors as liveout. (details)
  9. [ASan] Rename `-fsanitize-address-destructor-kind=` to drop the `-kind` suffix. (details)
  10. AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return (details)
  11. Revert "RegAlloc: do not consider liveins to EH-pad successors as liveout." (details)
  12. [InstCombine] add tests for popcount with zext operand; NFC (details)
  13. [InstCombine] narrow popcount with zext operand (details)
  14. [mlir][sparse] migrate sparse operations into new sparse tensor dialect (details)
  15. [lld-macho] Make everything PIE by default (details)
  16. [lld-macho][nfc] Clean up header.s test (details)
  17. Basic block sections for functions with implicit-section-name attribute (details)
  18. [lld-macho] Remove stray file (details)
  19. Revert "[COST] Improve shuffle kind detection if shuffle mask is provided." (details)
  20. [COST] Improve shuffle kind detection if shuffle mask is provided. (details)
  21. [AMDGPU] Fix v_swap_b32 formation on physical registers (details)
  22. [mlir] Fix lowering of multi-dimensional vector log1p to LLVM (details)
  23. Revert "Generalize getInvertibleOperand recurrence handling slightly" (details)
  24. [flang][OpenMP][FIX] Fix the worksharing nesting check with inclusion of more constructs to cover combined constructs. (details)
  25. [LLD] [COFF] Fix the mingw --export-all-symbols behaviour with comdat symbols (details)
  26. [llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets (details)
  27. Revert "[mlir][sparse] migrate sparse operations into new sparse tensor dialect" (details)
  28. [AArch64][GlobalISel] Simplify out of range rotate amount. (details)
  29. Revert "[llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets" (details)
  30. [ORC] JITDylib::addDependencies should be run under the session lock. (details)
  31. [CMake] Stop using c++ subdirectory for libc++ on Win to ARM Linux cross builds. NFC (details)
  32. [GlobalISel][Legalizer] Bump up a smallvector size that was found to be too small. NFC. (details)
  33. [libcxx][ranges] Fix tests for stdlib types that conform to sized_sentinel_for. (details)
  34. Recommit "[clang][driver] Use the provided arch name for a Darwin target triple (details)
  35. [XCOFF] Handle the case when personality routine is an alias (details)
  36. [mlir][tosa] Remove constant-0 dim expr values from TOSA lowerings (details)
  37. [CodeGen] don't emit addrsig symbol if it's used only by metadata (details)
  38. [mlir][sparse] migrate sparse operations into new sparse tensor dialect (details)
  39. Reland "[lld-link] Enable addrsig table in COFF lto" (details)
  40. [ObjC][ARC] Don't enter the cleanup scope if the initializer expression (details)
  41. [msan] Remove dead function/fields (details)
  42. [Sema] Don't set BlockDecl's DoesNotEscape bit if the parameter type of (details)
  43. [AMDGPU] Remove dead early-out in GCNHazardRecognizer (details)
  44. [AMDGPU][NFC] Refactor hazard recognition IsHazardFn and IsExpiredFn (details)
  45. AMDGPU: Add missing runline to test (details)
  46. VirtRegMap: Add pass option to not clear virt regs (details)
  47. [lldb-vscode] Follow up of D99989 - store some strings more safely (details)
  48. VirtRegMap: Support partially allocated virtual registers (details)
  49. [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX (details)
  50. [MS] Preserve base register %rbx around cpuid (details)
  51. [CMake][compiler-rt] avoid conflict with builtin check_linker_flag (details)
  52. [RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed (details)
  53. [RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed (details)
  54. [AMDGPU] Skip promote-alloca for insertelement/insertvalue users (details)
  55. [InlineCost] Remove visitUnaryInstruction() (details)
  56. Pre-commit test for PPC vector extraction test (details)
Commit 5fbea826920f2ed51259093ae87b33b571833513 by llvmgnsyncbot
[gn build] Port df323ba445f7
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
Commit a76df78470d7994f73df0353225cbddc463cce63 by Raphael Isemann
[lldb] Make the NSSet formatter faster and less prone to infinite recursion

Right now to get the 'NSSet *` pointer value we first derefence it and then take
the address of the result.

Beside being inefficient this potentially can cause an infinite recursion if the
`pointer` value we get is a pointer of a type that the TypeSystem can't
derefence. If the pointer is for example some form of `void *` that the dynamic
type resolution can't resolve to an actual type, then the `Derefence` call goes
back to asking the formatters how to reference it. If the NSSet formatter then
checks if it's an NSSet variation under the hood then we just end infinitely
often recursion.

In practice this seems to happen with some form of Builtin.RawPointer we get
from a NSDictionary in Swift.

FWIW, no other formatter is doing the same deref->addressOf as here and there
doesn't seem to be any specific reason to do so in the git history (it's just
part of the initial formatter commit)

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D101537
The file was modifiedlldb/source/Plugins/Language/ObjC/NSSet.cpp
Commit ba631240ae9ccbf70f57c0ba22cf2dd5a3592da2 by phosek
[CMake] Set correct CXX_FLAGS for relative-vtables variants

We overrite CXX_FLAGS to enable relative vtables, but doing so
overwrites generic Fuchsia CXX_FLAGS leading to a build failure
on Windows.

Differential Revision: https://reviews.llvm.org/D101551
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
Commit 9393060f908b95f30267f2122b3a2aadb698aadb by koraq
[libc++] Fixes std::to_chars for bases != 10.

While working on D70631, Microsoft's unit tests discovered an issue.
Our `std::to_chars` implementation for bases != 10 uses the range
`[first,last)` as temporary buffer. This violates the contract for
to_chars:
[charconv.to.chars]/1 http://eel.is/c++draft/charconv#to.chars-1
`to_chars_result to_chars(char* first, char* last, see below value, int base = 10);`
"If the member ec of the return value is such that the value is equal to
the value of a value-initialized errc, the conversion was successful and
the member ptr is the one-past-the-end pointer of the characters
written."

Our implementation modifies the range `[member ptr, last)`, which causes
Microsoft's test to fail. Their test verifies the buffer
`[member ptr, last)` is unchanged. (The test is only done when the
conversion is successful.)

While looking at the code I noticed the performance for bases != 10 also
is suboptimal. This is tracked in D97705.

This patch fixes the issue and adds a benchmark. This benchmark will be
used as baseline for D97705.

Reviewed By: #libc, Quuxplusone, zoecarver

Differential Revision: https://reviews.llvm.org/D100722
The file was addedlibcxx/benchmarks/to_chars.bench.cpp
The file was modifiedlibcxx/test/support/charconv_test_helpers.h
The file was modifiedlibcxx/include/charconv
Commit a6f406480a223068875602fb46e7b1db74873564 by sbc
[lld][WebAssembly] Add `--export-if-defined`

Unlike the existing `--export` option this will not causes errors
or warnings if the specified symbol is not defined.

See: https://github.com/emscripten-core/emscripten/issues/13736

Differential Revision: https://reviews.llvm.org/D99887
The file was modifiedlld/wasm/Config.h
The file was modifiedlld/wasm/Options.td
The file was modifiedlld/wasm/Writer.cpp
The file was addedlld/test/wasm/export-if-defined.s
The file was modifiedlld/wasm/Driver.cpp
The file was modifiedlld/docs/WebAssembly.rst
Commit cc63203908daa3a844d09160375c191003ab970c by lebedev.ri
[SimplifyCFG] Common code sinking: fix application of profitability check

The profitability check is: we don't want to create more than a single PHI
per instruction sunk. We need to create the PHI unless we'll sink
all of it's would-be incoming values.

But there is a caveat there.
This profitability check doesn't converge on the first iteration!
If we first decide that we want to sink 10 instructions,
but then determine that 5'th one is unprofitable to sink,
that may result in us not sinking some instructions that
resulted in determining that some other instruction
we've determined to be profitable to sink becoming unprofitable.

So we need to iterate until we converge, as in determine
that all leftover instructions are profitable to sink.

But, the direct approach of just re-iterating seems dumb,
because in the worst case we'd find that the last instruction
is unprofitable, which would result in revisiting instructions
many many times.

Instead, i think we can get away with just two passes - forward and backward.
However then it isn't obvious what is the most performant way to update
InstructionsToSink.
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit ae3377c55343e83e7768f612398dda942b83a06e by wei.huang
[AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects

- Add new variantKinds for the symbol's variable offset and region handle
- Print the proper relocation specifier @gd in the asm streamer when emitting
  the TC Entry for the variable offset for the symbol
- Fix the switch section failure between the TC Entry of variable offset and
  region handle
- Put .__tls_get_addr symbol in the ProgramCodeSects with XTY_ER property

Reviewed by: sfertile

Differential Revision: https://reviews.llvm.org/D100956
The file was modifiedllvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/MC/MCExpr.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPC.h
The file was modifiedllvm/include/llvm/MC/MCExpr.h
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 438a63e13bf89ebe21768940976a6eea6285f5ff by Tim Northover
RegAlloc: do not consider liveins to EH-pad successors as liveout.

These registers get defined by the runtime, not the block being allocated, and
treating them as preassigned in RegAllocFast adds extra pressure, sometimes
enough to make the function unallocatable.
The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
The file was addedllvm/test/CodeGen/X86/regalloc-tight-invoke.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit 2d42b2ee7bafe76d6b2c792b73f7371cb1cf8d94 by Dan Liew
[ASan] Rename `-fsanitize-address-destructor-kind=` to drop the `-kind` suffix.

Renaming the option is based on discussions in https://reviews.llvm.org/D101122.

It is normally not a good idea to rename driver flags but this flag is
new enough and obscure enough that it is very unlikely to have adopters.

While we're here also drop the `<kind>` metavar. It's not necessary and
is actually inconsistent with the documentation in
`clang/docs/ClangCommandLineReference.rst`.

Differential Revision: https://reviews.llvm.org/D101491
The file was modifiedclang/test/CodeGen/asan-destructor-kind.cpp
The file was removedclang/test/Driver/fsanitize-address-destructor-kind.c
The file was modifiedclang/test/Driver/darwin-asan-mkernel-kext.c
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was addedclang/test/Driver/fsanitize-address-destructor.c
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was modifiedclang/include/clang/Driver/Options.td
Commit c34900e1335d490bf6f16fba55eacd4ecf831f72 by petar.avramovic
AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return

When atomic image intrinsic return value is unused, register class for
destination of a sub-register copy of return value ends up not being set.
This copy then hits 'Register class not set' assert later.
If return value has uses, register class is determined by use instruction.
Fix is to not create sub-register copy when image intrinsic destination has
no uses because it would be deleted by dead-mi-elimination later anyway.

Differential Revision: https://reviews.llvm.org/D101448
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit c1b7460b5b705d983ac40ac37449911d132c7db4 by Tim Northover
Revert "RegAlloc: do not consider liveins to EH-pad successors as liveout."

Some liveins *can* come from this block (e.g. any SSA value except the call),
it's only the ones that produce `landingpad` values that can't and I didn't
think it through properly.
The file was removedllvm/test/CodeGen/X86/regalloc-tight-invoke.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
Commit b142e9d1c5170baad39dee3e800032460554551a by spatel
[InstCombine] add tests for popcount with zext operand; NFC

PR50141
The file was modifiedllvm/test/Transforms/InstCombine/ctpop.ll
Commit 0f8b6686ac288cda8d14d2ec5b8ca98d188b0684 by spatel
[InstCombine] narrow popcount with zext operand

https://llvm.org/PR50141
The file was modifiedllvm/test/Transforms/InstCombine/ctpop.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit a6d92a971175d727873a9e7644913ee02d7232a8 by ajcbik
[mlir][sparse] migrate sparse operations into new sparse tensor dialect

This is the very first step toward removing the glue and clutter from linalg and
replace it with proper sparse tensor types. This revision migrates the LinalgSparseOps
into SparseTensorOps of a sparse tensor dialect. This also provides a new home for
sparse tensor related transformation.

NOTE: the actual replacement with sparse tensor types (and removal of linalg glue/clutter)
will follow but I am trying to keep the amount of changes per revision manageable.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D101488
The file was removedmlir/lib/Dialect/Linalg/Transforms/SparseLowering.cpp
The file was addedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/CMakeLists.txt
The file was addedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
The file was removedmlir/test/Integration/Sparse/CPU/sparse_matvec.mlir
The file was modifiedmlir/test/mlir-opt/commandline.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was addedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorLowering.cpp
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/frostt-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_1d.mlir
The file was removedmlir/test/Integration/Sparse/CPU/sparse_sampled_matmul.mlir
The file was removedmlir/include/mlir/Dialect/Linalg/IR/LinalgSparseOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was modifiedmlir/test/lib/Transforms/TestSparsification.cpp
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
The file was addedmlir/test/Dialect/SparseTensor/lowering.mlir
The file was addedmlir/include/mlir/Dialect/SparseTensor/Transforms/Transforms.h
The file was removedmlir/test/Integration/Sparse/CPU/frostt-example.mlir
The file was removedmlir/test/Integration/Sparse/CPU/sparse_sum.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_nd.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
The file was addedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was addedmlir/lib/Dialect/SparseTensor/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/matrix-market-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_3d.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was removedmlir/test/Dialect/Linalg/sparse_roundtrip.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/include/mlir/InitAllDialects.h
The file was modifiedmlir/test/Dialect/Linalg/sparse_lower.mlir
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
The file was removedmlir/test/Dialect/Linalg/sparse_lower_calls.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg
The file was addedmlir/include/mlir/Dialect/SparseTensor/CMakeLists.txt
The file was addedmlir/lib/Dialect/SparseTensor/CMakeLists.txt
The file was removedmlir/test/Integration/Sparse/CPU/matrix-market-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_vector.mlir
The file was removedmlir/test/Integration/Sparse/CPU/lit.local.cfg
Commit 7e115da5df47dbbbef141987845c1258f0c52874 by jezng
[lld-macho] Make everything PIE by default

Modern versions of macOS (>= 10.7) and in general all modern Mach-O
target archs want PIEs by default. ld64 defaults to PIE for iOS >= 4.3,
as well as for all versions of watchOS and simulators. Basically all the
platforms LLD is likely to target want PIE. So instead of cluttering LLD's
code with legacy version checks, I think it's simpler to just default to
PIE for everything.

Note that `-no_pie` still works, so users can still opt out of it.

Reviewed By: #lld-macho, thakis, MaskRay

Differential Revision: https://reviews.llvm.org/D101513
The file was modifiedlld/test/MachO/x86-64-reloc-unsigned.s
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/Driver.cpp
Commit d9c8ffa958b7725e7d3a2231701ab20eb477b9ee by jezng
[lld-macho][nfc] Clean up header.s test

I don't think it's super worthwhile to test the dylib headers outputs of
all the different archs when x86_64 is the only one that has interesting
behavior.

Motivated by my upcoming addition of arm32...
The file was addedlld/test/MachO/arm-relocs.s
The file was modifiedlld/test/MachO/header.s
Commit a64411916cc8b3e87cf767dc24b3bce52af92575 by tmsriram
Basic block sections for functions with implicit-section-name attribute

Functions can have section names set via #pragma or section attributes,
basic block sections should be correctly named for such functions.

With #pragma, the expectation is that all functions in that file are placed
in the same section in the final binary. Basic block sections should be
correctly named with the unique flag set so that the final binary has all the
basic blocks of the function in that named section. This patch fixes the bug
by calling getExplictSectionGlobal when implicit-section-name attribute is set
to make sure the function's basic blocks get the correct section name.

Differential Revision: https://reviews.llvm.org/D101311
The file was addedllvm/test/CodeGen/X86/basic-block-sections-named-section.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was addedllvm/test/CodeGen/X86/basic-block-sections-pragma-sections.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Commit 07884152ec5d2cc112332c5a1ce157968b77a6de by jezng
[lld-macho] Remove stray file
The file was removedlld/test/MachO/arm-relocs.s
Commit 6e859f3cd40946f4d866f18860dc13a6c5f675c9 by a.bataev
Revert "[COST] Improve shuffle kind detection if shuffle mask is provided."

This reverts commit 92399322217917e67c0d72a55ec51ddc82251cf6 to fix
a compiler crash on mask checks.
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/remark_extract_broadcast.ll
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
Commit 12c51f23584252974b63180b7915e6e6f8df87de by a.bataev
[COST] Improve shuffle kind detection if shuffle mask is provided.

Added an extra analysis for better choosing of shuffle kind in
getShuffleCost functions for better cost estimation if mask was
provided.

Differential Revision: https://reviews.llvm.org/D100865
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/remark_extract_broadcast.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
Commit 16d707e656ecd54934afe6c3adb5f710fd6bb36c by jay.foad
[AMDGPU] Fix v_swap_b32 formation on physical registers

As explained in the comments, matchSwap matches:

// mov t, x
// mov x, y
// mov y, t

and turns it into:

// mov t, x (t is potentially dead and move eliminated)
// v_swap_b32 x, y

On physical registers we don't have full use-def chains so the check
for T being live-out was not working properly with subregs/superregs.

Differential Revision: https://reviews.llvm.org/D101546
The file was modifiedllvm/test/CodeGen/AMDGPU/v_swap_b32.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Commit b389c80963fb6276d5df62afe9bd4bd08239887b by benny.kra
[mlir] Fix lowering of multi-dimensional vector log1p to LLVM

This was using the untransformed operand, leading to invalid IR.

Differential Revision: https://reviews.llvm.org/D101531
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
Commit a047837b9063f33617abfa8abe0c408ab522b948 by listmail
Revert "Generalize getInvertibleOperand recurrence handling slightly"

This reverts commit 0c01b37eeb18a51a7e9c9153330d8009de0f600e while a problem reported is investigated.
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/test/Analysis/ValueTracking/known-non-equal.ll
Commit 8f5a2a5836cc8e4c1def2bdeb022e7b496623439 by arnamoy.bhattacharyya
[flang][OpenMP][FIX] Fix the worksharing nesting check with inclusion of more constructs to cover combined constructs.
The file was modifiedflang/test/Semantics/omp-workshare04.f90
The file was modifiedflang/test/Semantics/omp-do05.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/test/Semantics/omp-workshare01.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was modifiedflang/test/Semantics/omp-workshare05.f90
Commit 2b01a417d7ccb001ccc1185ef5fdc967c9fac8d7 by martin
[LLD] [COFF] Fix the mingw --export-all-symbols behaviour with comdat symbols

When looking for the "all" symbols that are supposed to be exported,
we can't look at the live flag - the symbols we mark as to be
exported will become GC roots even if they aren't yet marked as live.

With this in place, building an LLVM library with BUILD_SHARED_LIBS
produces the same set of symbols exported regardless of whether the
--gc-sections flag is specified, both with and without being built
with -ffunction-sections.

Differential Revision: https://reviews.llvm.org/D101522
The file was modifiedlld/COFF/MinGW.cpp
The file was modifiedlld/test/COFF/export-all.s
Commit 37789240882bfacd951767acdb4c088fcbf53385 by martin
[llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets

When looking up data referenced from pdata/xdata structures, the
referenced data can be found in two different ways:
- For an unrelocated object file, it's located via a relocation
- For a relocated, linked image, the data is referenced with an
  (image relative) absolute address

For the latter case, the absolute address can optionally be
described with a symbol.

For the case of an object file, there's two offsets involved; one
immediate offset encoded in the data location that is modified by
the relocation, and a section offset in the symbol.

Previously, for the ExceptionRecord field, we printed the offset
from the symbol (only) but used the immediate offset ignoring
the symbol's address (using only the symbol's section) for printing
the exception data.

Add a helper method for doing the lookup and address calculation,
for simplifying the calling code and making all the cases consistent.

This addresses an existing FIXME comment, fixing printing of the
exception data for cases where relocations point at individual
symbols in the xdata section (which is what MSVC generates) instead of
all relocations pointing at the start of the xdata section (which is
what LLVM generates).

This also fixes printing of the function name for packed entries in
linked images.

Differential Revision: https://reviews.llvm.org/D100305
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
The file was addedllvm/test/tools/llvm-readobj/COFF/arm64-unwind-reference.yaml
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.h
The file was addedllvm/test/tools/llvm-readobj/COFF/arm64-packed-symbol-name.yaml
Commit 086e0f05bfc2f5e24a016a037e01c1fcf8a5146a by joker.eph
Revert "[mlir][sparse] migrate sparse operations into new sparse tensor dialect"

This reverts commit a6d92a971175d727873a9e7644913ee02d7232a8.

The build with -DBUILD_SHARED_LIBS=ON is broken.
The file was modifiedmlir/lib/Dialect/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
The file was modifiedmlir/include/mlir/Dialect/CMakeLists.txt
The file was removedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorLowering.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_3d.mlir
The file was removedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/test/lib/Transforms/TestSparsification.cpp
The file was addedmlir/test/Dialect/Linalg/sparse_lower_calls.mlir
The file was addedmlir/test/Integration/Sparse/CPU/frostt-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_1d.mlir
The file was removedmlir/lib/Dialect/SparseTensor/IR/CMakeLists.txt
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_lower.mlir
The file was removedmlir/test/Dialect/SparseTensor/lowering.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
The file was addedmlir/test/Integration/Sparse/CPU/sparse_sampled_matmul.mlir
The file was modifiedmlir/test/mlir-opt/commandline.mlir
The file was removedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
The file was addedmlir/test/Dialect/Linalg/sparse_roundtrip.mlir
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/frostt-example.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was removedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was removedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/matrix-market-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_vector.mlir
The file was removedmlir/include/mlir/Dialect/SparseTensor/Transforms/Transforms.h
The file was addedmlir/include/mlir/Dialect/Linalg/IR/LinalgSparseOps.td
The file was removedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was removedmlir/include/mlir/Dialect/SparseTensor/IR/CMakeLists.txt
The file was removedmlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg
The file was removedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
The file was removedmlir/lib/Dialect/SparseTensor/CMakeLists.txt
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was addedmlir/lib/Dialect/Linalg/Transforms/SparseLowering.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was addedmlir/test/Integration/Sparse/CPU/sparse_matvec.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
The file was modifiedmlir/test/Dialect/Linalg/sparse_nd.mlir
The file was addedmlir/test/Integration/Sparse/CPU/sparse_sum.mlir
The file was addedmlir/test/Integration/Sparse/CPU/matrix-market-example.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was addedmlir/test/Integration/Sparse/CPU/lit.local.cfg
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
The file was removedmlir/include/mlir/Dialect/SparseTensor/CMakeLists.txt
The file was modifiedmlir/include/mlir/InitAllDialects.h
Commit 96ec6d91e4da6910c7038e02691285978668be10 by Amara Emerson
[AArch64][GlobalISel] Simplify out of range rotate amount.

Differential Revision: https://reviews.llvm.org/D101005
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit 5bf2ef9d869ba882480232a4ed87728af74dac3b by martin
Revert "[llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets"

This reverts commit 37789240882bfacd951767acdb4c088fcbf53385.

The added test fails on at least one buildbot, by printing a reversed
combination, printing "func3_xdata +0x18 (0x8)" while it's supposed to
be "func3_xdata +0x8 (0x18)", see e.g.
https://lab.llvm.org/buildbot/#/builders/107/builds/7269. Currently
no idea how that could happen, but reverting until it can be figured
out.
The file was removedllvm/test/tools/llvm-readobj/COFF/arm64-packed-symbol-name.yaml
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.h
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
The file was removedllvm/test/tools/llvm-readobj/COFF/arm64-unwind-reference.yaml
Commit aaf026d9da3885a951dcdc5edd64c8e7d23b6285 by Lang Hames
[ORC] JITDylib::addDependencies should be run under the session lock.
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
Commit 74d9a76ad3f55c16982ceaa8b6b4a6b7744109b1 by vvereschaka
[CMake] Stop using c++ subdirectory for libc++ on Win to ARM Linux cross builds. NFC

Updated cross Win-x-ARM Linux toolchain cmake cache file in according of
the following changes: https://reviews.llvm.org/D100869

Stop using use c++ subdirectory for libc++ library
The file was modifiedclang/cmake/caches/CrossWinToARMLinux.cmake
Commit fa2340574c5b3208eaa17bf021be92cda7b6d308 by Amara Emerson
[GlobalISel][Legalizer] Bump up a smallvector size that was found to be too small. NFC.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit 3aaac01aab2f2e5c654f73e3424e92c53ba601a4 by zoecarver
[libcxx][ranges] Fix tests for stdlib types that conform to sized_sentinel_for.

Differential Revision: https://reviews.llvm.org/D101371
The file was modifiedlibcxx/test/std/containers/sequences/array/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/strings/string.view/string.view.iterators/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/multiset/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector.bool/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/map/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/multimap/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/set/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/strings/basic.string/string.iterators/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/deque/iterator_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/iterator_concept_conformance.compile.pass.cpp
Commit 6b938d2ead2cb0465436496c0171c7d750e11773 by Alex Lorenz
Recommit "[clang][driver] Use the provided arch name for a Darwin target triple

This ensures that the Darwin driver uses a consistent target triple
representation when the triple is printed out to the user.

This reverts the revert commit ab0df6c0346e515291a381467527621ab0ccf953.

Differential Revision: https://reviews.llvm.org/D100807
The file was modifiedclang/test/Driver/default-toolchain.c
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedclang/test/Driver/openmp-offload-gpu.c
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
The file was modifiedclang/test/Driver/openmp-offload.c
The file was modifiedclang/test/Driver/darwin-version.c
The file was modifiedclang/test/Driver/arm64_32-link.c
Commit 7049fbf960df7ebf77f322a058a3eff9cb4a33cd by jasonliu
[XCOFF] Handle the case when personality routine is an alias

Summary:
Personality routine could be an alias to another personality routine.
Fix the situation when we compile the file that contains the personality
routine and the file also have functions that need to refer to the
personality routine.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D101401
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AIXException.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/Analysis/EHPersonalities.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-personality-alias.ll
Commit be01b091afd820c5784ba960241ea6140529b654 by rob.suderman
[mlir][tosa] Remove constant-0 dim expr values from TOSA lowerings

Constant-0 dim expr values should be avoided for linalg as it can prevent
fusion. This includes adding support for rank-0 reshapes.

Differential Revision: https://reviews.llvm.org/D101418
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
Commit cab48e2f0e00648ef0494ce114f4e00a3ded330f by zequanwu
[CodeGen] don't emit addrsig symbol if it's used only by metadata

Value only used by metadata can be removed from .addrsig table.
This solves the undefined symbol error when enabling addrsig table on COFF LTO.

Differential Revision: https://reviews.llvm.org/D101512
The file was modifiedllvm/include/llvm/IR/Value.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/lib/IR/Value.cpp
The file was modifiedllvm/test/CodeGen/X86/addrsig.ll
Commit 319072f4e3377c4703c25333a321140a6d63c59b by ajcbik
[mlir][sparse] migrate sparse operations into new sparse tensor dialect

This is the very first step toward removing the glue and clutter from linalg and
replace it with proper sparse tensor types. This revision migrates the LinalgSparseOps
into SparseTensorOps of a sparse tensor dialect. This also provides a new home for
sparse tensor related transformation.

NOTE: the actual replacement with sparse tensor types (and removal of linalg glue/clutter)
will follow but I am trying to keep the amount of changes per revision manageable.

Differential Revision: https://reviews.llvm.org/D101573
The file was addedmlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/CMakeLists.txt
The file was modifiedmlir/test/Dialect/Linalg/sparse_1d.mlir
The file was modifiedmlir/test/lib/Transforms/TestSparsification.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was addedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/test/Dialect/Linalg/sparse_3d.mlir
The file was removedmlir/test/Integration/Sparse/CPU/sparse_matvec.mlir
The file was modifiedmlir/include/mlir/Dialect/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
The file was addedmlir/lib/Dialect/SparseTensor/IR/CMakeLists.txt
The file was modifiedmlir/test/mlir-opt/commandline.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was addedmlir/include/mlir/Dialect/SparseTensor/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
The file was removedmlir/test/Integration/Sparse/CPU/sparse_sum.mlir
The file was addedmlir/test/Dialect/SparseTensor/lowering.mlir
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/matrix-market-example.mlir
The file was removedmlir/test/Integration/Sparse/CPU/frostt-example.mlir
The file was removedmlir/test/Integration/Sparse/CPU/matrix-market-example.mlir
The file was removedmlir/test/Dialect/Linalg/sparse_lower_calls.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/include/mlir/InitAllDialects.h
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/frostt-example.mlir
The file was addedmlir/include/mlir/Dialect/SparseTensor/Transforms/Transforms.h
The file was removedmlir/lib/Dialect/Linalg/Transforms/SparseLowering.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was addedmlir/include/mlir/Dialect/SparseTensor/IR/CMakeLists.txt
The file was removedmlir/test/Dialect/Linalg/sparse_roundtrip.mlir
The file was addedmlir/lib/Dialect/SparseTensor/CMakeLists.txt
The file was removedmlir/test/Integration/Sparse/CPU/lit.local.cfg
The file was addedmlir/test/Dialect/SparseTensor/roundtrip.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_lower.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_nd.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_vector.mlir
The file was removedmlir/test/Integration/Sparse/CPU/sparse_sampled_matmul.mlir
The file was removedmlir/include/mlir/Dialect/Linalg/IR/LinalgSparseOps.td
The file was addedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorLowering.cpp
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg
The file was addedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
Commit 6b30240288fc6c0871ea92fcf77c944b0bdd43ad by zequanwu
Reland "[lld-link] Enable addrsig table in COFF lto"

This reverts commit a78fa73bcf986cf5912d665ecd9620535f480607.

The commit cab48e2f0e00648ef0494ce114f4e00a3ded330f fixes the issue on eabd55b1b2c5e322c3b36cb44348f178692890c8.
The file was modifiedlld/COFF/LTO.cpp
Commit 2e1d9ebd46b826b06f0a5882e992e3d84335f268 by Akira
[ObjC][ARC] Don't enter the cleanup scope if the initializer expression
isn't an ExprWithCleanups

This patch fixes a bug where a temporary ObjC pointer is released before
the end of the full expression.

This fixes PR50043.

rdar://77030453

Differential Revision: https://reviews.llvm.org/D101502
The file was modifiedclang/test/CodeGenObjCXX/arc.mm
The file was modifiedclang/lib/CodeGen/CGDecl.cpp
The file was modifiedclang/test/CodeGenObjCXX/arc-blocks.mm
Commit 75be3681d1a98e57f3e7d45343b8fd0a8286b56b by jianzhouzh
[msan] Remove dead function/fields

To see how to extract a shared allocator interface for D101204,
found some unused code. Tests passed. Are they safe to remove?

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D101559
The file was modifiedcompiler-rt/lib/memprof/memprof_allocator.h
The file was modifiedcompiler-rt/lib/msan/msan_allocator.h
The file was modifiedcompiler-rt/lib/msan/msan.h
Commit 809435e390e91355f64bee0142a65c4fe6e9f488 by Akira
[Sema] Don't set BlockDecl's DoesNotEscape bit if the parameter type of
the function the block is passed to isn't a block pointer type

This patch fixes a bug where a block passed to a function taking a
parameter that doesn't have a block pointer type (e.g., id or reference
to a block pointer) was marked as noescape.

This partially fixes PR50043.

rdar://77030453

Differential Revision: https://reviews.llvm.org/D101097
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/SemaObjCXX/noescape.mm
Commit 749702fc6ba268cb0096c09393db51a20bb5eb0d by carl.ritson
[AMDGPU] Remove dead early-out in GCNHazardRecognizer

Remove an early-out in wait state counting which can never be
taken.

Reviewed By: foad, rampitec

Differential Revision: https://reviews.llvm.org/D101520
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Commit 424f1f6f96d0e0f14d25b0d1f3e85b85aa6a8249 by carl.ritson
[AMDGPU][NFC] Refactor hazard recognition IsHazardFn and IsExpiredFn

Refactor IsHazardFn and IsExpiredFn to use constant references as these should not be mutating the instructions visited and the instruction can never be null.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D101430
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Commit e6701e575cfd035d808edf2752881c4b6bba77d1 by Matthew.Arsenault
AMDGPU: Add missing runline to test

There are checks for gfx908, but this wasn't actually running with it.
The file was modifiedllvm/test/CodeGen/AMDGPU/agpr-csr.ll
Commit 1cf3d68f9731199b3f753c5a87826c40a4d2168b by Matthew.Arsenault
VirtRegMap: Add pass option to not clear virt regs

In a future change it will be possible to run register
allocation with a specific set of register classes,
so some of the remaining virtual registers will still
be meaningful.
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/lib/CodeGen/VirtRegMap.cpp
Commit 1141ba677e09156daec8ef31d3dcdae7f59f60c5 by walter erquinigo
[lldb-vscode] Follow up of D99989 - store some strings more safely

As a follow up of https://reviews.llvm.org/D99989#inline-953343, I'm now
storing std::string instead of char *. I know it might never break as char *,
but if it does, chasing that bug might be dauting.
Besides, I'm also checking of the strings gotten through the SB API are
null or not.
The file was modifiedlldb/tools/lldb-vscode/JSONUtils.h
The file was modifiedlldb/tools/lldb-vscode/JSONUtils.cpp
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
Commit 55a29c6b71c9b80353ccb17c0dd15dde5c9940b3 by Matthew.Arsenault
VirtRegMap: Support partially allocated virtual registers

Don't assert if there are unassigned virtual registers.  Maintain
LiveIntervals by removing the RegUnits for allocated registers, since
they should not longer be necessary.

One part I find somewhat questionable is the special handling
necessary for handleIdentityCopy. The LiveIntervals for the relevant
regunits needs to be removed.
The file was modifiedllvm/lib/CodeGen/VirtRegMap.cpp
Commit d7d85f72ef9b45b45472611196f6b97305832b9a by brendon.cahoon
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX

When creating G_SBFX/G_UBFX opcodes, the last operand is the
width instead of the bit position. The bit position is used
for the AArch64 SBFM and UBFM instructions. The bit position
is converted to a width if the SBFX/UBFX aliases are generated.
For other SBMF/UBFM aliases, such as shifts, the bit position
is used.

Differential Revision: https://reviews.llvm.org/D101543
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
Commit e0c7db7d8ce780df5129b4d0f5bbf145271ef14f by pengfei.wang
[MS] Preserve base register %rbx around cpuid

This patch copies implementation from cpuid.h, which preserve base register %rbx around cpuid. It fixes PR50133.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D101338
The file was modifiedclang/test/CodeGen/ms-intrinsics-cpuid.c
The file was modifiedclang/lib/Headers/intrin.h
Commit 7259394b32d96bf981a1d9972514e98d3ac0b1da by Steven Wu
[CMake][compiler-rt] avoid conflict with builtin check_linker_flag

Rename `check_linker_flag` in compiler_rt to avoid conflict. Follow up
as the fix in D100901.

Patched by radford.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D101581
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit 325b454ed8d8165fe63c03883ce7a3de0ec990c9 by 932494295
[RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed

Differential Revision: https://reviews.llvm.org/D100284
The file was modifiedllvm/test/CodeGen/RISCV/rvv/localvar.ll
Commit 5603ed60ad6cd6370010e0746faef9f823c1fa72 by 932494295
[RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed

When rvv vector objects existed, using sp to access the fixed stack object will pass the rvv vector objects field. So the StackOffset needs add a scalable offset of the size of rvv vector objects field

Differential Revision: https://reviews.llvm.org/D100286
The file was modifiedllvm/test/CodeGen/RISCV/rvv/localvar.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Commit 544be708641b2f3d58a1b86ae86c3ba460f41d10 by Christudasan.Devadasan
[AMDGPU] Skip promote-alloca for insertelement/insertvalue users

It is difficult to track the users of vector and aggregate types.

Reviewed by: arsenm

Differential Revision: https://reviews.llvm.org/D101562
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
The file was addedllvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
Commit a3a798d49dfcc30fbe26bb865ac30ccda216c4a7 by aeubanks
[InlineCost] Remove visitUnaryInstruction()

The simplifyInstruction() in visitUnaryInstruction() does not trigger
for all of check-llvm. Looking at all delegates to UnaryInstruction in
InstVisitor, the only instructions that either don't have a visitor in
CallAnalyzer, or redirect to UnaryInstruction, are VAArgInst and Alloca.
VAArgInst will never get simplified, and visitUnaryInstruction(Alloca)
would always return false anyway.

Reviewed By: mtrofin, lebedev.ri

Differential Revision: https://reviews.llvm.org/D101577
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit bd48def3e2203e534f8f7345664a35f08f1d9c32 by qiucofan
Pre-commit test for PPC vector extraction test
The file was modifiedllvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_extract_p9.ll