SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Bumped urllib3 from 1.26.3 to 1.26.4. (details)
  2. Added enable_runtimes and enable_projects to LLVMBuildFactory. (details)
  3. Added support for LLVM_ENABLE_RUNTIMES to UnifiedTreeBuilder. (details)
  4. Documentation builds do not support LLVM_ENABLE_RUNTIMES. (details)
  5. Added support for LLVM_ENABLE_RUNTIMES to ClangLTOBuilder. (details)
  6. Changed LibcxxAndAbiBuilder to use LLVMBuildFactory enable_projects and enable_runtimes. (details)
Commit de05587afe1c1f79810a27ad77e39c485995dd98 by gkistanova
Bumped urllib3 from 1.26.3 to 1.26.4.
The file was modifiedrequirements.txt
Commit 2ed0c6ae25a4da897f23770f9a4976c3e19fff10 by gkistanova
Added enable_runtimes and enable_projects to LLVMBuildFactory.
The file was modifiedzorg/buildbot/process/factory.py
Commit 90c0b74c2ee54639b417bbda061c45ba8967ed9f by gkistanova
Added support for LLVM_ENABLE_RUNTIMES to UnifiedTreeBuilder.
The file was modifiedzorg/buildbot/builders/UnifiedTreeBuilder.py
Commit 4762fe8e3c66b6ca574eb0b5f2cbe99db079e6c7 by gkistanova
Documentation builds do not support LLVM_ENABLE_RUNTIMES.
The file was modifiedzorg/buildbot/builders/DoxygenDocsBuilder.py
The file was modifiedzorg/buildbot/builders/SphinxDocsBuilder.py
Commit 1a77335dfe7cff35bc736523ae7d9f801a470739 by gkistanova
Added support for LLVM_ENABLE_RUNTIMES to ClangLTOBuilder.
The file was modifiedzorg/buildbot/builders/ClangLTOBuilder.py
Commit a138f265e7a4fd9a6bf7288ca50361b4d7c0860f by gkistanova
Changed LibcxxAndAbiBuilder to use LLVMBuildFactory enable_projects and enable_runtimes.
The file was modifiedzorg/buildbot/builders/LibcxxAndAbiBuilder.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [msan] Add static to some msan allocator functions (details)
  2. [debugserver] Use add_lldb_library instead of add_library (details)
  3. tsan: refactor fork handling (details)
  4. Reapply [llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets (details)
  5. Fix -fdebug-pass-structure test case (details)
  6. [cmake] Use -ffunction-sections and -Wl,--gc-sections on MinGW targets (details)
  7. [AMDGPU] Simplify getWaitStatesSince. NFC. (details)
  8. [GISel] Teach TableGen to check predicates of immediate operands in patterns (details)
  9. tsan: fix fork syscall test (details)
  10. [llvm][Support][NFC] Fix fallthrough attribute indentation (details)
  11. [RISCV] Support STEP_VECTOR with a step greater than one (details)
  12. [RISCV][NFC] Merge RV32/RV64 test checks with a common prefix (details)
  13. [lldb] Add tests for DumpDataExtractor formats (details)
  14. [AArch64] Change __ARM_FEATURE_FP16FML macro name to  __ARM_FEATURE_FP16_FML (details)
  15. [JITLink] Minor fix to avoid Windows compiler warning for static-cast (details)
  16. [AMDGPU] Tidy up some simple expressions for clarity NFC (details)
  17. Wrap edit line configuration calls into helper functions (details)
  18. [InlineCost] CallAnalyzer: use TTI info for extractvalue - they are free (PR50099) (details)
  19. [AArch64][SVE] Lower index_vector to step_vector (details)
  20. [Passes] Run sinking/hoisting in SimplifyCFG earlier. (details)
  21. [Doc] Fix sphinx warnings about wrong code-block format (details)
  22. [NARY] Don't optimize min/max if there are side uses (part2) (details)
  23. clang-format: [JS] handle "off" in imports (details)
  24. Require shell for lld/test/MachO/reproduce.s (details)
  25. [clangd][NFC] Remove unnecessary string captures in lambdas. (details)
  26. [ARM][MVE] vcreateq lane ordering for big endian (details)
  27. [libc++] Minor cleanups in <iterator>. NFCI. (details)
  28. [libc++] [test] Run the clang-format and generated-output checks on the "service" queue (details)
  29. [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks (details)
  30. [clang] Refactor mustprogress handling, add it to all loops in c++11+. (details)
  31. [MCA] Fix CarryOver check in the DispatchStage (PR50174). (details)
  32. [lld/mac] Tweak two comments and fix style on one variable name (details)
  33. [docs]Added llvm/bindings section (details)
  34. [lld/mac] Remove unused -L%t flags from tests (details)
  35. [OpenCL] Prevent adding vendor extensions for all targets (details)
  36. [AMDGPU] Add implicit negative check for the set_gpr_idx tests (details)
  37. [VP,Integer,#2] ExpandVectorPredication pass (details)
  38. [VE] VP intrinsics are legal (details)
  39. [gn build] Port 43bc584dc05e (details)
  40. sanitizer_common: introduce kInvalidTid/kMainTid (details)
  41. [AMDGPU] Add test for set_gpr_idx removal with conditional branches (details)
  42. [clang] Fix assert() crash when checking undeduced arg alignment (details)
  43. [XCOFF][AIX] Add Global Variables Directly to TOC for 32 bit AIX (details)
  44. [PowerPC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns. (details)
  45. [SimpleLoopUnswitch] Port partially invariant unswitch from LoopUnswitch to SimpleLoopUnswitch (details)
  46. [lldb] More tests for DumpDataExtractor (details)
  47. AMDGPU/llvm-readobj: Add missing tests for note parsing/displaying (details)
  48. [TableGen] Fix two bugs in 'defm' when complex 'assert' is involved. (details)
  49. [CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0 (details)
  50. [lldb] DumpDataExtractor tests for item byte size errors (details)
  51. Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0" (details)
  52. [lldb] Change DumpDataExtractorTest function names to lldb style (NFC) (details)
  53. [AArch64][SVE] Remove unused function missed from D101302 (details)
  54. [analyzer] Fix assertion in SVals.h (details)
Commit c027272ac260785849ae8afbb26742d5b7499ae5 by jianzhouzh
[msan] Add static to some msan allocator functions

This is to help review refactor the allocator code.
So it is easy to see which are the real public interfaces.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D101586
The file was modifiedcompiler-rt/lib/msan/msan_allocator.cpp
Commit b535459d0a1db37fca6688b8e15305e361debff5 by Jonas Devlieghere
[debugserver] Use add_lldb_library instead of add_library

Use add_lldb_library to ensure debugserver inherits the defines set by
llvm and lldb.

Differential revision: https://reviews.llvm.org/D101596
The file was modifiedlldb/tools/debugserver/source/CMakeLists.txt
Commit ed7bf7d73fa253c770c0e715db5262f359268c3a by dvyukov
tsan: refactor fork handling

Commit efd254b6362 ("tsan: fix deadlock in pthread_atfork callbacks")
fixed another deadlock related to atfork handling.
But builders with DCHECKs enabled reported failures of
pthread_atfork_deadlock2.c and pthread_atfork_deadlock3.c tests
related to the fact that we hold runtime locks on interceptor exit:
https://lab.llvm.org/buildbot/#/builders/70/builds/6727
This issue is somewhat inherent to the current approach,
we indeed execute user code (atfork callbacks) with runtime lock held.

Refactor fork handling to not run user code (atfork callbacks)
with runtime locks held. This change does this by installing
own atfork callbacks during runtime initialization.
Atfork callbacks run in LIFO order, so the expectation is that
our callbacks run last, right before the actual fork.
This way we lock runtime mutexes around fork, but not around
user callbacks.

Extend tests to also install after fork callbacks just to cover
more scenarios. Some tests also started reporting real races
that we previously suppressed.

Also extend tests to cover fork syscall support.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D101517
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was addedcompiler-rt/test/tsan/Linux/fork_syscall.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
The file was modifiedcompiler-rt/test/tsan/pthread_atfork_deadlock.c
The file was addedcompiler-rt/test/tsan/pthread_atfork_deadlock3.c
The file was modifiedcompiler-rt/test/tsan/pthread_atfork_deadlock2.c
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_mman.cpp
Commit 4750a8b1bcded31ba15d21b14530882092a9d5cc by martin
Reapply [llvm-readobj] [ARMWinEH] Fix handling of relocations and symbol offsets

When looking up data referenced from pdata/xdata structures, the
referenced data can be found in two different ways:
- For an unrelocated object file, it's located via a relocation
- For a relocated, linked image, the data is referenced with an
  (image relative) absolute address

For the latter case, the absolute address can optionally be
described with a symbol.

For the case of an object file, there's two offsets involved; one
immediate offset encoded in the data location that is modified by
the relocation, and a section offset in the symbol.

Previously, for the ExceptionRecord field, we printed the offset
from the symbol (only) but used the immediate offset ignoring
the symbol's address (using only the symbol's section) for printing
the exception data.

Add a helper method for doing the lookup and address calculation,
for simplifying the calling code and making all the cases consistent.

This addresses an existing FIXME comment, fixing printing of the
exception data for cases where relocations point at individual
symbols in the xdata section (which is what MSVC generates) instead of
all relocations pointing at the start of the xdata section (which is
what LLVM generates).

This also fixes printing of the function name for packed entries in
linked images.

Relanded with a format string fix in the formatSymbol function; one
can't use %X as format string for an uint64_t. That bug has been
present since this code was added in e6971cab306cd.

Differential Revision: https://reviews.llvm.org/D100305
The file was addedllvm/test/tools/llvm-readobj/COFF/arm64-packed-symbol-name.yaml
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.h
The file was addedllvm/test/tools/llvm-readobj/COFF/arm64-unwind-reference.yaml
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
Commit c81ec19fba27ec308607aac2e44234eee8e190d1 by eleviant
Fix -fdebug-pass-structure test case

Pass structure can change when -O0 is given and extensions are used.
The file was modifiedclang/test/Driver/debug-pass-structure.c
Commit b11a2f2544e880602b539c85c4445468d14b63a1 by martin
[cmake] Use -ffunction-sections and -Wl,--gc-sections on MinGW targets

If compiling with GCC or linking with ld.bfd, these options have little
effect, but if built with Clang and linked with LLD, they provide a
quite notable size decrease - this shrinks an entire llvm-mingw
distribution package by 22%.

If building with BUILD_SHARED_LIBS or LLVM_BUILD_LLVM_DYLIB with LLD,
this requires a version of LLD that contains a fix for auto exporting
symbols from comdats, 2b01a417d7ccb001ccc1185ef5fdc967c9fac8d7.

Differential Revision: https://reviews.llvm.org/D101568
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit f251379a91d3731be079b701fda0d3551bb22b4e by jay.foad
[AMDGPU] Simplify getWaitStatesSince. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Commit 97ed1b6036074e66dd926b6720f087b9964a7286 by dominik.montada
[GISel] Teach TableGen to check predicates of immediate operands in patterns

Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D91703
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was addedllvm/test/TableGen/immarg-predicated.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
Commit b6df85290118d17c1dddf412a1a44a83158133e3 by dvyukov
tsan: fix fork syscall test

Arm64 builders failed with:
error: use of undeclared identifier 'SYS_fork'
https://lab.llvm.org/buildbot/#/builders/7/builds/2575

Indeed, not all arches have fork syscall.
Implement fork via clone on these arches.

Differential Revision: https://reviews.llvm.org/D101603
The file was modifiedcompiler-rt/test/tsan/Linux/fork_syscall.cpp
Commit 95157860aeecde33da8dc75c67823ac9ea9c58ff by tbaeder
[llvm][Support][NFC] Fix fallthrough attribute indentation

The attribute does not belong to the if statement before and trips up
gcc's indentation checker.
The file was modifiedllvm/lib/Support/GraphWriter.cpp
Commit 791766e6d2e14f437a0b765cb7133c1509ac378e by fraser
[RISCV] Support STEP_VECTOR with a step greater than one

DAGCombiner was recently taught how to combine STEP_VECTOR nodes,
meaning the step value is no longer guaranteed to be one by the time it
reaches the backend for lowering.

This patch supports such cases on RISC-V by lowering to other step
values to a multiply following the vid.v instruction. It includes a
small optimization for common cases where the multiply can be expressed
as a shift left.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D100856
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 1d85b247628521f52a9cb8c9a7ccd3ea480a88ec by fraser
[RISCV][NFC] Merge RV32/RV64 test checks with a common prefix
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
Commit 8fdfc1d64c51d949b84b2ee824f2ba9b9a3a6bd6 by david.spickett
[lldb] Add tests for DumpDataExtractor formats

Covering basic cases where you have 1 item on 1 line.

Apart from eFormatCharArray, where using multiple lines
highlights the difference between it and eFormatVectorOfChar.

Reviewed By: #lldb, teemperor

Differential Revision: https://reviews.llvm.org/D101453
The file was addedlldb/unittests/Core/DumpDataExtractorTest.cpp
The file was modifiedlldb/unittests/Core/CMakeLists.txt
Commit 109bf25e2c425ea5dd20836f25176cf9d9479016 by keith.walker
[AArch64] Change __ARM_FEATURE_FP16FML macro name to  __ARM_FEATURE_FP16_FML

The "Arm C Language extensions" document (the current version can be
found at https://developer.arm.com/documentation/101028/0012/?lang=en)
states that the name of the feature test macro for the FP16 FML extension
is __ARM_FEATURE_FP16_FML.

Differential Revision: https://reviews.llvm.org/D101532
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
The file was modifiedclang/include/clang/Basic/arm_neon.td
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
Commit 417b1164c28ef526cfe3ccab70d22598b7c63624 by david.stuttard
[JITLink] Minor fix to avoid Windows compiler warning for static-cast

Change-Id: Id0c1d5535b53e2aebe314151c0efa585e763f3f6

Differential Revision: https://reviews.llvm.org/D100093
The file was modifiedllvm/lib/ExecutionEngine/JITLink/x86_64.cpp
Commit a67a377014ceaaed55b2ba2259e080bc3fc42b43 by david.stuttard
[AMDGPU] Tidy up some simple expressions for clarity NFC

Slight refactor for clarity.

Change-Id: Ib25e7f4582c67a7c57f066cfd5382c1405d7d4c5

Differential Revision: https://reviews.llvm.org/D101610
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit fd89af6880f33ead708abe2f7d88ecb687d4e0d2 by Raphael Isemann
Wrap edit line configuration calls into helper functions

Currently we call el_set directly to configure the editor in the libedit
wrapper.  There are some cases in which this causes extra casting, but we pass
captureless lambdas as function pointers, which should work out of the box.
Since el_set takes varargs, if the cast is incorrect or if the cast is not
present, it causes a run time failure rather than compile error.  This change
makes it so a few different types of configuration is done inside a helper
function to provide type safety and eliminate that casting.  I didn't do all
edit line configuration because I'm not sure how important it was in other cases
and it might require something more general keep up with libedit's signature.
I'm open to suggestions, though.

Reviewed By: teemperor, JDevlieghere

Differential Revision: https://reviews.llvm.org/D101250
The file was modifiedlldb/include/lldb/Host/Editline.h
The file was modifiedlldb/source/Host/common/Editline.cpp
Commit ba5b015b0de13b412d73d127ca181115c5e78717 by lebedev.ri
[InlineCost] CallAnalyzer: use TTI info for extractvalue - they are free (PR50099)

It seems incorrect to use TTI data in some places,
and override it in others. In this case, TTI says
that `extractvalue` are free, yet we bill them.

While this doesn't address https://bugs.llvm.org/show_bug.cgi?id=50099 yet,
it reduces the cost from 55 to 50 while the threshold is 45.

Differential Revision: https://reviews.llvm.org/D101228
The file was modifiedllvm/test/Transforms/Inline/X86/extractvalue.ll
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit b310dd15017f9aecd1ecc84b896d346075282a34 by JunMa
[AArch64][SVE] Lower index_vector to step_vector

As discussed in D100107, this patch first convert index_vector to
step_vector, and convert step_vector back to index_vector after LegalizeDAG.

Differential Revision: https://reviews.llvm.org/D100816
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
Commit ed9df5bd2f50b2199204cc6e50910ba52dd5e93e by flo
[Passes] Run sinking/hoisting in SimplifyCFG earlier.

Hoisting and sinking instructions out of conditional blocks enables
additional vectorization by:

1. Executing memory accesses unconditionally.
2. Reducing the number of instructions that need predication.

After disabling early hoisting / sinking, we miss out on a few
vectorization opportunities. One of those is causing a ~10% performance
regression in one of the Geekbench benchmarks on AArch64.

This patch tires to recover the regression by running hoisting/sinking
as part of a SimplifyCFG run after LoopRotate and before LoopVectorize.

Note that in the legacy pass-manager, we run LoopRotate just before
vectorization again and there's no SimplifyCFG run in between, so the
sinking/hoisting may impact the later run on LoopRotate. But the impact
should be limited and the benefit of hosting/sinking at this stage
should outweigh the risk of not rotating.

Compile-time impact looks slightly positive for most cases.
http://llvm-compile-time-tracker.com/compare.php?from=2ea7fb7b1c045a7d60fcccf3df3ebb26aa3699e5&to=e58b4a763c691da651f25996aad619cb3d946faf&stat=instructions

NewPM-O3: geomean -0.19%
NewPM-ReleaseThinLTO: geoman -0.54%
NewPM-ReleaseLTO-g: geomean -0.03%

With a few benchmarks seeing a notable increase, but also some
improvements.

Alternative to D101290.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D101468
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
The file was modifiedllvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll
The file was modifiedllvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_use.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Transforms/PGOProfile/thinlto_cspgo_use.ll
Commit 76f84e772978a3daef33df5bea7da676a0163f28 by alexey.bader
[Doc] Fix sphinx warnings about wrong code-block format

Differential Revision: https://reviews.llvm.org/D101549
The file was modifiedclang/docs/SYCLSupport.rst
Commit 7861cb600cd6f1905df3d1055ea910a07e2c3c4f by ybrevnov
[NARY] Don't optimize min/max if there are side uses (part2)

Previous attempt to fix infinite recursion in min/max reassociation was not fully successful (D100170). Newly discovered failing case is due to not properly handled when there is a single use. It should be processed separately from 2 uses case.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D101359
The file was modifiedllvm/lib/Transforms/Scalar/NaryReassociate.cpp
The file was modifiedllvm/test/Transforms/NaryReassociate/nary-req.ll
Commit b2780cd744eaad6f5c7f39165054cf7000a1ff07 by martin
clang-format: [JS] handle "off" in imports

Previously, the JavaScript import sorter would ignore `// clang-format
off` and `on` comments. This change fixes that. It tracks whether
formatting is enabled for a stretch of imports, and then only sorts and
merges the imports where formatting is enabled, in individual chunks.

This means that there's no meaningful total order when module references are mixed
with blocks that have formatting disabled. The alternative approach
would have been to sort all imports that have formatting enabled in one
group. However that raises the question where to insert the
formatting-off block, which can also impact symbol visibility (in
particular for exports). In practice, sorting in chunks probably isn't a
big problem.

This change also simplifies the general algorithm: instead of tracking
indices separately and sorting them, it just sorts the vector of module
references. And instead of attempting to do fine grained tracking of
whether the code changed order, it just prints out the module references
text, and compares that to the previous text. Given that source files
typically have dozens, but not even hundreds of imports, the performance
impact seems negligible.

Differential Revision: https://reviews.llvm.org/D101515
The file was modifiedclang/unittests/Format/SortImportsTestJS.cpp
The file was modifiedclang/lib/Format/SortJavaScriptImports.cpp
Commit cbe62f2f2f1e7e514fdf10d9bfc604921e7eba89 by hans
Require shell for lld/test/MachO/reproduce.s

as a way of not running it on Windows, where the file paths when
extracting repro2.tar can become longer than the maximum file length
limit (depending on the build dir name) and cause the test to fail.

(See https://crbug.com/1204463 for example test failure.)
The file was modifiedlld/test/MachO/reproduce.s
Commit 6815037085945be8bb758c23b1a5daabe0a8667d by n.james93
[clangd][NFC] Remove unnecessary string captures in lambdas.

Due to a somewhat annoying, but necessary, shortfall in -Wunused-lambda-capture, These unused captures aren't warned about.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D101611
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
Commit b14a6f06cc8763830a25023edf5b9ccee18e426a by tomas.matheson
[ARM][MVE] vcreateq lane ordering for big endian

Use of bitcast resulted in lanes being swapped for vcreateq with big
endian. Fix this by using vreinterpret. No code change for little
endian. Adds IR lit test.

Differential Revision: https://reviews.llvm.org/D101606
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/admin.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit 5f51fb3421e0254f6d88673b61053bd485c13a41 by arthur.j.odwyer
[libc++] Minor cleanups in <iterator>. NFCI.
The file was modifiedlibcxx/include/iterator
Commit 6712534ebc6f84f0b178a19bf17b7b2bd852f6eb by arthur.j.odwyer
[libc++] [test] Run the clang-format and generated-output checks on the "service" queue

As these jobs only run in a couple seconds, and block starting of
other jobs, they can run on the "service" queue which doesn't get
blocked by other long-running jobs.

Differential Revision: https://reviews.llvm.org/D101437
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 66b8a16cc07c20f97f21c61d880f7924d47e597b by jay.foad
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks

In some cases the lack of --- or ... confused update_mir_test_checks.py
into not adding any checks for a function.
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
Commit 6c3129549374c0e81e28fd0a21e96f8087b63a78 by flo
[clang] Refactor mustprogress handling, add it to all loops in c++11+.

Currently Clang does not add mustprogress to inifinite loops with a
known constant condition, matching C11 behavior. The forward progress
guarantee in C++11 and later should allow us to add mustprogress to any
loop (http://eel.is/c++draft/intro.progress#1).

This allows us to simplify the code dealing with adding mustprogress a
bit.

Reviewed By: aaron.ballman, lebedev.ri

Differential Revision: https://reviews.llvm.org/D96418
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/test/CodeGenCXX/attr-mustprogress.cpp
The file was modifiedclang/lib/CodeGen/CGStmt.cpp
The file was modifiedclang/test/CodeGen/attr-mustprogress.c
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
Commit 8bd4f3d5474b3a97933476fb6646496d4c525468 by andrea.dibiagio
[MCA] Fix CarryOver check in the DispatchStage (PR50174).

Early exit from method DispatchStage::isAvailable() if the dispatch group is
already full. Not all instructions declare at least one uOP.
Fixes PR50174.
The file was addedllvm/test/tools/llvm-mca/ARM/cortex-a57-carryover.s
The file was modifiedllvm/lib/MCA/Stages/DispatchStage.cpp
Commit 4b456038e4372b7f5199ffcfaaae11364b73837d by thakis
[lld/mac] Tweak two comments and fix style on one variable name

Cosmetic, no behavior change.
The file was modifiedlld/MachO/InputFiles.cpp
Commit cfb95f6f916dfd518e89c545e2988e2c7bc56fd3 by shivam98.tkg
[docs]Added llvm/bindings section

Added information about language bindings provided by LLVM.

Reviewed By: xgupta, gandhi21299

Differential Revision: https://reviews.llvm.org/D101295
The file was modifiedllvm/docs/GettingStarted.rst
Commit a1a2a8e8acef1061215d1baa442755b472cc1448 by thakis
[lld/mac] Remove unused -L%t flags from tests

No behavior change.

Differential Revision: https://reviews.llvm.org/D101623
The file was modifiedlld/test/MachO/weak-definition-order.s
The file was modifiedlld/test/MachO/weak-definition-direct-fetch.s
The file was modifiedlld/test/MachO/weak-definition-indirect-fetch.s
Commit 3ec82e519513b231bb0e8dd5e098c4c5a51501a2 by anastasia.stulova
[OpenCL] Prevent adding vendor extensions for all targets

Removed extension begin/end pragma as it has no effect and
it is added unconditionally for all targets.

Differential Revision: https://reviews.llvm.org/D92244
The file was modifiedclang/lib/Headers/opencl-c-base.h
The file was modifiedclang/test/Headers/opencl-c-header.cl
The file was modifiedclang/lib/Headers/opencl-c.h
Commit 181c492ee72c2234e50a60dda467a587f1e8dc08 by jay.foad
[AMDGPU] Add implicit negative check for the set_gpr_idx tests

The only effect of the optimization is to remove s_set_gpr_idx_*
instructions, and update_mir_test_checks.py always inserts CHECK: rather
than CHECK-NEXT: checks, so without this implicit negative check, the
tests would always pass even if the optimization did nothing.

Differential Revision: https://reviews.llvm.org/D101622
The file was modifiedllvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
Commit 43bc584dc05e24c6d44ece8e07d4bff585adaf6d by simon.moll
[VP,Integer,#2] ExpandVectorPredication pass

This patch implements expansion of llvm.vp.* intrinsics
(https://llvm.org/docs/LangRef.html#vector-predication-intrinsics).

VP expansion is required for targets that do not implement VP code
generation. Since expansion is controllable with TTI, targets can switch
on the VP intrinsics they do support in their backend offering a smooth
transition strategy for VP code generation (VE, RISC-V V, ARM SVE,
AVX512, ..).

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D78203
The file was addedllvm/test/CodeGen/Generic/expand-vp.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/tools/llc/llc.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicInst.h
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/lib/CodeGen/ExpandVectorPredication.cpp
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
The file was modifiedllvm/include/llvm/LinkAllPasses.h
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was addedllvm/include/llvm/CodeGen/ExpandVectorPredication.h
The file was modifiedllvm/include/llvm/CodeGen/MachinePassRegistry.def
The file was modifiedllvm/lib/IR/IntrinsicInst.cpp
Commit 7a8664561116cd3c1ce2e66826c479649ae741b9 by simon.moll
[VE] VP intrinsics are legal
The file was modifiedllvm/lib/Target/VE/VETargetTransformInfo.h
Commit 4978bf65adbcd1674cec33c49d646d55694b03ef by llvmgnsyncbot
[gn build] Port 43bc584dc05e
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit 92a3a2dc3eb69ff4f20ec27f68d9923cf3201bf3 by dvyukov
sanitizer_common: introduce kInvalidTid/kMainTid

Currently we have a bit of a mess related to tids:
- sanitizers re-declare kInvalidTid multiple times
- some call it kUnknownTid
- implicit assumptions that main tid is 0
- asan/memprof claim their tids need to fit into 24 bits,
   but this does not seem to be true anymore
- inconsistent use of u32/int to store tids

Introduce kInvalidTid/kMainTid in sanitizer_common
and use them consistently.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D101428
The file was modifiedcompiler-rt/lib/asan/asan_thread.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_registry.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_clock.h
The file was modifiedcompiler-rt/lib/asan/asan_descriptions.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_thread.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_posix.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_common.h
The file was modifiedcompiler-rt/lib/asan/asan_thread.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_descriptions.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
The file was modifiedcompiler-rt/lib/lsan/lsan_interceptors.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_thread.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_defs.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_thread_registry_test.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_sync.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_report.cpp
The file was modifiedcompiler-rt/lib/asan/asan_allocator.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_registry.h
The file was modifiedcompiler-rt/lib/lsan/lsan_thread.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
Commit e2a2df2a1e96a523dd7c0f8fb1eb5935aa6b4d09 by jay.foad
[AMDGPU] Add test for set_gpr_idx removal with conditional branches
The file was modifiedllvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
Commit fbfcfdbf6828b8d36f4ec0ff5f4eac11fb1411a5 by adamcz
[clang] Fix assert() crash when checking undeduced arg alignment

There already was a check for undeduced and incomplete types, but it
failed to trigger when outer type (SubstTemplateTypeParm in test) looked
fine, but inner type was not.

Differential Revision: https://reviews.llvm.org/D100667
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/SemaCXX/recovery-expr-type.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 70c433a184a54819835e54c62c3e6891e7069861 by sidharth.baveja
[XCOFF][AIX] Add Global Variables Directly to TOC for 32 bit AIX

Summary:
This patch implements the backend implementation of adding global variables
directly to the table of contents (TOC), rather than adding the address of the
variable to the TOC.
Currently, this patch will look for the "toc-data" attribute on symbols in the
IR, and then add those symbols to the TOC.
ATM, this is implemented for 32 bit AIX.

Reviewers: sfertile
Differential Revision: https://reviews.llvm.org/D101178
The file was addedllvm/test/CodeGen/PowerPC/basic-toc-data-def.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was addedllvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll
The file was addedllvm/test/CodeGen/PowerPC/toc-data.ll
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/MC/MCSectionXCOFF.cpp
The file was addedllvm/test/CodeGen/PowerPC/basic-toc-data-local-linkage.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit 64d951be61aa7d69ad10cc87796151156da7d7ce by amy.kwan1
[PowerPC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns.

This patch introduces a new infrastructure that is used to select the load and
store instructions in the PPC backend.

The primary motivation is that the current implementation of selecting load/stores
is dependent on the ordering of patterns in TableGen. Given this limitation, we
are not able to easily and reliably generate the P10 prefixed load and stores
instructions (such as when the immediates that fit within 34-bits). This
refactoring is meant to provide us with more control over the patterns/different
forms to exploit, as well as eliminating dependency of pattern declaration in TableGen.

The idea of this refactoring is that it introduces a set of addressing modes that
correspond to different instruction formats of a particular load and store
instruction, along with a set of common flags that describes a load/store.
Whenever a load/store instruction is being selected, we analyze the instruction
and compute a set of flags for it. The computed flags are then used to
select the most optimal load/store addressing mode.

This patch is the first of a series of patches to be committed - it contains the
initial implementation of the refactored load/store selection infrastructure and
also updates P8/P9 patterns to adopt this infrastructure. The idea is that
incremental patches will add more implementation and support, and eventually
the old implementation will be removed.

Differential Revision: https://reviews.llvm.org/D93370
The file was modifiedllvm/test/CodeGen/PowerPC/p9-dform-load-alignment.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 88b259c01463c08ac2575b4432c07ea7751946b5 by jingu.kang
[SimpleLoopUnswitch] Port partially invariant unswitch from LoopUnswitch to SimpleLoopUnswitch

Differential Revision: https://reviews.llvm.org/D99354
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-mssa-threshold.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-update-memoryssa.ll
The file was modifiedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll
Commit a86cbd475576b0c08537bea44c54cfc332f215f2 by david.spickett
[lldb] More tests for DumpDataExtractor

* Using a base address or skipping it with LLDB_INVALID_ADDRESS
* Using a data offset, which does not effect the printed addresses
* Not providing an output stream
* Formatting a double sized HexFloat
* Formatting over multiple lines

Since address printing now has its own test,
I've removed the base address from all the format
type tests.

The multi line tests still use a base address to check that
it's incremented correctly for each new line.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D101627
The file was modifiedlldb/unittests/Core/DumpDataExtractorTest.cpp
Commit c9c4676a458b1ef99ffb67b43cfd87d6c27a448c by kzhuravl_dev
AMDGPU/llvm-readobj: Add missing tests for note parsing/displaying

This is a follow up review/change for https://reviews.llvm.org/D95638

Add valid note tests for code object v2 notes:
  - NT_AMD_HSA_CODE_OBJECT_VERSION (required yaml2obj update)
  - NT_AMD_HSA_HSAIL (required yaml2obj update)
  - NT_AMD_HSA_ISA_VERSION (required yaml2obj update)
  - NT_AMD_HSA_METADATA
  - NT_AMD_HSA_ISA_NAME
  - NT_AMD_PAL_METADATA

Add valid note tests for code object v3 notes:
  - NT_AMDGPU_METADATA

Add invalid note tests for code object v2 notes:
  - NT_AMD_HSA_CODE_OBJECT_VERSION (required yaml2obj update)
  - NT_AMD_HSA_HSAIL (required yaml2obj update)
  - NT_AMD_HSA_ISA_VERSION (required yaml2obj update)

Add invalid note tests for code object v3 notes:
  - NT_AMDGPU_METADATA

Differential Revision: https://reviews.llvm.org/D101304
The file was addedllvm/test/tools/llvm-readobj/ELF/note-amd-valid-v2.test
The file was addedllvm/test/tools/llvm-readobj/ELF/note-amd-invalid-v2.test
The file was addedllvm/test/tools/llvm-readobj/ELF/note-amd-invalid-v3.test
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was addedllvm/test/tools/llvm-readobj/ELF/note-amd-valid-v3.s
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 985ab6e1fa575fc41ebfdafbba401e5787661584 by Paul C. Anagnostopoulos
[TableGen] Fix two bugs in 'defm' when complex 'assert' is involved.

This patch fixes two bugs that arise when a 'defm' inherits from a multiclass
and also from a class with assertions.

Differential Revision: https://reviews.llvm.org/D101626
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/test/TableGen/assert.td
The file was modifiedllvm/lib/TableGen/TGParser.cpp
Commit 3338290c187b254ad071f4b9cbf2ddb2623cefc0 by tomas.matheson
[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0

atomicrmw instructions are expanded by AtomicExpandPass before register allocation
into cmpxchg loops. Register allocation can insert spills between the exclusive loads
and stores, which invalidates the exclusive monitor and can lead to infinite loops.

To avoid this, reimplement atomicrmw operations as pseudo-instructions and expand them
after register allocation.

Floating point legalisation:
f16 ATOMIC_LOAD_FADD(*f16, f16) is legalised to
f32 ATOMIC_LOAD_FADD(*i16, f32) and then eventually
f32 ATOMIC_LOAD_FADD_16(*i16, f32)

Differential Revision: https://reviews.llvm.org/D101164
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
The file was addedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_all.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Commit 8da5d111a5d2f795d5c32ef194f2e93c8ac0ec3f by david.spickett
[lldb] DumpDataExtractor tests for item byte size errors

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D101631
The file was modifiedlldb/unittests/Core/DumpDataExtractorTest.cpp
Commit c7df6b1223d88dfd15248fbf7b7b83dacad22ae3 by tomas.matheson
Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0"

This reverts commit 3338290c187b254ad071f4b9cbf2ddb2623cefc0.

Broke expensive checks on debian.
The file was modifiedllvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was removedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_all.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
Commit 44d0ad53afbe06d1141b84321eaca234c60a1305 by david.spickett
[lldb] Change DumpDataExtractorTest function names to lldb style (NFC)
The file was modifiedlldb/unittests/Core/DumpDataExtractorTest.cpp
Commit 62e9c7601adb1d137c8f5f2061bd47580ddd8f7f by bradley.smith
[AArch64][SVE] Remove unused function missed from D101302

The functionality in SVEIntrinsicOpts::isReinterpretToSVBool was moved in
D101302, however the original now unused function was not removed (NFC).

Differential Revision: https://reviews.llvm.org/D101642
The file was modifiedllvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
Commit a27af1d8166cc8cebd6ecfed94042852922d8239 by vince.a.bridgers
[analyzer] Fix assertion in SVals.h

Fix assertion in SVals.h apparently caused by
https://reviews.llvm.org/D89055.

clang:clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h:596:
clang::ento::loc::MemRegionVal::MemRegionVal(const clang::ento::MemRegion *):
  Assertion `r' failed.

Backtrace:
...
     clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h:597:3
     clang::QualType, clang::QualType)
     clang/lib/StaticAnalyzer/Core/SValBuilder.cpp:773:18
     clang::QualType, clang::QualType)
     clang/lib/StaticAnalyzer/Core/SValBuilder.cpp:612:12
     clang::QualType) clang/lib/StaticAnalyzer/Core/SValBuilder.cpp:587:12
     namespace)::RegionBindingsRef const&, clang::ento::Loc, clang::QualType)
     clang/lib/StaticAnalyzer/Core/RegionStore.cpp:1510:24
...

Reviewed By: ASDenysPetrov

Differential Revision: https://reviews.llvm.org/D101635
The file was modifiedclang/test/Analysis/casts.c
The file was modifiedclang/lib/StaticAnalyzer/Core/SValBuilder.cpp