SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [X86]Fix a crash trying to convert indices to proper type. (details)
  2. [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV (details)
  3. [AMDGPU] Autogenerate checks for a clustering test and add GFX10 (details)
  4. [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM (details)
  5. Revert "[Passes] Enable the relative lookup table converter pass on aarch64" (details)
  6. [X86][SSE] Move unpack(hop,hop) fold from foldShuffleOfHorizOp to combineTargetShuffle (details)
  7. Make dependency between certain analysis passes transitive (reapply) (details)
  8. [AArch64] Fix scalar imm variants of SIMD shift left instructions (details)
  9. [SystemZ][z/OS] Fix return values in AutoConversion functions (details)
  10. [DebugInfo][test][MIPS] Use mtriple in tests (details)
  11. [OpenCL] Add clang extension for non-portable kernel parameters. (details)
  12. [AArch64] Fix for the pre-indexed paired load/store optimization. (details)
  13. [AsmParser][SystemZ][z/OS] Reject character and string literals for HLASM (details)
  14. [AMDGPU][OpenMP] Fix clang driver crash when provided -c (details)
  15. [mlir][linalg] Fix bug in the fusion on tensors index op handling. (details)
  16. [AMDGPU] Fix llc pipeline lit test for bots enabling expensive checks (details)
  17. [MIPS][MSA] Regenerate bitwise tests. NFCI. (details)
  18. [MIPS][MSA] Regenerate i5-b tests. NFCI. (details)
  19. [MIPS][MSA] Regenerate immediates tests. NFCI. (details)
  20. [InstCombine] improve readability; NFC (details)
  21. [GlobalISel] Fix buildZExtInReg creating new register. (details)
  22. [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics (details)
  23. [RISCV][NFC] Fix up pseudoinstruction name in comment (details)
  24. [libc] Normalize LIBC_TARGET_MACHINE (details)
  25. Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics" (details)
  26. [docs] Update the llvm/example section (details)
  27. Added a faster method to clone llvm project [DOCS] (details)
  28. [clang][Driver] Add -fintegrate-as to debug-pass-structure test (details)
  29. [mlir][Affine][Vector] Support vectorizing reduction loops (details)
  30. [AMDGPU] Pre-commit 2 new saddr load tests. NFC. (details)
  31. [clang] remove an incremental build workaround (details)
  32. [mlir][ArmSVE] Add masked arithmetic operations (details)
  33. [LV] Workaround PR49900 (a crash due to analyzing partially mutated IR) (details)
  34. [MC] Untangle MCContext and MCObjectFileInfo (details)
  35. [NFC][X86][CostModel] Add tests for byteswap intrinsic (details)
  36. RISSCV: clang-format RISC-V AsmParser (NFC) (details)
  37. [llvm-objcopy][ELF] --only-keep-debug: set offset/size of segments with no sections to zero (details)
  38. [NFC][SimplifyCFG] Update documentation comments for SinkCommonCodeFromPredecessors() after 1886aad (details)
  39. [Clang] remove text extension from diag::err_drv_invalid_value_with_suggestion (details)
  40. Make clangd CompletionModel not depend on directory layout. (details)
  41. [lld-macho] Have --reproduce account for path rerooting (details)
  42. [lld-macho] Preliminary support for ARM_RELOC_BR24 (details)
  43. [hwasan] Fix missing synchronization in AllocThread. (details)
  44. [libomptarget] Initial documentation on amdgpu offload (details)
  45. [WebAssembly] Set alignment to 1 for SIMD memory intrinsics (details)
  46. [libc++] NFC: Remove stray semicolon in from-scratch config files (details)
  47. [libcxx] [ci] Add a Windows CI configuration for a statically linked libc++ (details)
  48. [lld-macho] Try to unbreak build (details)
  49. Add fuzzer for Rust demangler (details)
  50. [WebAssembly] Update narrowing builtin function operand types (details)
  51. [WebAssembly] Fix constness of pointer params to load intrinsics (details)
  52. [libc++] Move <__sso_allocator> out of include/ into src/. NFCI. (details)
  53. [libc++] [LIBCXX-DEBUG-FIXME] Fix an iterator-invalidation issue in string::assign. (details)
  54. [libc++] [LIBCXX-DEBUG-FIXME] Iterating a string::iterator "off the end" is UB. (details)
  55. [libc++] [LIBCXX-DEBUG-FIXME] Our `__debug_less` breaks some complexity guarantees. (details)
  56. [libc++] [LIBCXX-DEBUG-FIXME] std::advance shouldn't use ADL `>=` on the _Distance type. (details)
  57. [libc++] [LIBCXX-DEBUG-FIXME] Stop using invalid iterators to insert into sets/maps. (details)
  58. [scudo] Align objects with alignas (details)
  59. [mlir][tosa] Add tosa.depthwise lowering to existing linalg.depthwise_conv (details)
  60. [lld] Convert LLVM_CMAKE_PATH to a CMake path (details)
  61. [WebAssembly] Add SIMD const_splat intrinsics (details)
  62. [NFC][X86][Codegen] Add some tests for 64-bit shift by (32-x) (details)
  63. Preserve metadata on masked intrinsics in auto-upgrade (details)
  64. [Utils][NFC] Rename replace-function-regex in update_cc_test_checks (details)
  65. [MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs (details)
  66. [mlir] Add polynomial approximation for math::ExpM1 (details)
  67. GlobalISel: Use DAG call lowering infrastructure in a more compatible way (details)
  68. X86/GlobalISel: Use generic version of splitToValueTypes (details)
  69. AMDGPU/GlobalISel: Remove unnecessary override (details)
  70. GlobalISel: Update documentation (details)
  71. [clangd] Split CC and refs limit and increase refs limit to 1000 (details)
  72. [AMDGPU] Improve global SADDR selection (details)
  73. When performing template argument deduction to select a partial (details)
  74. ARM/GlobalISel: Don't store a MachineInstrBuilder reference (details)
  75. AMDGPU: Add a few more tail call tests (details)
  76. [gn build] (semi-manually) port 0b10bb7ddd3c (details)
  77. [lld-macho] Check simulator platforms to avoid issuing false positive errors. (details)
  78. [lldb] Handle missing SBStructuredData copy assignment cases (details)
  79. [gn build] (semi-manually) port 0b10bb7ddd3c more (details)
  80. [AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads (details)
  81. [Driver] Move -print-runtime-dir and -print-resource-dir tests (details)
  82. [AArch64] Fix some coding standard issues related to namespace llvm (details)
  83. [mlir][Linalg] Fix element type of results when folding reshapes. (details)
  84. AMDGPU: Fix lit test (details)
  85. Allow /STACK in #pragma comment(linker, ...) (details)
  86. Attach metadata to simplified masked loads and stores (details)
  87. [mlir][Linalg] Fix test to use new reshape op form. (details)
Commit 13a51e017c09ce449ba2ec0024baf356d6dfcbad by a.bataev
[X86]Fix a crash trying to convert indices to proper type.

Need to perfortm a bitcast on IndicesVec rather than subvector extract
if the original size of the IndicesVec is the same as the size of the
  destination type.

Differential Revision: https://reviews.llvm.org/D101838
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/var-permute-128.ll
Commit 437468f31942433c55bd2ceefeaaa0e8924deb1b by fraser
[RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV

As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
Commit f106fe5f23deb66092ab2a846a31d4c0931fa0a5 by jay.foad
[AMDGPU] Autogenerate checks for a clustering test and add GFX10
The file was modifiedllvm/test/CodeGen/AMDGPU/cluster_stores.ll
Commit 61a46375a25b817da8657378b3fbd707a5e54771 by fraser
[RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM

As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
Commit 6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 by martin
Revert "[Passes] Enable the relative lookup table converter pass on aarch64"

This reverts commit 57b259a852a6383880f5d0875d848420bb3c2945.

The relative lookup table converter pass seems to cause problems
for chromium on Windows/ARM64, see https://crbug.com/1204788.
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit 85460a2f5b6309450b341d19d800a7d90786b941 by llvm-dev
[X86][SSE] Move unpack(hop,hop) fold from foldShuffleOfHorizOp to combineTargetShuffle

By moving this after more of the shuffle canonicalization we reduce the demanded vector elts, avoiding a few unnecessary copies/moves etc.
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 3ee826594a9ed4119dd1fdfdd3f5f9175991e688 by bjorn.a.pettersson
Make dependency between certain analysis passes transitive (reapply)

LazyBlockFrequenceInfoPass, LazyBranchProbabilityInfoPass and
LoopAccessLegacyAnalysis all cache pointers to their nestled required
analysis passes. One need to use addRequiredTransitive to describe
that the nestled passes can't be freed until those analysis passes
no longer are used themselves.

There is still a bit of a mess considering the getLazyBPIAnalysisUsage
and getLazyBFIAnalysisUsage functions. Those functions are used from
both Transform, CodeGen and Analysis passes. I figure it is OK to
use addRequiredTransitive also when being used from Transform and
CodeGen passes. On the other hand, I figure we must do it when
used from other Analysis passes. So using addRequiredTransitive should
be more correct here. An alternative solution would be to add a
bool option in those functions to let the user tell if it is a
analysis pass or not. Since those lazy passes will be obsolete when
new PM has conquered the world I figure we can leave it like this
right now.

Intention with the patch is to fix PR49950. It at least solves the
problem for the reproducer in PR49950. However, that reproducer
need five passes in a specific order, so there are lots of various
"solutions" that could avoid the crash without actually fixing the
root cause.

This is a reapply of commit 3655f0757f2b4b, that was reverted in
33ff3c20498ef5c2057 due to problems with assertions in the polly
lit tests. That problem is supposed to be solved by also adjusting
ScopPass to explicitly preserve LazyBlockFrequencyInfo and
LazyBranchProbabilityInfo (it already preserved
OptimizationRemarkEmitter which depends on those lazy passes).

Differential Revision: https://reviews.llvm.org/D100958
The file was modifiedllvm/lib/Analysis/LazyBlockFrequencyInfo.cpp
The file was modifiedpolly/lib/Analysis/ScopPass.cpp
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was addedllvm/test/Other/pr49950.ll
The file was modifiedllvm/lib/Analysis/LazyBranchProbabilityInfo.cpp
Commit 1ee50b473168735752a2f80ae9b356cfa70a76d0 by andrew.savonichev
[AArch64] Fix scalar imm variants of SIMD shift left instructions

This issue was reported in PR50057: Cannot select:
t10: i64 = AArch64ISD::VSHL t2, Constant:i32<2>

Shift intrinsics (llvm.aarch64.neon.ushl.i64 and sshl) with a constant
shift operand are lowered into AArch64ISD::VSHL in tryCombineShiftImm.
VSHL has i64 and v1i64 patterns for a right shift, but only v1i64 for
a left shift.

This patch adds the missing i64 pattern for AArch64ISD::VSHL, and LIT
tests to cover scalar variants (i64 and v1i64) of all shift
intrinsics (only ushl and sshl cases fail without the patch, others
were just not covered).

Differential Revision: https://reviews.llvm.org/D101580
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vshift.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
Commit 6a12875046fd8c3e9f67482803a9f0f7b39dcfa6 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix return values in AutoConversion functions

My previous patch https://reviews.llvm.org/rG1527a5e4b4834e65678f9c30f786a2f4c17932bf incorrectly set int return values instead of std::error_code. This patch correctly returns and std::error_code value.

Reviewed By: fanbo-meng, Jonathan.Crowther

Differential Revision: https://reviews.llvm.org/D101904
The file was modifiedllvm/lib/Support/AutoConvert.cpp
Commit f6ef409406d7691bed32d1835809ed4cbb14015b by Jinsong Ji
[DebugInfo][test][MIPS] Use mtriple in tests

Mips tests are using -march in RUN lines,
this will fail on AIX OS , when we get the mips-ibm-aix triple.

This is caused/exposed recently due to https://reviews.llvm.org/D101194 changed the default getMultiarchTriple in toolchain.

Update the tests to use -mtriple instead to avoid unintended failures.

Reviewed By: atanasyan

Differential Revision: https://reviews.llvm.org/D101863
The file was modifiedllvm/test/DebugInfo/Mips/dwarfdump-tls.ll
The file was modifiedllvm/test/DebugInfo/Mips/dsr-fixed-objects.ll
The file was modifiedllvm/test/DebugInfo/Mips/dsr-non-fixed-objects.ll
Commit e994e74bca49831eb649e7c67955e9de7a1784b6 by anastasia.stulova
[OpenCL] Add clang extension for non-portable kernel parameters.

Added __cl_clang_non_portable_kernel_param_types extension that
allows using non-portable types as kernel parameters. This allows
bypassing the portability guarantees from the restrictions specified
in C++ for OpenCL v1.0 s2.4.

Currently this only disables the restrictions related to the data
layout. The programmer should ensure the compiler generates the same
layout for host and device or otherwise the argument should only be
accessed on the device side. This extension could be extended to other
case (e.g. permitting size_t) if desired in the future.

Patch by olestrohm (Ole Strohm)!

https://reviews.llvm.org/D101168
The file was modifiedclang/test/Misc/r600.languageOptsOpenCL.cl
The file was modifiedclang/lib/Basic/Targets/NVPTX.h
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Basic/Targets/AMDGPU.h
The file was modifiedclang/test/SemaOpenCLCXX/invalid-kernel.clcpp
The file was modifiedclang/include/clang/Basic/OpenCLExtensions.def
The file was modifiedclang/test/Misc/nvptx.languageOptsOpenCL.cl
The file was modifiedclang/test/Misc/amdgcn.languageOptsOpenCL.cl
The file was modifiedclang/docs/LanguageExtensions.rst
Commit 3f4bad5eadacfc5322817eaa062dd272b52cfc54 by stelios.ioannou
[AArch64] Fix for the pre-indexed paired load/store optimization.

This patch fixes an issue where a pre-indexed store e.g.,
STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are
merged into a single store: STP x1, x0, [x0, #24]!
. They shouldn’t be merged because the second store uses
x0 as both the stored value and the address and so it needs to be using the updated x0.
Therefore, it should not be folded into a STP <>pre.

Additionally a new test case is added to verify this fix.

Differential Revision: https://reviews.llvm.org/D101888

Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
The file was modifiedllvm/test/CodeGen/AArch64/strpre-str-merge.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Commit ae2aef13618beb8cb86e8b137a8ddbc846461169 by anirudh_prasad
[AsmParser][SystemZ][z/OS] Reject character and string literals for HLASM

- As per the HLASM support we are providing, i.e. support only for the first parameter of the inline asm block, only pertaining to Z machine instructions defined in LLVM, character literals and string literals are not supported (see Figure 4 - https://www-01.ibm.com/servers/resourcelink/svc00100.nsf/pages/zOSV2R3sc264940/$file/asmr1023.pdf for more information)
- This patch explicitly rejects the usage of char literals and string literals (for example "abc 'a'") when the relevant field is set
- This is achieved by introducing a field called `LexHLASMStrings` in MCAsmLexer similar to `LexMasmStrings`

Reviewed By: abhina.sreeskantharajan, Kai

Differential Revision: https://reviews.llvm.org/D101660
The file was modifiedllvm/include/llvm/MC/MCParser/MCAsmLexer.h
The file was modifiedllvm/lib/MC/MCParser/AsmLexer.cpp
The file was modifiedllvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp
Commit 1f5cacfcb845fd4163dec5a8c7991934c53d6cb3 by Pushpinder.Singh
[AMDGPU][OpenMP] Fix clang driver crash when provided -c

The offload action is used in four different ways as explained
in Driver.cpp:4495. When -c is present, the final phase will be
assemble (linker when -c is not present). However, this phase
is skipped according to D96769 for amdgcn. So, offload action
arrives into following situation,

compile (device) ---> offload ---> offload

without -c the chain looks like,
compile (device) ---> offload ---> linker (device)
---> offload

The former situation creates an unhandled case which causes
problem. The solution presented in this patch delays the D96769
logic until job creation time. This keeps the offload action
in the 1 of the 4 specified situations.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D101901
The file was modifiedclang/lib/Driver/Driver.cpp
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit 4a6ee23d832f823d71faf7d0dca1b6eec71df253 by gysit
[mlir][linalg] Fix bug in the fusion on tensors index op handling.

The old index op handling let the new index operations point back to the
producer block. As a result, after fusion some index operations in the
fused block had back references to the old producer block resulting in
illegal IR. The patch now relies on a block and value mapping to avoid
such back references.

Differential Revision: https://reviews.llvm.org/D101887
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
Commit 83646f60a8a499473aad0fa591195065fca9d7b2 by baptiste.saleil
[AMDGPU] Fix llc pipeline lit test for bots enabling expensive checks
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit c673a95cb46aacc9631dbc7d1a07851d951f2e64 by llvm-dev
[MIPS][MSA] Regenerate bitwise tests. NFCI.

Simplifies an upcoming patch diff
The file was modifiedllvm/test/CodeGen/Mips/msa/bitwise.ll
Commit 679e30dc3f50b5fc6adc3a67dc2a4d1b23e8656e by llvm-dev
[MIPS][MSA] Regenerate i5-b tests. NFCI.

Simplifies an upcoming patch diff
The file was modifiedllvm/test/CodeGen/Mips/msa/i5-b.ll
Commit 0f97afe32044ab5b7e4d20090952143d8a5547e5 by llvm-dev
[MIPS][MSA] Regenerate immediates tests. NFCI.

Simplifies an upcoming patch diff
The file was modifiedllvm/test/CodeGen/Mips/msa/immediates.ll
Commit 00341978745d93e22560ae394a57e80a3fd29bf7 by spatel
[InstCombine] improve readability; NFC
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit a3d273c9ff4c789aec0dc743fa2dc846b5987312 by Vang.Thao
[GlobalISel] Fix buildZExtInReg creating new register.

Fix a bug where buildZExtInReg will create and use a new register instead of using the register from parameter DstOp Res.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D101871
The file was modifiedllvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
Commit 6e876f9dedf00b24a96b8781e3b39d5282c43e91 by jrtc27
[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics

Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.

This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.

This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.

Reviewed By: RKSimon, atanasyan

Differential Revision: https://reviews.llvm.org/D101342
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
Commit efc31be7f8e8487c774dd9052980b67f0d5e70e2 by fraser
[RISCV][NFC] Fix up pseudoinstruction name in comment
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Commit 7c2ece523d7ff74f3eeabce1b9685f3eaae8cff4 by gchatelet
[libc] Normalize LIBC_TARGET_MACHINE

Current implementation defines LIBC_TARGET_MACHINE with the use of CMAKE_SYSTEM_PROCESSOR.
Unfortunately CMAKE_SYSTEM_PROCESSOR is OS dependent and can produce different results.
An evidence of this is the various matchers used to detect whether the architecture is x86.

This patch normalizes LIBC_TARGET_MACHINE and renames it LIBC_TARGET_ARCHITECTURE.
I've added many architectures but we may want to limit ourselves to x86 and ARM.

Differential Revision: https://reviews.llvm.org/D101524
The file was modifiedlibc/config/linux/CMakeLists.txt
The file was modifiedlibc/test/loader/linux/CMakeLists.txt
The file was modifiedlibc/test/utils/FPUtil/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
The file was modifiedlibc/src/string/CMakeLists.txt
The file was modifiedlibc/loader/linux/CMakeLists.txt
The file was addedlibc/src/string/x86_64/CMakeLists.txt
The file was removedlibc/src/string/x86/memcpy.cpp
The file was modifiedlibc/src/threads/linux/CMakeLists.txt
The file was modifiedlibc/test/config/linux/CMakeLists.txt
The file was modifiedlibc/src/math/CMakeLists.txt
The file was addedlibc/cmake/modules/LLVMLibCArchitectures.cmake
The file was modifiedlibc/src/string/aarch64/CMakeLists.txt
The file was removedlibc/src/string/x86/CMakeLists.txt
The file was modifiedlibc/utils/FPUtil/CMakeLists.txt
The file was addedlibc/src/string/x86_64/memcpy.cpp
The file was modifiedlibc/test/src/math/CMakeLists.txt
The file was modifiedlibc/CMakeLists.txt
Commit 897d7bceb90f1ef4807c0f698eaff3c10b471cb9 by jrtc27
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"

This seems to have broken sanitizers, giving lots of

  Assertion `NumBits <= MAX_INT_BITS && "bitwidth too large"' failed.

failures across multiple targets (currently X86 and PowerPC). Reverting
until I have a chance to reproduce and debug.

This reverts commit 6e876f9dedf00b24a96b8781e3b39d5282c43e91.
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
Commit 0b9447157b01ac18bb9f4d865920027cbd7df840 by shivam98.tkg
[docs] Update the llvm/example section

Added details about the llvm/example section.

Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D101284
The file was modifiedllvm/docs/GettingStarted.rst
Commit 67ee2f870d3b06a5684251272eae36d6e0f519b0 by shivam98.tkg
Added a faster method to clone llvm project [DOCS]

Reviewed By: xgupta, amccarth

Differential Revision: https://reviews.llvm.org/D101433
The file was modifiedclang/www/get_started.html
Commit 20d0aca43073f18f70b1c5a665631dee1be1598d by Jinsong Ji
[clang][Driver] Add -fintegrate-as to debug-pass-structure test

CGProfilePass is not always on, it will be disabled when using
non-intergrated assemblers.

  // Only enable CGProfilePass when using integrated assembler, since
  // non-integrated assemblers don't recognize .cgprofile section.
  PMBuilder.CallGraphProfile = !CodeGenOpts.DisableIntegratedAS;

Add -fintegrate-as to make sure the output don't rely on the platform default.

Reviewed By: evgeny777

Differential Revision: https://reviews.llvm.org/D101918
The file was modifiedclang/test/Driver/debug-pass-structure.c
Commit d80b04ab0015b218b613f8fe59506d45739817b8 by sergei.grechanik
[mlir][Affine][Vector] Support vectorizing reduction loops

This patch adds support for vectorizing loops with 'iter_args'
implementing known reductions along the vector dimension. Comparing to
the non-vector-dimension case, two additional things are done during
vectorization of such loops:
- The resulting vector returned from the loop is reduced to a scalar
  using `vector.reduce`.
- In some cases a mask is applied to the vector yielded at the end of
  the loop to prevent garbage values from being written to the
  accumulator.

Vectorization of reduction loops is disabled by default. To enable it, a
map from loops to array of reduction descriptors should be explicitly passed to
`vectorizeAffineLoops`, or `vectorize-reductions=true` should be passed
to the SuperVectorize pass.

Current limitations:
- Loops with a non-unit step size are not supported.
- n-D vectorization with n > 1 is not supported.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D100694
The file was addedmlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction_2d.mlir
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
The file was modifiedmlir/include/mlir/Analysis/AffineAnalysis.h
The file was modifiedmlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
The file was modifiedmlir/include/mlir/Dialect/Affine/Utils.h
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was addedmlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.h
The file was modifiedmlir/include/mlir/Dialect/Affine/Passes.td
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.h
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit 4c178d809b1df3216de251d5345b8ecc9cc3990e by Stanislav.Mekhanoshin
[AMDGPU] Pre-commit 2 new saddr load tests. NFC.
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-load.ll
Commit f16afcd9b5ce3054aac2b08b3a20472c07b6773a by thakis
[clang] remove an incremental build workaround

This cleaned up an oversight over a year ago. Should no longer be needed.
The file was modifiedclang/test/CoverageMapping/coroutine.cpp
Commit 95861216ac6558dc0dbcf638902feb9072c84661 by javier.setoain
[mlir][ArmSVE] Add masked arithmetic operations

These instructions map to SVE-specific instrinsics that accept a
predicate operand to support control flow in vector code.

Differential Revision: https://reviews.llvm.org/D100982
The file was modifiedmlir/lib/Dialect/ArmSVE/IR/ArmSVEDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/ArmSVE/ArmSVE.td
The file was modifiedmlir/test/Dialect/ArmSVE/roundtrip.mlir
The file was modifiedmlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
The file was modifiedmlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
The file was modifiedmlir/test/Target/LLVMIR/arm-sve.mlir
Commit 80e8025083982f4eca8ca8200eafecf4a5c3ae6e by listmail
[LV] Workaround PR49900 (a crash due to analyzing partially mutated IR)

LoopVectorize has a fairly deeply baked in design problem where it will try to query analysis (primarily SCEV, but also ValueTracking) in the midst of mutating IR. In particular, the intermediate IR state does not represent the semantics of the original (or final) program.

Fixing this for real is hard, but all of the cases seen so far share a common symptom. In cases seen to date, the analysis being queried is the computation of the original loop's trip count. We can fix this particular instance of the issue by simply computing the trip count early, and caching it.

I want to be really clear that this is nothing but a workaround. It does nothing to fix the root issue, and at best, delays the time until we have to fix this for real. Florian and I have discussed an eventual solution in the review comments for https://reviews.llvm.org/D100663, but it's a lot of work.

Test taken from https://reviews.llvm.org/D100663.

Differential Revision: https://reviews.llvm.org/D101487
The file was addedllvm/test/Transforms/LoopVectorize/scev-during-mutation.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 632ebc4ab4374e53fce1ec870465c587e0a33668 by i
[MC] Untangle MCContext and MCObjectFileInfo

This untangles the MCContext and the MCObjectFileInfo. There is a circular
dependency between MCContext and MCObjectFileInfo. Currently this dependency
also exists during construction: You can't contruct a MOFI without a MCContext
without constructing the MCContext with a dummy version of that MOFI first.
This removes this dependency during construction. In a perfect world,
MCObjectFileInfo wouldn't depend on MCContext at all, but only be stored in the
MCContext, like other MC information. This is future work.

This also shifts/adds more information to the MCContext making it more
available to the different targets. Namely:

- TargetTriple
- ObjectFileType
- SubtargetInfo

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D101462
The file was modifiedllvm/include/llvm/MC/MCContext.h
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/SnippetFile.cpp
The file was modifiedllvm/unittests/MC/DwarfLineTables.cpp
The file was modifiedlldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
The file was modifiedclang/lib/Parse/ParseStmtAsm.cpp
The file was modifiedllvm/lib/MC/MCWinCOFFStreamer.cpp
The file was modifiedllvm/lib/MC/MCMachOStreamer.cpp
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Analysis.cpp
The file was modifiedllvm/lib/CodeGen/MachineModuleInfo.cpp
The file was modifiedllvm/tools/llvm-ml/llvm-ml.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/tools/llvm-mc/llvm-mc.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/Target/NVPTX/MCTargetDesc/NVPTXTargetStreamer.cpp
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
The file was modifiedllvm/unittests/CodeGen/MachineInstrTest.cpp
The file was modifiedllvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/LlvmState.cpp
The file was modifiedllvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/unittests/CodeGen/TestAsmPrinter.cpp
The file was modifiedllvm/lib/MC/MCStreamer.cpp
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/MC/MCContext.cpp
The file was modifiedllvm/include/llvm/MC/MCObjectFileInfo.h
The file was modifiedllvm/lib/Object/ModuleSymbolTable.cpp
The file was modifiedllvm/tools/llvm-ml/Disassembler.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
The file was modifiedllvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
The file was modifiedclang/tools/driver/cc1as_main.cpp
The file was modifiedllvm/lib/MC/MCParser/DarwinAsmParser.cpp
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/Disassembler.cpp
The file was modifiedllvm/lib/MC/MCParser/COFFAsmParser.cpp
The file was modifiedllvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
The file was modifiedllvm/lib/Target/TargetLoweringObjectFile.cpp
The file was modifiedllvm/lib/DWARFLinker/DWARFStreamer.cpp
The file was modifiedllvm/tools/sancov/sancov.cpp
The file was modifiedllvm/tools/llvm-dwp/llvm-dwp.cpp
Commit 833b33a7f4dc1d1f1a75bb3e04dee7ce8ed22f06 by lebedev.ri
[NFC][X86][CostModel] Add tests for byteswap intrinsic
The file was addedllvm/test/Analysis/CostModel/X86/bswap-store.ll
The file was addedllvm/test/Analysis/CostModel/X86/bswap-vec.ll
The file was addedllvm/test/Analysis/CostModel/X86/load-bswap.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/bswap.ll
Commit ba5c122647c79586a6d060ca649e586feb7f57a0 by Saleem Abdulrasool
RISSCV: clang-format RISC-V AsmParser (NFC)

This corrects a few issues identified by `clang-format`.  This is meant
to be preparation for a subsequent change.
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit b3336bfa2e6a38f16c4ecf4d77bd0f97ec5a46eb by i
[llvm-objcopy][ELF] --only-keep-debug: set offset/size of segments with no sections to zero

PR50160: we currently ignore non-PT_PHDR segments with no sections, not
accounting for its p_offset and p_filesz: this can cause an out-of-bounds write
in `writeSegmentData` if the p_offset+p_filesz is larger than the total file
size.

This can be fixed by setting p_offset=p_filesz=0. The logic nicely unifies with
the logic added in D90897.

Reviewed By: jhenderson, rupprecht

Differential Revision: https://reviews.llvm.org/D101560
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/only-keep-debug.test
Commit 8048005739ebf6734b2d841a528c06595062f899 by lebedev.ri
[NFC][SimplifyCFG] Update documentation comments for SinkCommonCodeFromPredecessors() after 1886aad
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit aefbfbcbd776f5549b18cd6083d6408f661efacc by ndesaulniers
[Clang] remove text extension from diag::err_drv_invalid_value_with_suggestion

This hinders translations, as per:
https://clang.llvm.org/docs/InternalsManual.html#the-format-string

Reviewed By: MaskRay, xbolva00

Differential Revision: https://reviews.llvm.org/D101387
The file was modifiedflang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedflang/test/Driver/fixed-line-length.f90
The file was modifiedclang/test/Driver/stack-protector-guard.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
Commit 7907c46fe6195728fafd843b8c0fb19a3e68e9ad by harald
Make clangd CompletionModel not depend on directory layout.

The current code accounts for two possible layouts, but there is at
least a third supported layout: clang-tools-extra may also be checked
out as clang/tools/extra with the releases, which was not yet handled.
Rather than treating that as a special case, use the location of
CompletionModel.cmake to handle all three cases. This should address the
problems that prompted D96787 and the problems that prompted the
proposed revert D100625.

Reviewed By: usaxena95

Differential Revision: https://reviews.llvm.org/D101851
The file was modifiedclang-tools-extra/clangd/quality/CompletionModel.cmake
Commit 20f51ffe67d12ab72c917dc4b371b55c80321393 by jezng
[lld-macho] Have --reproduce account for path rerooting

We need to account for path rerooting when generating the response
file. We could either reroot the paths before generating the file, or pass
through the original filenames and change just the syslibroot. I've opted for
the latter, in order that the reproduction run more closely mirrors the
original.

We must also be careful *not* to make an absolute path relative if it is
shadowed by a rerooted path. See repro6.tar in reroot-path.s for
details.

I've moved the call to `createResponseFile()` after the initialization of
`config->systemLibraryRoots`, since it now needs to know what those roots are.

Reviewed By: #lld-macho, oontvoo

Differential Revision: https://reviews.llvm.org/D101224
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/Driver.h
The file was modifiedlld/MachO/DriverUtils.cpp
The file was modifiedlld/test/MachO/reroot-path.s
Commit 8806df4778349dac4e8744b9ae50f43b80eedda3 by jezng
[lld-macho] Preliminary support for ARM_RELOC_BR24

ARM_RELOC_BR24 is used for BL/BLX instructions from within ARM (i.e. not
Thumb) code. This diff just handles the basic case: branches from ARM to
ARM, or from ARM to Thumb where no shimming is required. (See comments
in ARM.cpp for why shims are required.)

Note: I will likely be deprioritizing ARM work for the near future to
focus on other parts of LLD. Apologies for the half-done state of this;
I'm just trying to wrap up what I've already worked on.

Reviewed By: #lld-macho, alexshap

Differential Revision: https://reviews.llvm.org/D101814
The file was addedlld/test/MachO/arm-branch-relocs.s
The file was modifiedlld/MachO/Arch/ARM.cpp
Commit 18959a6a094c6469fc2fd5cc167fda7cbe3f163b by eugenis
[hwasan] Fix missing synchronization in AllocThread.

The problem was introduced in D100348.

It's really hard to trigger the bug in a stress test - the race is just too
narrow - but the new checks in Thread::Init should at least provide usable
diagnostic if the problem ever returns.

Differential Revision: https://reviews.llvm.org/D101881
The file was modifiedcompiler-rt/lib/hwasan/hwasan_thread.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan_thread_list.h
Commit 25fe17d3c1041de7e2dc5df865d7f65fd074f9a6 by jonathanchesterfield
[libomptarget] Initial documentation on amdgpu offload

[libomptarget] Initial documentation on amdgpu offload

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D101927
The file was modifiedopenmp/docs/SupportAndFAQ.rst
Commit 89333b35a7a909d29ae53fddcfb4792d87223b96 by tlively
[WebAssembly] Set alignment to 1 for SIMD memory intrinsics

The WebAssembly SIMD intrinsics in wasm_simd128.h generally try not to require
any particular alignment for memory operations to be maximally flexible. For
builtin memory access functions and their corresponding LLVM IR intrinsics,
there's no way to set the expected alignment, so the best we can do is set the
alignment to 1 in the backend. This change means that the alignment hints in the
emitted code will no longer be incorrect when users use the intrinsics to access
unaligned data.

Differential Revision: https://reviews.llvm.org/D101850
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
Commit 7fbc7bfdfddd85e12156556e3c074f6dcef865df by Louis Dionne
[libc++] NFC: Remove stray semicolon in from-scratch config files
The file was modifiedlibcxx/test/configs/libcxx-trunk-static.cfg.in
The file was modifiedlibcxx/test/configs/libcxx-trunk-shared.cfg.in
Commit 9b24ff9cd2efe1d8319af023ffb69efdaf4cd5ce by martin
[libcxx] [ci] Add a Windows CI configuration for a statically linked libc++

On Windows, static vs DLL linking affects details in quite a few
cases, so it's good to have coverage for both cases.

Testing with static linking also increases coverage for a number of
cases and individual checks that have had to be waived for the DLL
case, and allows testing libc++experimental, increasing the number
of test cases actually executed by 180 (176 new tests from
libc++experimental and 4 ones that are XFAIL windows-dll).

Also drop the "generic-" prefix from these configuration names, as
they're perhaps not what the "generic" prefix intended originally
in the other generic-posix configurations.

Differential Revision: https://reviews.llvm.org/D101565
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/test/libcxx/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/db_deallocate.pass.cpp
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 75ba35130080f91494b0ceb90c0501b50787b1cc by jezng
[lld-macho] Try to unbreak build

Looks like the PointerUnion casting cares about const-ness...
The file was modifiedlld/MachO/Arch/ARM.cpp
Commit 0e7c2aeaa8c0fe25178f7fc4c61cd92321cdde76 by dblaikie
Add fuzzer for Rust demangler

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101823
The file was addedllvm/tools/llvm-rust-demangle-fuzzer/llvm-rust-demangle-fuzzer.cpp
The file was addedllvm/tools/llvm-rust-demangle-fuzzer/CMakeLists.txt
The file was addedllvm/tools/llvm-rust-demangle-fuzzer/DummyDemanglerFuzzer.cpp
Commit 627a52695537dd2bea068630887431febbf06856 by tlively
[WebAssembly] Update narrowing builtin function operand types

Make the inputs to all narrowing builtins signed, which is how they are
interpreted by the underlying instructions (only the result changes sign
between instructions).

Differential Revision: https://reviews.llvm.org/D101883
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedclang/test/CodeGen/builtins-wasm.c
Commit 602f318cfdac999a8604f1588159326b1a1a1a23 by tlively
[WebAssembly] Fix constness of pointer params to load intrinsics

Update the SIMD builtin load functions to take pointers to const data and update
the intrinsics themselves to not cast away constness.

Differential Revision: https://reviews.llvm.org/D101884
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedclang/lib/Headers/wasm_simd128.h
Commit 0b10bb7ddd3c92465ef12d52e88614e6b4c5ef27 by arthur.j.odwyer
[libc++] Move <__sso_allocator> out of include/ into src/. NFCI.

This allocator is not intended for libc++'s users to use;
it's strictly an implementation detail of `src/locale.cpp`.
So, move it to the `src/include/` directory.

Drive-by const-qualify its comparison operators.

For consistency with `__hidden_allocator` (defined in `src/thread.cpp`),
do *not* remove it from "libcxx/lib/libc++unexp.exp",
"libcxx/utils/symcheck-blacklists/linux_blacklist.txt", etc.

Differential Revision: https://reviews.llvm.org/D101293
The file was addedlibcxx/src/include/sso_allocator.h
The file was modifiedlibcxx/include/module.modulemap
The file was modifiedlibcxx/include/CMakeLists.txt
The file was modifiedlibcxx/src/locale.cpp
The file was removedlibcxx/include/__sso_allocator
The file was modifiedlibcxx/src/CMakeLists.txt
Commit db9425cb060bd076fcdcbb5a37bfd992deff2086 by arthur.j.odwyer
[libc++] [LIBCXX-DEBUG-FIXME] Fix an iterator-invalidation issue in string::assign.

This appears to be a bug in our string::assign: when assigning into
a longer string, from a shorter snippet of itself, we invalidate
iterators before doing the copy. We should invalidate them afterward.
Also drive-by improve the formatting of a function header.

Differential Revision: https://reviews.llvm.org/D101675
The file was modifiedlibcxx/include/string
The file was modifiedlibcxx/test/std/strings/basic.string/string.modifiers/string_assign/iterator.pass.cpp
Commit 12dd9cdf1a8267e0c5db4f191f2598648de02619 by arthur.j.odwyer
[libc++] [LIBCXX-DEBUG-FIXME] Iterating a string::iterator "off the end" is UB.

The range of char pointers [data, data+size] is a valid closed range,
but the range [begin, end) is valid only half-open.

Differential Revision: https://reviews.llvm.org/D101676
The file was modifiedlibcxx/test/std/input.output/filesystems/class.path/path.nonmember/path.factory.pass.cpp
Commit 165ad89947e8ef6c08c80eb067d85b4fa9074904 by arthur.j.odwyer
[libc++] [LIBCXX-DEBUG-FIXME] Our `__debug_less` breaks some complexity guarantees.

`__debug_less` ends up running the comparator up-to-twice per comparison,
because whenever `(x < y)` it goes on to verify that `!(y < x)`.
This breaks the strict "Complexity" guarantees of algorithms like
`inplace_merge`, which we test in the test suite. So, just skip the
complexity assertions in debug mode.

Differential Revision: https://reviews.llvm.org/D101677
The file was modifiedlibcxx/test/std/algorithms/alg.sorting/alg.merge/inplace_merge_comp.pass.cpp
The file was modifiedlibcxx/docs/DesignDocs/DebugMode.rst
Commit 9571b8f238f97bce01bcf3c84a4f87cfb1c00dbf by arthur.j.odwyer
[libc++] [LIBCXX-DEBUG-FIXME] std::advance shouldn't use ADL `>=` on the _Distance type.

Convert to a primitive type first; then use primitive `>=` on that value.

Differential Revision: https://reviews.llvm.org/D101678
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/iterator.operations/robust_against_adl.pass.cpp
Commit 9ea2db2c513534aa63acc087b8dc744c37119d02 by arthur.j.odwyer
[libc++] [LIBCXX-DEBUG-FIXME] Stop using invalid iterators to insert into sets/maps.

This simply applies Howard's commit 4c80bfbd53caf consistently
across all the associative and unordered container tests.

"unord.set/insert_hint_const_lvalue.pass.cpp" failed with `-D_LIBCPP_DEBUG=1`
before this patch; it was the only one that incorrectly reused
invalid iterator `e`. The others already used valid iterators
(generally `c.end()`); I'm just making them all match the same pattern
of usage: "e, then r, then c.end() for the rest."

Differential Revision: https://reviews.llvm.org/D101679
The file was modifiedlibcxx/test/std/containers/unord/unord.map/unord.map.modifiers/insert_hint_rvalue.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/insert_hint_const_lvalue.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multiset/insert_hint_const_lvalue.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multimap/unord.multimap.modifiers/insert_hint_const_lvalue.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/insert_hint_rvalue.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.map/unord.map.modifiers/insert_hint_const_lvalue.pass.cpp
Commit 1d767b13bfad806bf584e0b054eb7d00a494591d by Vitaly Buka
[scudo] Align objects with alignas

Operator new must align allocations for types with large alignment.

Before c++17 behavior was implementation defined and both clang and gc++
before 11 ignored alignment. Miss-aligned objects mysteriously crashed
tests on Ubuntu 14.

Alternatives are compile with -std=c++17 or -faligned-new, but they were
discarded as less portable.

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D101874
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/primary_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/combined_test.cpp
Commit 7abb56c78ba7bb9e2a91f61a65bb8feb69a92865 by rob.suderman
[mlir][tosa] Add tosa.depthwise lowering to existing linalg.depthwise_conv

Implements support for undialated depthwise convolution using the existing
depthwise convolution operation. Once convolutions migrate to yaml defined
versions we can rewrite for cleaner implementation.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D101579
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 662a58fa0534508c2c37b22425bfdf16b9d985a8 by isuruf
[lld] Convert LLVM_CMAKE_PATH to a CMake path

Otherwise I get the following error on windows.
```
CMake Error at D:/bld/lld_1569206597988/work/build/CMakeFiles/CMakeTmp/CMakeLists.txt:2 (set):
  Syntax error in cmake code at

    D:/bld/lld_1569206597988/work/build/CMakeFiles/CMakeTmp/CMakeLists.txt:2

  when parsing string

    D:\bld\lld_1569206597988\_h_env\Library\lib\cmake\llvm

  Invalid character escape '\b'.

CMake Error at D:/bld/lld_1569206597988/_build_env/Library/share/cmake-3.15/Modules/CheckSymbolExists.cmake:100 (try_compile):
  Failed to configure test project build system.
Call Stack (most recent call first):
  D:/bld/lld_1569206597988/_build_env/Library/share/cmake-3.15/Modules/CheckSymbolExists.cmake:57 (__CHECK_SYMBOL_EXISTS_IMPL)
  D:/bld/lld_1569206597988/_h_env/Library/lib/cmake/llvm/HandleLLVMOptions.cmake:943 (check_symbol_exists)
  CMakeLists.txt:56 (include)
```

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D68158
The file was modifiedlld/CMakeLists.txt
Commit 81fce29d6e1f0a83e8a4170c7f24cdd93869d55a by tlively
[WebAssembly] Add SIMD const_splat intrinsics

These intrinsics do not correspond to their own underlying instruction, but are
a convenience for the common case of materializing a constant vector that has
the same value in each lane.

Differential Revision: https://reviews.llvm.org/D101885
The file was modifiedclang/lib/Headers/wasm_simd128.h
The file was modifiedclang/test/Headers/wasm.c
Commit 40147c33d17eca98d186628272a076a1bb3e6868 by lebedev.ri
[NFC][X86][Codegen] Add some tests for 64-bit shift by (32-x)
The file was addedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
Commit 1817dae1924144c19b9caec196f574c51d6d9957 by kparzysz
Preserve metadata on masked intrinsics in auto-upgrade

When auto-upgrade was replacing a call to a masked intrinsic, it would
not copy the metadata from the original call.

If an intrinsic had metadata, but did not need any updates, the metadata
would stay, but if an update was needed, the would end up being removed.
A similar effect could be observed with masked_expandload and
masked_compressstore, which at the moment are not handled by auto-upgrade:
the metadata remained untouched.

Differential Revision: https://reviews.llvm.org/D101201
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was addedllvm/test/Bitcode/upgrade-masked-keep-metadata.ll
Commit 78a7d8c4dd1076dccfde2c48fc924d8f5529f4d1 by georgakoudis1
[Utils][NFC] Rename replace-function-regex in update_cc_test_checks

This patch renames the replace-function-regex to replace-value-regex to indicate that the existing regex replacement functionality can replace any IR value besides functions.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D101934
The file was modifiedclang/test/OpenMP/nvptx_parallel_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_parallel_for_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_codegen.cpp
The file was modifiedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c
The file was modifiedclang/test/OpenMP/nvptx_nested_parallel_codegen.cpp
The file was modifiedclang/test/utils/update_cc_test_checks/generated-funcs-regex.test
The file was modifiedllvm/utils/update_analyze_test_checks.py
The file was modifiedllvm/utils/update_llc_test_checks.py
The file was modifiedclang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_debug_codegen.cpp
The file was modifiedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
The file was modifiedclang/test/OpenMP/nvptx_lambda_capturing.cpp
The file was modifiedllvm/utils/UpdateTestChecks/common.py
The file was modifiedclang/test/OpenMP/nvptx_allocate_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_debug_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_teams_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_data_sharing.cpp
The file was modifiedclang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp
Commit a11489ae3e36063c64921439cbab89d1f3280f4a by mkitzan
[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs

- Move the code preventing CSE of `isConvergent` instrs into
  `ProcessBlockCSE` (from `isProfitableToCSE`)
- Add comments explaining why `isConvergent` is used to prevent
  CSE of non-local instrs in MachineCSE and the new test
The file was modifiedllvm/lib/CodeGen/MachineCSE.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
Commit 0edc4bc84aa246ee1f156982e19a1b8b5fbecf4c by ezhulenev
[mlir] Add polynomial approximation for math::ExpM1

This approximation matches the one in Eigen.

```
name                      old cpu/op  new cpu/op  delta
BM_mlir_Expm1_f32/10      90.9ns ± 4%  52.2ns ± 4%  -42.60%    (p=0.000 n=74+87)
BM_mlir_Expm1_f32/100      837ns ± 3%   231ns ± 4%  -72.43%    (p=0.000 n=79+69)
BM_mlir_Expm1_f32/1k      8.43µs ± 3%  1.58µs ± 5%  -81.30%    (p=0.000 n=77+83)
BM_mlir_Expm1_f32/10k     83.8µs ± 3%  15.4µs ± 5%  -81.65%    (p=0.000 n=83+69)
BM_eigen_s_Expm1_f32/10   68.8ns ±17%  72.5ns ±14%   +5.40%  (p=0.000 n=118+115)
BM_eigen_s_Expm1_f32/100   694ns ±11%   717ns ± 2%   +3.34%   (p=0.000 n=120+75)
BM_eigen_s_Expm1_f32/1k   7.69µs ± 2%  7.97µs ±11%   +3.56%   (p=0.000 n=95+117)
BM_eigen_s_Expm1_f32/10k  88.0µs ± 1%  89.3µs ± 6%   +1.45%   (p=0.000 n=74+106)
BM_eigen_v_Expm1_f32/10   44.3ns ± 6%  45.0ns ± 8%   +1.45%   (p=0.018 n=81+111)
BM_eigen_v_Expm1_f32/100   351ns ± 1%   360ns ± 9%   +2.58%    (p=0.000 n=73+99)
BM_eigen_v_Expm1_f32/1k   3.31µs ± 1%  3.42µs ± 9%   +3.37%   (p=0.000 n=71+100)
BM_eigen_v_Expm1_f32/10k  33.7µs ± 8%  34.1µs ± 9%   +1.04%    (p=0.007 n=99+98)
```

Reviewed By: ezhulenev

Differential Revision: https://reviews.llvm.org/D101852
The file was modifiedmlir/test/mlir-cpu-runner/math_polynomial_approx.mlir
The file was modifiedmlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp
The file was modifiedmlir/test/Dialect/Math/polynomial-approximation.mlir
Commit fa0b93b5a0866aad3ce517daab6cd91cc67823ad by Matthew.Arsenault
GlobalISel: Use DAG call lowering infrastructure in a more compatible way

Unfortunately the current call lowering code is built on top of the
legacy MVT/DAG based code. However, GlobalISel was not using it the
same way. In short, the DAG passes legalized types to the assignment
function, and GlobalISel was passing the original raw type if it was
simple.

I do believe the DAG lowering is conceptually broken since it requires
picking a type up front before knowing how/where the value will be
passed. This ends up being a problem for AArch64, which wants to pass
i1/i8/i16 values as a different size if passed on the stack or in
registers.

The argument type decision is split across 3 different places which is
hard to follow. SelectionDAG builder uses
getRegisterTypeForCallingConv to pick a legal type, tablegen gives the
illusion of controlling the type, and the target may have additional
hacks in the C++ part of the call lowering. AArch64 hacks around this
by not using the standard AnalyzeFormalArguments and special casing
i1/i8/i16 by looking at the underlying type of the original IR
argument.

I believe people have generally assumed the calling convention code is
processing the original types, and I've discovered a number of dead
paths in several targets.

x86 actually relies on the opposite behavior from AArch64, and relies
on x86_32 and x86_64 sharing calling convention code where the 64-bit
cases implicitly do not work on x86_32 due to using the pre-legalized
types.

AMDGPU targets without legal i16/f16 have always used a broken ABI
that promotes to i32/f32. GlobalISel accidentally fixed this to be the
ABI we should have, but this fixes it so we're using the worse ABI
that is compatible with the DAG. Ideally we would fix the DAG to match
the old GlobalISel behavior, but I don't wish to fight that battle.

A new native GlobalISel call lowering framework should let the target
process the incoming types directly.

CCValAssigns select a "ValVT" and "LocVT" but the meanings of these
aren't entirely clear. Different targets don't use them consistently,
even within their own call lowering code. My current belief is the
intent was "ValVT" is supposed to be the legalized value type to use
in the end, and and LocVT was supposed to be the ABI passed type
(which is also legalized).

With the default CCState::Analyze functions always passing the same
type for these arguments, these only differ when the TableGen part of
the lowering decide to promote the type from one legal type to
another. AArch64's i1/i8/i16 hack ends up inverting the meanings of
these values, so I had to add an additional hack to let the target
interpret how large the argument memory is.

Since targets don't consistently interpret ValVT and LocVT, this
doesn't produce quite equivalent code to the initial DAG
lowerings. I've opted to consistently interpret LocVT as the in-memory
size for stack passed values, and ValVT as the register type to assign
from that memory. We therefore produce extending loads directly out of
the IRTranslator, whereas the DAG would emit regular loads of smaller
values. This will also produce loads/stores that are wider than the
argument value if the allocated stack slot is larger (and there will
be undef padding bytes). If we had the optimizations to reduce
load/stores based on truncated values, this wouldn't produce a
different end result.

Since ValVT/LocVT are more consistently interpreted, we now will emit
more G_BITCASTS as requested by the CCAssignFn. For example AArch64
was directly assigning types to some physical vector registers which
according to the tablegen spec should have been casted to a vector
with a different element type.

This also moves the responsibility for inserting
G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the
generic code, which is closer to how SelectionDAGBuilder works.

I had to xfail an x86 test since I don't see a quick way to fix it
right now (I filed bug 50035 for this). It's broken independently of
this change, and only triggers since now we end up with more ands
which hit the improperly handled selection pattern.

I also observed that FP arguments that need promotion (e.g. f16 passed
as f32) are broken, and use regular G_TRUNC and G_ANYEXT.

TLDR; the current call lowering infrastructure is bad and nobody has
ever understood how it chooses types.
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/add-scalar.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/ext.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/callingconv.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
Commit 23ae35e858da37c753b8efaac965046358ec3818 by Matthew.Arsenault
X86/GlobalISel: Use generic version of splitToValueTypes

The custom insert of an unmerge and the callback weirdness should be
unnecessary. Since handleAssignments should now use
getRegisterTypeForCalling conv as SelectionDAG builder would, this
should now just be able to use the generic code. X86-32 relies on the
generated CCAssignFns not seeing illegal types and sharing code with
x86_64, so i64 values would incorrectly be assigned to 64-bit
registers.
The file was modifiedllvm/lib/Target/X86/X86CallLowering.h
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
Commit 8fc4eb9e732006b3b4f0b224c79ab097f3026f85 by Matthew.Arsenault
AMDGPU/GlobalISel: Remove unnecessary override

This is the same as the default implementation
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit e723b511e6e951444d2a646a23fc2e9cf4faecd4 by Matthew.Arsenault
GlobalISel: Update documentation
The file was modifiedllvm/docs/GlobalISel/IRTranslator.rst
Commit e623ce6188d698422d4ead24065056d6a869e6f8 by kbobyrev
[clangd] Split CC and refs limit and increase refs limit to 1000

Related discussion: https://github.com/clangd/clangd/discussions/761

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D101902
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
Commit 909a5ccf3be7868b24320aaaf0e588b56ba6e3f3 by Stanislav.Mekhanoshin
[AMDGPU] Improve global SADDR selection

An address can be a uniform sum of two i64 bit values.
That regularly happens in a loop where index is an induction
variable promoted to 64 bit by the LSR. We can materialize
zero in a VGPR and still use SADDR form of the load.

Differential Revision: https://reviews.llvm.org/D101591
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-load.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/global_atomics.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/offset-split-global.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
Commit 6bbfa0fd408e81055c360c2e059554dd76fd7f09 by richard
When performing template argument deduction to select a partial
specialization while substituting a partial template parameter pack,
don't try to extend the existing deduction.

This caused us to select the wrong partial specialization in some rare
cases. A recent change to libc++ caused this to happen in practice for
code using std::conjunction.
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/test/SemaTemplate/partial-spec-instantiate.cpp
Commit 6e88539ab16de1cbe1b6b0a7f2922fd5e710cab9 by Matthew.Arsenault
ARM/GlobalISel: Don't store a MachineInstrBuilder reference

This is basically a pointer anyway
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
Commit ef5f0adecd02d92cbb1a713ac7316f6768269412 by Matthew.Arsenault
AMDGPU: Add a few more tail call tests

Add some cases I noticed were missing when porting to GlobalISel. The
cases that required any argument splitting did not work at first.
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
Commit ceccfaae140d2a067d9023a9a3ca71efc86f9e2d by thakis
[gn build] (semi-manually) port 0b10bb7ddd3c
The file was modifiedllvm/utils/gn/secondary/libcxx/src/BUILD.gn
Commit 23233ad139f4b69ea4ed1cdbd22abc72c7a4cb93 by vyng
[lld-macho] Check simulator platforms to avoid issuing false positive errors.

Currently the linker causes unnecessary errors when either the target or the config's platform is a simulator.

Differential Revision: https://reviews.llvm.org/D101855
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/test/MachO/invalid/incompatible-arch.s
Commit c5cf4b8f11cd641560b0cd6e106765721688e74a by davelee.com
[lldb] Handle missing SBStructuredData copy assignment cases

Fix cases that can crash `SBStructuredData::operator=`.

This happened in a case where `rhs` had a null `SBStructuredDataImpl`.

Differential Revision: https://reviews.llvm.org/D101585
The file was modifiedlldb/unittests/API/CMakeLists.txt
The file was addedlldb/unittests/API/SBStructuredDataTest.cpp
The file was modifiedlldb/source/API/SBStructuredData.cpp
Commit ea3777fe2201fac29bfd5450a35f628b2a294306 by thakis
[gn build] (semi-manually) port 0b10bb7ddd3c more
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit 7a41639c60ab1bd3712302e2588d5c7d6d8b57dc by Vang.Thao
[AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads

Widen 1 and 2 byte scalar loads to 4 bytes when sufficiently
aligned to avoid using a global load.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D100430
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 9d3dbcd24c7d61e83fe5b3c4e7b7e4ecf9d70cd7 by phosek
[Driver] Move -print-runtime-dir and -print-resource-dir tests

Put these into a separate files to match other -print-* options tests.

Differential Revision: https://reviews.llvm.org/D101813
The file was addedclang/test/Driver/print-resource-dir.c
The file was modifiedclang/test/Driver/immediate-options.c
The file was addedclang/test/Driver/print-runtime-dir.c
Commit 7b0756a51a750f92d07ef82d02380c262e8e3803 by i
[AArch64] Fix some coding standard issues related to namespace llvm

https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64MacroFusion.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandImm.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FastISel.cpp
Commit b6060b76731da36e14ef96c789b79e3b23672973 by ravishankarm
[mlir][Linalg] Fix element type of results when folding reshapes.

Fixing a minor bug which lead to element type of the output being
modified when folding reshapes with generic op.

Differential Revision: https://reviews.llvm.org/D101942
The file was modifiedmlir/test/Dialect/Linalg/fusion-push-reshape.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
Commit b6d244e5b8ab62d04ae9b1cf7463b78ecbb2f989 by Matthew.Arsenault
AMDGPU: Fix lit test
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
Commit 7ac3fcc526ceb36da9ed41f27f686709a5554af8 by rnk
Allow /STACK in #pragma comment(linker, ...)

The Halide project uses `#pragma comment(linker, "/STACK:...")` to set
the stack size high enough for our embedded compiler to run in end-user
programs on Windows.

Unfortunately, lld-link.exe breaks on this when embedded in a COFF
object, despite supporting the flag on the command line. MSVC's link.exe
supports this fine. This patch extends support for this to lld-link.exe
for better compatibility with MSVC projects.

Differential Revision: https://reviews.llvm.org/D99680
The file was modifiedlld/COFF/Driver.cpp
The file was addedlld/test/COFF/stack-drectve.s
Commit 6251b2f7f697f9378f4f0dbb284eea9cbe286728 by kparzysz
Attach metadata to simplified masked loads and stores
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was addedllvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll
Commit 4b2d7ef3ea81d0d6746e609b46f38bfceff23838 by ravishankarm
[mlir][Linalg] Fix test to use new reshape op form.

Differential Revision: https://reviews.llvm.org/D101956
The file was modifiedmlir/test/Dialect/Linalg/fusion-push-reshape.mlir