SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. [Zorg][OpenMP] Add CUDA offloading worker. (details)
Commit e4aa8a2773fe76c427a91229f021ab067eafc8e7 by llvm-zorg
[Zorg][OpenMP] Add CUDA offloading worker.

This worker tests OpenMP offloading for the x86_64 and NVIDIA GPU. In
addition to check-openmp, it runs the SOLLVE Validation & Verification Suite
via the LLVM test-suite External builder. The builder is configured to
only warn if the SOLLVE suite fails, as it also tests features that
have not been implemented in Clang yet.

CUDA is intentionally not installed in a default location (/opt/cuda) to
resemble setups often found in computing clusters with multiple versions
of CUDA to choose from.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D101268
The file was modifiedbuildbot/osuosl/master/config/workers.py
The file was modifiedzorg/buildbot/builders/OpenMPBuilder.py
The file was modifiedbuildbot/osuosl/master/config/builders.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [mlir][linalg] Remove IndexedGenericOp support from LinalgToLoops... (details)
  2. [llvm-dwarfdump] Fix abstract origin vars location stats calculation (details)
  3. [libcxx][test] Make string.modifiers/clear_and_shrink_db1.pass.cpp a regular mode test (details)
  4. Support VectorTransfer splitting on writes also. (details)
  5. [OpenCL] [NFC] Fixed underline being too short in rst (details)
  6. Fix -Wdocumentation warnings. NFCI. (details)
  7. * Add support for JSON output style to llvm-symbolizer (details)
  8. [flang][cmake] Enable the new driver by default (details)
  9. [WebAssembly] Support for WebAssembly globals in LLVM IR (details)
  10. [VP] Improve the VP intrinsic unittests (details)
  11. [CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols (details)
  12. [LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC. (details)
  13. [MLIR] Switch llvm.noalias to a unit attribute (details)
  14. [AMDGPU] Add some GFX10.3 testing. NFC. (details)
  15. [RegAllocFast] properly handle STATEPOINT instruction. (details)
  16. [PowerPC][Bug] Fix Bug in Stack Frame Update Code (details)
  17. [LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling. (details)
  18. [libomptarget][nfc] Drop stringify in macro (details)
  19. [OpenCL] Allow use of double type without extension pragma. (details)
  20. [AMDGPU] Move code sinking before structurizer (details)
  21. [SLP] restrict matching of load combine candidates (details)
  22. [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again (details)
  23. CodeGen: Fix null dereference before null check (details)
  24. [X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp (details)
  25. [X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI. (details)
  26. [TableGen] Make the NUL character invalid in .td files (details)
  27. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost() (details)
  28. [VPlan] Register recipe for instr if the simplified value is recipe. (details)
  29. [OpenMP] Fix hidden helper + affinity (details)
  30. Revert "[TableGen] Make the NUL character invalid in .td files" (details)
  31. Fix typo "Execpt" in comments (details)
  32. [LoopInterchange] Fix legality for triangular loops (details)
  33. Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S" (details)
  34. [NFC][AMDGPU] Correct product name for gfx908 (details)
  35. [IR][AutoUpgrade] Drop align attribute from void return types (details)
  36. Produce warning for performing pointer arithmetic on a null pointer. (details)
  37. [NFC][X86] Precommit another testcase for D101944 (details)
  38. Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation (details)
  39. Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested. (details)
  40. Add null-pointer checks when accessing a TypeSystem's SymbolFile (details)
  41. [mlir] Use static shape knowledge when lowering memref.reshape (details)
  42. [libomptarget][nfc] Add hook to easily disable building amdgcn bclib (details)
  43. [libc++] s/_VSTD::declval/declval/g. NFCI. (details)
  44. [libc++] s/std::size_t/size_t/g. NFCI. (details)
  45. [libc++] s/_VSTD::chrono/chrono/g. NFCI. (details)
  46. [libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI. (details)
  47. [libc++] Remove more unnecessary _VSTD:: from type names. NFCI. (details)
  48. Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation" (details)
  49. [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. (details)
  50. [X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32) (details)
  51. [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min. (details)
  52. [libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10. (details)
  53. [X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds. (details)
  54. Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"" (details)
  55. Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  56. [TextAPI] Reformat llvm_unreachable message (details)
  57. [flang] Allow large and erroneous ac-implied-do's (details)
  58. Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  59. [lld/mac] Implement -sectalign (details)
  60. [git-clang-format] Do not apply clang-format to symlinks (details)
  61. [libcxx] [test] Fix filesystem permission tests for windows (details)
  62. [mlir][ODS]: Add per-op cppNamespace. (details)
  63. [ArgumentPromotion] Fix byval alignment handling. (details)
  64. [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local (details)
  65. [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. (details)
  66. [GlobalOpt] Remove heap SROA (details)
  67. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type (details)
  68. [lld][WebAssembly] Convert test to assembly. NFC. (details)
  69. [clang] Support -fpic -fno-semantic-interposition for RISCV (details)
  70. [OpenMP] Use compound operators for reduction combiner if available. (details)
  71. [libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows. (details)
Commit 7bc6df2528f60920ae8aaa90ef2351df4676232a by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgToLoops...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102187
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
Commit 1ed296360041c3091fa8d7348efde729f0d9c754 by djtodoro
[llvm-dwarfdump] Fix abstract origin vars location stats calculation

There are cases where a concrete DIE with DW_TAG_subprogram can have
abstract_origin attribute, so we handle that situation as well.

Differential Revision: https://reviews.llvm.org/D101025
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/stats-scope-bytes-covered.yaml
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
The file was removedllvm/test/tools/llvm-dwarfdump/X86/locstats-for-inlined-vars.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-v3.test
The file was addedllvm/test/tools/llvm-dwarfdump/X86/locstats-for-absctract-origin-vars.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-dwo.test
Commit 65e40f0b265d13bde397db41303ac08d214a6559 by kbessonova
[libcxx][test] Make string.modifiers/clear_and_shrink_db1.pass.cpp a regular mode test

Turn this test into a normal mode as it contains well-formed code and
checks for defined behavior. It still can be run in debug mode as of D100866.

Differential Revision: https://reviews.llvm.org/D102192
The file was removedlibcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink_db1.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink.pass.cpp
Commit 88a48999d249a5478d813596d1cfac6ba82126dc by tpopp
Support VectorTransfer splitting on writes also.

VectorTransfer split previously only split read xfer ops. This adds
the same logic to write ops. The resulting code involves 2
conditionals for write ops while read ops only needed 1, but the created
ops are built upon the same patterns, so pattern matching/expectations
are all consistent other than in regards to the if/else ops.

Differential Revision: https://reviews.llvm.org/D102157
The file was modifiedmlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit 7d20f709ea6da8442a153beda7ecdda07440f046 by olemarius.strohm
[OpenCL] [NFC] Fixed underline being too short in rst
The file was modifiedclang/docs/LanguageExtensions.rst
Commit 33399405f4423429ec92c98a116c9ddc486864ec by llvm-dev
Fix -Wdocumentation warnings. NFCI.
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
Commit 05d1ae4e18fa565ea522e02d2497ec68d1dbdd80 by aorlov
* Add support for JSON output style to llvm-symbolizer

This patch adds JSON output style to llvm-symbolizer to better support CLI automation by providing a machine readable output.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D96883
The file was modifiedllvm/docs/CommandGuide/llvm-symbolizer.rst
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-data.test
The file was modifiedllvm/lib/DebugInfo/Symbolize/DIPrinter.cpp
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-frame.ll
The file was modifiedllvm/tools/llvm-symbolizer/Opts.td
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-code.test
The file was modifiedllvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
Commit 04adfb660987072ad31756e0d04803f96c3c39f7 by andrzej.warzynski
[flang][cmake] Enable the new driver by default

With this patch, `FLANG_BUILD_NEW_DRIVER` is set to `On` by default
(i.e. the new driver is enabled). Note that the new driver depends on
Clang and hence with this change you will need to add `clang` to
`LLVM_ENABLE_PROJECTS`.

If you don't want to build the new driver, set `FLANG_BUILD_NEW_DRIVER`
to `Off`. This way you won't be required to include `clang` in
`LLVM_ENABLE_PROJECTS`.

Differential Revision: https://reviews.llvm.org/D101842
The file was modifiedflang/CMakeLists.txt
The file was modifiedflang/README.md
The file was modifiedllvm/CMakeLists.txt
Commit d7086af2143d58a6535e0837c4d8789c69c6985f by wingo
[WebAssembly] Support for WebAssembly globals in LLVM IR

This patch adds support for WebAssembly globals in LLVM IR, representing
them as pointers to global values, in a non-default, non-integral
address space.  Instruction selection legalizes loads and stores to
these pointers to new WebAssemblyISD nodes GLOBAL_GET and GLOBAL_SET.
Once the lowering creates the new nodes, tablegen pattern matches those
and converts them to Wasm global.get/set of the appropriate type.

Based on work by Paulo Matos in https://reviews.llvm.org/D95425.

Reviewed By: pmatos

Differential Revision: https://reviews.llvm.org/D101608
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedclang/lib/Basic/Targets/WebAssembly.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISD.def
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
The file was modifiedclang/test/CodeGen/target-data.c
The file was addedllvm/test/CodeGen/WebAssembly/global-get.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
The file was addedllvm/test/CodeGen/WebAssembly/global-set.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrRef.td
Commit b159987054e12ad9f5b5e373249cbdba90047b84 by simon.moll
[VP] Improve the VP intrinsic unittests

Test that all VP intrinsics are tested.
Test intrinsic id -> opcode -> intrinsic id round tripping.
Test property scopes in the include/llvm/IR/VPIntrinsics.def file.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D93534
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
Commit b2f21b145aecbf5bc1af63b79de395897fc2e6f4 by wingo
[CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols

As we have been missing support for WebAssembly globals on the IR level,
the lowering of WASM_SYMBOL_TYPE_GLOBAL to IR was incomplete.  This
commit fleshes out the lowering support, lowering references to and
definitions of addrspace(1) values to correctly typed
WASM_SYMBOL_TYPE_GLOBAL symbols.

Depends on D101608.

Differential Revision: https://reviews.llvm.org/D101913
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h
The file was modifiedllvm/test/CodeGen/WebAssembly/global-get.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global-set.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
Commit 518b7f913526b5d002751edfa88869d10f5412fc by martin
[LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC.

As this isn't handled as a regular relocation, the normal handling of
maybeReportRelocationToDiscarded in Chunks.cpp doesn't apply here.

This would have caught the issue fixed by
82de4e075339f5ad8d68cfe31eb45b771d4750ae.

Differential Revision: https://reviews.llvm.org/D102115
The file was modifiedlld/COFF/DLL.cpp
Commit 1c777ab459d7ee181d7aba62af8bc35a572a2290 by uday
[MLIR] Switch llvm.noalias to a unit attribute

Switch llvm.noalias attribute from a boolean attribute to a unit
attribute.

Differential Revision: https://reviews.llvm.org/D102225
The file was modifiedmlir/test/Dialect/LLVMIR/func.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Target/LLVMIR/llvmir-invalid.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir
Commit 3b873831c439021da736fdc7c2c54bd0da2869ea by jay.foad
[AMDGPU] Add some GFX10.3 testing. NFC.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/readcyclecounter.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/readcyclecounter.ll
Commit df47368d406aa4b9aaa7dd49026a0eff9763e6ca by dantrushin
[RegAllocFast] properly handle STATEPOINT instruction.

STATEPOINT is a fancy and complex pseudo instruction which
has both tied defs and regmask operand.

Basic FastRA algorithm is as follows:

1. Mark registers used by defs as free
2. If instruction has regmask operand displace clobbered registers
   according to regmask.
3. Assign registers for use operands.

In case of tied defs step 1 is replaced with allocation of registers
for them. But regmask is still processed, which may displace already
allocated registers. As a result, tied use and def will get assigned
to different registers.

This patch makes FastRA to process instruction's RegMask (if any) when
checking for physical registers interference.
That way tied operands won't get registers clobbered by regmask.

Reviewed By: arsenm, skatkov
Differential Revision: https://reviews.llvm.org/D99284
The file was addedllvm/test/CodeGen/X86/statepoint-fastregalloc.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit c79bc5942d0efd4740c7a6d36ad951c59ef3bc0e by stefanp
[PowerPC][Bug] Fix Bug in Stack Frame Update Code

The stack frame update code does not take into consideration spilling
to registers for callee saved registers. The option -ppc-enable-pe-vector-spills
turns on spilling to registers for callee saved registers and may expose a bug
in the code that moves a stack frame pointer update instruction.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101366
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
Commit 3f03877f5a838973d0d22f6b45c112228319f4da by martin
[LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling.

Differential Revision: https://reviews.llvm.org/D101903
The file was modifiedlldb/CMakeLists.txt
Commit dedca78d486e6532ad0d01f670c409c7339e6387 by jonathanchesterfield
[libomptarget][nfc] Drop stringify in macro

[libomptarget][nfc] Drop stringify in macro
A step towards deleting the macros entirely.

Differential Revision: https://reviews.llvm.org/D102228
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 13ea238b1e1db96ef5fd409e869d9a8ebeef1332 by anastasia.stulova
[OpenCL] Allow use of double type without extension pragma.

Simply use of extensions by allowing the use of supported
double types without the pragma. Since earlier standards
instructed that the pragma is used explicitly a new warning
is introduced in pedantic mode to indicate that use of
type without extension pragma enable can be non-portable.

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior
of the compiler less strict by accepting code without extra
pragma statements.

Differential Revision: https://reviews.llvm.org/D100980
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/test/Misc/warning-flags.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaOpenCL/extensions.cl
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit 09fe84abb4ee71f707c3ec8e960a42d8292f6211 by Piotr Sobczak
[AMDGPU] Move code sinking before structurizer

Moving code sinking pass before structurizer creates more sinking
opportunities.

The extra flow edges introduced by the structurizer can have adverse
effects on sinking, because the sinking pass prefers moving instructions
to blocks with unique predecessors and the structurizer destroys that
property in some cases.

A notable example is moving high-latency image instructions across kills.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D101115
The file was modifiedllvm/test/CodeGen/AMDGPU/multilevel-break.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was addedllvm/test/CodeGen/AMDGPU/sink-image-sample.ll
Commit 49950cb1f6f699cbb9d8f141c0c043d4795c3417 by spatel
[SLP] restrict matching of load combine candidates

The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.

Differential Revision: https://reviews.llvm.org/D102074
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit c02476f3158f2908ef0a6f628210b5380bd33695 by lebedev.ri
[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again

Instead of handling power-of-two sized vector chunks,
try handling the large vector in a stream mode,
decreasing the operational vector size
once it no longer works for the elements left to process.

Notably, this improves costs for overaligned loads - loading padding is fine.
This more directly tracks when we need to insert/extract the YMM/XMM subvector,
some costs fluctuate because of that.

Reviewed By: RKSimon, ABataev

Differential Revision: https://reviews.llvm.org/D100684
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/load_store.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit bce3cca4889a9e4ab7b9652b0c44bb49ca8f3bad by Matthew.Arsenault
CodeGen: Fix null dereference before null check
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
Commit 9acc03ad92c66b856f67bf11ff4460c7da45f413 by llvm-dev
[X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp

foldShuffleOfHorizOp only handled basic shufps(hop(x,y),hop(z,w)) folds - by moving this to canonicalizeShuffleMaskWithHorizOp we can work with more general/combined v4x32 shuffles masks, float/integer domains and support shuffle-of-packs as well.

The next step will be to support 256/512-bit vector cases.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 759b97e55a4bd7b0d89493686f4a769718e385ee by llvm-dev
[X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI.

Noticed while looking at D101944
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 6ca2bdb03c0fdb6736ed5c6a30d7bec6b557d1a0 by Paul C. Anagnostopoulos
[TableGen] Make the NUL character invalid in .td files

Differential Revision: https://reviews.llvm.org/D101923
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was addedllvm/test/TableGen/nul-char.td
Commit 69ed93a4355123a45c1d7216aea7cd53d07a361b by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()

Now that getMemoryOpCost() correctly handles all the vector variants,
we should no longer hand-roll our own version of it, but use it directly.

The AVX512 variant probably needs a similar change,
but there it is less obvious.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8.ll
Commit faebc6bf108eccdfd75917636c64137f73a7bda7 by flo
[VPlan] Register recipe for instr if the simplified value is recipe.

If the simplified VPValue is a recipe, we need to register it for Instr,
in case it needs to be recorded. The way this is handled in general may
change soon, following some post-commit comments.

This fixes PR50298.
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit c765d140fe45906fb503d843acccf5838e775245 by jonathan.l.peyton
[OpenMP] Fix hidden helper + affinity

When KMP_AFFINITY is set, each worker thread's gtid value is used as an
index into the place list to determine the thread's placement. With hidden
helpers enabled, this gtid value is shifted down leading to unexpected
shifted thread placement. This patch restores the previous behavior by
adjusting the mask index to take the number of hidden helper threads
into account.

Hidden helper threads are given the full initial mask and do not
participate in any of the other affinity mechanisms (place partitioning,
balanced affinity). Their affinity is only printed for debug builds.

Differential Revision: https://reviews.llvm.org/D101882
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
The file was modifiedopenmp/runtime/src/kmp_affinity.cpp
Commit 46402eb103d06b1e695ecfd6f6c9571615042a9c by Paul C. Anagnostopoulos
Revert "[TableGen] Make the NUL character invalid in .td files"

At least one build uses a 'sed' that does not understand \x00.

This reverts commit cf9647011c4f05e1eb4423c6637d84e2f26b2042.
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
The file was removedllvm/test/TableGen/nul-char.td
Commit c58912eca743c612fd2a22c03b64a1bda3d2180f by aakanksha555
Fix typo "Execpt" in comments

Differential Revision: https://reviews.llvm.org/D101858
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 29342291d25b83da97e74d75004b177ba41114fc by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions of the loop body
will be different before and after interchange, resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
Commit eca3d68399246765bc6e8c94ffb4d5927b1add12 by Pushpinder.Singh
Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S"

This reverts commit 7f78e409d0280c62209e1a7dc8c6d1409acc9184.
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit d6a228cba47ffb33d4f6814af1feaf49b34568d0 by Tony.Tye
[NFC][AMDGPU] Correct product name for gfx908

The product name for gfx908 is "AMD Instinct MI100 Accelerator".

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102209
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 4eff9469475384a59a9da407e78aa00262edcdd0 by Steven Wu
[IR][AutoUpgrade] Drop align attribute from void return types

Since D87304, `align` become an invalid attribute on none pointer types and
verifier will reject bitcode that has invalid `align` attribute.

The problem is before the change, DeadArgumentElimination can easily
turn a pointer return type into a void return type without removing
`align` attribute. Teach Autograde to remove invalid `align` attribute
from return types to maintain bitcode compatibility.

rdar://77022993

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D102201
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll.bc
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
Commit dfc1e31d49fe1380c9bab43373995df5fed15e6d by schmeise
Produce warning for performing pointer arithmetic on a null pointer.

Summary:
Test and produce warning for subtracting a pointer from null or subtracting
null from a pointer.  Reuse existing warning that this is undefined
behaviour.  Also add unit test for both warnings.

Reformat to satisfy clang-format.

Respond to review comments:  add additional test.

Respond to review comments:  Do not issue warning for nullptr - nullptr
in C++.

Fix indenting to satisfy clang-format.

Respond to review comments:  Add C++ tests.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: efriedma (Eli Friedman), nickdesaulniers (Nick Desaulniers)
Differential Revision: https://reviews.llvm.org/D98798
The file was modifiedclang/test/Sema/pointer-addition.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was addedclang/test/Sema/pointer-addition.cpp
Commit 2c1f9f390b0a5dd308e2e925fe250d19a29c103f by lebedev.ri
[NFC][X86] Precommit another testcase for D101944
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
Commit 6400905a615282c83a2fc6e49e57ff716aa8b4de by a-phipps
Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage
summary to do the same thing for branches that is done for lines and regions.
That is, across function instantiations in an instantiation group, the maximum
branch coverage found in any of those instantiations is returned, with the
total number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit 6c82b8a378a6f59e94a81d91225db4fabf6e2bff by augusto2112
Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested.

This change ensures that if for whatever reason we read less bytes than expected (for example, when trying to read memory that spans multiple sections), we try reading from the live process as well.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D101390
The file was modifiedlldb/source/Target/Target.cpp
Commit ec28e43e01540a57f8822b2efb8638996873f945 by augusto2112
Add null-pointer checks when accessing a TypeSystem's SymbolFile

A type system is not guaranteed to have a symbol file. This patch adds null-pointer checks so we don't crash when trying to access a type system's symbol file.

Reviewed By: aprantl, teemperor

Differential Revision: https://reviews.llvm.org/D101539
The file was modifiedlldb/source/Symbol/Type.cpp
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/unittests/Symbol/TestTypeSystemClang.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/PDB/PDBASTParser.cpp
Commit b20e150c9be16f69c73f4cd2986053d13d0f376a by benny.kra
[mlir] Use static shape knowledge when lowering memref.reshape

This is actually necessary for correctness, as memref.reinterpret_cast
doesn't verify if the output shape doesn't match the static sizes.

Differential Revision: https://reviews.llvm.org/D102232
The file was modifiedmlir/lib/Dialect/StandardOps/Transforms/ExpandOps.cpp
The file was modifiedmlir/test/Dialect/Standard/expand-ops.mlir
Commit 72995a4bdf7d95887883ccfa04567b723f2b342a by jonathanchesterfield
[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

This is useful when building LLVM with a toolchain that can't emit code
for amdgcn, e.g. because it overrides the include search path with headers
from another architecture, or the clang compiler is missing builtins.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D102229
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt
Commit ab3fcc5065a895f88ec8a020bc3c2f7e54cc4561 by arthur.j.odwyer
[libc++] s/_VSTD::declval/declval/g. NFCI.
The file was modifiedlibcxx/include/scoped_allocator
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/concepts
The file was modifiedlibcxx/include/__functional_base
The file was modifiedlibcxx/include/ostream
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/__memory/construct_at.h
The file was modifiedlibcxx/include/__memory/shared_ptr.h
The file was modifiedlibcxx/include/variant
The file was modifiedlibcxx/include/istream
The file was modifiedlibcxx/include/experimental/propagate_const
The file was modifiedlibcxx/include/memory
Commit 0b8da5fa5915f1cea790c7e246195e30afd9e391 by arthur.j.odwyer
[libc++] s/std::size_t/size_t/g. NFCI.
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/experimental/functional
Commit aa5e3beea3d4d4e00cb2b0f2d103b4bd52239384 by arthur.j.odwyer
[libc++] s/_VSTD::chrono/chrono/g. NFCI.
The file was modifiedlibcxx/include/chrono
Commit 866b27950aaf2c38f4ecfc8a0f18945fff3b8542 by arthur.j.odwyer
[libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI.
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/test/std/numerics/rand/rand.eng/rand.eng.lcong/params.fail.cpp
Commit 6491d99e330c38b33b9cb6acb19afa3a464febeb by arthur.j.odwyer
[libc++] Remove more unnecessary _VSTD:: from type names. NFCI.

Differential Revision: https://reviews.llvm.org/D102181
The file was modifiedlibcxx/include/__memory/allocator_traits.h
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/experimental/functional
The file was modifiedlibcxx/include/functional
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/include/experimental/type_traits
The file was modifiedlibcxx/include/type_traits
Commit 668dccc396da4f593ac87c92dc0eb7bc983b5762 by a-phipps
Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"

This reverts commit 6400905a615282c83a2fc6e49e57ff716aa8b4de.
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit dc00cbb5053895356955a6dc03632d4fa05048e3 by craig.topper
[RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.

Limited to splats because we would need to truncate the shift
amount vector otherwise.

I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102019
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
Commit 5f78ba001ca23ab826b9be823fc8ac0a0e5d2237 by lebedev.ri
[X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32)

I've seen this in the RawSpeed's BitPumpMSB*::push() hotpath,
after fixing the buffer abstraction to a more sane one,
when looking into a +5% runtime regression.
I was hoping that this would fix it, but it does not look it does.

This seems to be at least not worse than the original pattern.
But i'm actually mainly interested in the case where we already
compute `(y+32)` (see last test),

https://alive2.llvm.org/ce/z/ZCzJio

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D101944
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
Commit ce6e4f27dd72f834502f47176d84869a1f509d7b by craig.topper
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.

Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D101215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
Commit db13f832a1eec7427762c1ef1f56f169518f1abe by zoecarver
[libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10.

For some reason clang-10 can't match the expected errors produced by
passing icomplete arrays to range access functions. Disabling the tests
is a stop-gap solution to fix the bots.
The file was modifiedlibcxx/test/std/ranges/range.access/range.prim/empty.incomplete.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.begin/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cend/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cbegin/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.end/incomplete.compile.verify.cpp
Commit 4f80340fb6712f5f1e97e7667bfd5cffa7d684b7 by llvm-dev
[X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds.

We currently only fold if NumEltsPerLane == 4
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-4.ll
Commit eccb925147d5f262a3e74cc050d0665dd4e6d8db by a-phipps
Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation""

Originally landed in: 6400905a615282c83a2fc6e49e57ff716aa8b4de
Reverted in: 668dccc396da4f593ac87c92dc0eb7bc983b5762

Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage summary to do
the same thing for branches that is done for lines and regions.  That is,
across function instantiations in an instantiation group, the maximum branch
coverage found in any of those instantiations is returned, with the total
number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
Commit 1c7c6f2b106250d63905d7cde99a4559f0bb4978 by Lang Hames
Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reverts commit 6d263b6f1c9 while I investigate the CMake failures that it
causes in some configurations.
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was removedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was removedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was addedcompiler-rt/lib/orc/placeholder.cpp
The file was removedcompiler-rt/lib/orc/extensible_rtti.h
The file was removedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was removedcompiler-rt/lib/orc/extensible_rtti.cpp
Commit cba508fb678798094a4fd668ce6bf4225fc73509 by Jonas Devlieghere
[TextAPI] Reformat llvm_unreachable message

Change llvm_unreachable message from "Unknown llvm.MachO.PlatformKind
enum" to "Unknown llvm::MachO::PlatformKind enum".

Differential revision: https://reviews.llvm.org/D102250
The file was modifiedllvm/lib/TextAPI/Platform.cpp
Commit 5a9497d6890145da74325dfcb032ad2963b5da3f by psteinfeld
[flang] Allow large and erroneous ac-implied-do's

We sometimes unroll an ac-implied-do of an array constructor into a flat list
of values.  We then re-analyze the array constructor that contains the
resulting list of expressions.  Such a list may or may not contain errors.

But when processing an array constructor with an unrolled ac-implied-do, the
compiler was building an expression to represent the extent of the resulting
array constructor containing the list of values.  The number of operands
in this extent expression was based on the number of elements in the
unrolled list of values.  For very large lists, this created an
expression so large that it could not be evaluated by the compiler
without overflowing the stack.

I fixed this by continuously folding the extent expression as each operand is
added to it.  I added the test .../flang/test/Semantics/array-constr-big.f90
that will cause the compiler to seg fault without this change.

Also, when the unrolled ac-implied-do expression contains errors, we were
repeating the same error message referencing the same source line for every
instance of the erroneous expression in the unrolled list.  This potentially
resulted in a very long list of messages for a single error in the source code.

I fixed this by comparing the message being emitted to the previously emitted
message.  If they are the same, I do not emit the message.  This change is also
tested by the new test array-constr-big.f90.

Several of the existing tests had duplicate error messages for the same source
line, and this change caused differences in their output.  So I adjusted the
tests to match the new message emitting behavior.

Differential Revision: https://reviews.llvm.org/D102210
The file was modifiedflang/include/flang/Parser/message.h
The file was modifiedflang/test/Semantics/resolve70.f90
The file was modifiedflang/test/Semantics/io06.f90
The file was modifiedflang/test/Semantics/omp-clause-validity01.f90
The file was addedflang/test/Semantics/array-constr-big.f90
The file was modifiedflang/test/Semantics/omp-flush01.f90
The file was modifiedflang/include/flang/Evaluate/shape.h
The file was modifiedflang/test/Semantics/omp-atomic.f90
The file was modifiedflang/lib/Parser/message.cpp
The file was modifiedflang/test/Semantics/allocate02.f90
Commit e0b6c99288bf1798ccc80aa0c5c7940c17665e69 by Lang Hames
Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reapplies 6d263b6f1c9 (which was reverted in 1c7c6f2b106) with a fix for a
CMake issue.
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was removedcompiler-rt/lib/orc/placeholder.cpp
The file was addedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was addedcompiler-rt/lib/orc/extensible_rtti.h
The file was addedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was addedcompiler-rt/lib/orc/extensible_rtti.cpp
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
Commit 9ab49ae55dd7b928c2b806adccf6d07a89e59102 by thakis
[lld/mac] Implement -sectalign

clang sometimes passes this flag along (see D68351), so we should implement it.

Differential Revision: https://reviews.llvm.org/D102247
The file was modifiedlld/MachO/Driver.cpp
The file was addedlld/test/MachO/sectalign.s
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/Config.h
The file was modifiedlld/MachO/OutputSegment.cpp
Commit 0fd0a010a1ed2ce761d20bfc6378e5bbaa75c8de by pirama
[git-clang-format] Do not apply clang-format to symlinks

This fixes PR46992.

Git stores symlinks as text files and we should not format them even if
they have one of the requested extensions.

(Move the call to `cd_to_toplevel()` up a few lines so we can also print
the skipped symlinks during verbose output.)

Differential Revision: https://reviews.llvm.org/D101878
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/tools/clang-format/git-clang-format
Commit 68de58cd649cb3a3e94a1c9552ebf2a18bb9d040 by martin
[libcxx] [test] Fix filesystem permission tests for windows

On Windows, the permission bits are mapped down to essentially only
two possible states; readonly or readwrite. Normalize the checked
permission bitmask to match what the implementation will return.

Differential Revision: https://reviews.llvm.org/D101728
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file.pass.cpp
Commit 49755871ad0c24ed970c0a4f2c51f90488b0ddd2 by silvasean
[mlir][ODS]: Add per-op cppNamespace.

This is useful for dialects that have logical subparts.

Differential Revision: https://reviews.llvm.org/D102200
The file was modifiedmlir/lib/TableGen/Operator.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/TableGen/CodeGenHelpers.h
The file was modifiedmlir/test/mlir-tblgen/dialect.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/TableGen/Operator.h
Commit 61cbbba7a645a1d87db9a80867c84a788ab2ea9c by efriedma
[ArgumentPromotion] Fix byval alignment handling.

Make sure the alignment of the generated operations matches the
alignment of the byval argument.  Previously, we were just ignoring
alignment and getting lucky.

While I'm here, also delete the unnecessary "tail" handling.
Passing a pointer to a byval argument to a "tail" call is UB, so
rewriting to an alloca doesn't require any special handling.

Differential Revision: https://reviews.llvm.org/D89819
The file was modifiedllvm/test/Transforms/ArgumentPromotion/dbg.ll
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
The file was modifiedllvm/test/Transforms/ArgumentPromotion/attrs.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval.ll
The file was removedllvm/test/Transforms/ArgumentPromotion/tail.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval-2.ll
Commit ec27c5f170441ab54295830aa9f7d376406c6a0f by i
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local

Similar to X86 D73230 and AArch64 D101872

With this change, we can set dso_local in clang's -fpic -fno-semantic-interposition mode,
for default visibility external linkage non-ifunc-non-COMDAT definitions.

For such dso_local definitions, variable access/taking the address of a
function/calling a function will go through a local alias to avoid GOT/PLT.

Reviewed By: jrtc27, luismarques

Differential Revision: https://reviews.llvm.org/D101875
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was addedllvm/test/CodeGen/RISCV/elf-preemption.ll
Commit ae2b36e8bdfa612649c6f2d8b6b9079679cb2572 by Amara Emerson
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs.

This needs some tablegen changes so that we can actually import the patterns properly.

Differential Revision: https://reviews.llvm.org/D102204
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 129f466e222e13fdf680356831bb935e1229bdf4 by i
[GlobalOpt] Remove heap SROA

GlobalOpt implements a heap SROA (SROA for an malloc allocatated struct or array
of structs) which is largely undertested (heap-sra-[1234].ll are basically the
same test with very little difference) and does not trigger at all when
bootstrapping clang (it only supports the case of one single store).

The heap SROA implementation causes PR50027 (GEP is not properly handled; crash or miscompile).
Just drop the implementation. I have deleted some obviously duplicated tests
but kept `heap-sra-[12]{,-no-nullopt}.ll`.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D102257
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3-no-null-opt.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4-no-null-opt.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-2.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/MallocSROA-section.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-phi.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-1.ll
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
Commit 97e04d41e646aa13b0cc5ff3812bfb7305fa4756 by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type

This way we don't have to duplicate i32/f32 and i64/f64 entries,
which was already forgotten to be done for a few tuples.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit b2f227c6c87c16fa593e643a487efd9326249066 by sbc
[lld][WebAssembly] Convert test to assembly. NFC.

Differential Revision: https://reviews.llvm.org/D102264
The file was addedlld/test/wasm/reloc-addend.s
The file was removedlld/test/wasm/reloc-addend.ll
Commit 2075f2b296b0fa90cb7597f0f318232940d29e95 by i
[clang] Support -fpic -fno-semantic-interposition for RISCV

-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```

-fpic (var and fun are dso_preemptable)
```
test:
.LBB1_1:
        auipc   a0, %got_pcrel_hi(var)
        ld      a0, %pcrel_lo(.LBB1_1)(a0)
        lw      a0, 0(a0)
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
        tail    fun@plt
```

vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:
.Ltest$local:
.LBB1_1:
        auipc   a0, %pcrel_hi(.Lvar$local)
        addi    a0, a0, %pcrel_lo(.LBB1_1)
        lw      a0, 0(a0)
// The assembler either resolves .Lfun$local at assembly time (-mno-relax
// -fno-function-sections), or produces a relocation referencing a non-preemptible
// local symbol (which can avoid PLT).
        tail    .Lfun$local
```

Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.

Depends on D101875

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D101876
The file was modifiedclang/test/Driver/fsemantic-interposition.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit f90abac6caab3b44e6a000de8cb72d204e74eb76 by michael.p.rice
[OpenMP] Use compound operators for reduction combiner if available.

The OpenMP spec seems to require the compound operators be used for
+, *, &, |, and ^ reduction.  So use these if a class has those operators.
If not try the simple operators as we did previously to limit the impact
to existing code.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48584

Differential Revision: https://reviews.llvm.org/D101941
The file was modifiedclang/test/OpenMP/distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_reduction_messages.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/test/OpenMP/simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskgroup_task_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_reduction_messages.cpp
The file was addedclang/test/OpenMP/reduction_compound_op.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/task_in_reduction_message.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_reduction_messages.cpp
Commit 384dd9ddaf616a1563ee1c1a8a1347b7658e7a70 by vvereschaka
[libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows.

Fix for substitutes-in-compile-flags.sh.cpp to run it properly on Windows platform.

Differential Revision: https://reviews.llvm.org/D102048
The file was modifiedlibcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp