SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Add an "interrupt timeout" to Process, and pipe that through the (details)
  2. [lld][WebAssembly] Remove relocation target verification (details)
  3. [mlir] Move move capture in SparseElementsAttr::getValues (details)
  4. [NFC][LSAN] Limit the number of concurrent threads is the test (details)
  5. [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (details)
  6. [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract (details)
  7. [OpenMP] Changes to enable MSVC ARM64 build of libomp (details)
  8. [RISCV] Regenerate stepvector.ll. NFC (details)
  9. [hwasan] Stress test for thread creation. (details)
  10. [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 (details)
  11. Removed unnecessary introduction of semi-colons. (details)
  12. [mlir] Elide large elements attrs when printing Operations in diagnostics (details)
  13. [mlir][tosa] Tosa elementwise broadcasting had some minor bugs (details)
  14. [InstCombine] Clean up one-hot merge optimization (NFC) (details)
  15. [RISCV] Move instruction information into the RISCVII namespace (NFC) (details)
  16. [llvm-cov] Support for v4 format in convert-for-testing (details)
  17. Revert "[LoopInterchange] Fix legality for triangular loops" (details)
  18. [AIX][TLS] Diagnose use of unimplemented TLS models (details)
  19. [JITLink] Make LinkGraph debug dumps more readable. (details)
  20. [JITLink][x86-64] Add an x86_64 PointerSize constexpr. (details)
  21. [JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes. (details)
  22. [Coverage] Support overriding compilation directory (details)
  23. [LoopInterchange] Fix legality for triangular loops (details)
  24. [clang][Fuchsia] Introduce compat multilibs (details)
  25. [JITLink] Fix bogus format string. (details)
  26. Revert "[GVN] Clobber partially aliased loads." (details)
  27. GlobalISel: Move AArch64 AssignFnVarArg to base class (details)
  28. GlobalISel: Split ValueHandler into assignment and emission classes (details)
  29. GlobalISel: Make constant fields const (details)
  30. AMDGPU: Fix assert on constant load from addrspacecasted pointer (details)
  31. GlobalISel: Don't hardcode varargs=false in resultsCompatible (details)
  32. Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. (details)
  33. Add test for PR50039. (details)
  34. Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope." (details)
  35. [lld][WebAssembly] Fix for string merging + negative addends (details)
  36. This test is failing on Linux, skip while I investigate. (details)
  37. AMDGPU: Fix SILoadStoreOptimizer for gfx90a (details)
  38. Removing test... (details)
  39. [LoopInterchange] Handle lcssa PHIs with multiple predecessors (details)
  40. [NFC][msan] Move setlocale test into sanitizer_common (details)
  41. [mlir][AsmPrinter] Remove recursion while SSA naming (details)
  42. tsan: add a simple syscall test (details)
  43. tsan: mark sigwait as blocking (details)
  44. [VectorComine] Restrict single-element-store index to inbounds constant (details)
  45. tsan: declare annotations in test.h (details)
  46. sanitizer_common: fix SIG_DFL warning (details)
Commit 9558b602b22cb7d681757c5f56d941e39a9d9d19 by jingham
Add an "interrupt timeout" to Process, and pipe that through the
ProcessGDBRemote plugin layers.

Also fix a bug where if we tried to interrupt, but the ReadPacket
wakeup timer woke us up just after the timeout, we would break out
the switch, but then since we immediately check if the response is
empty & fail if it is, we could end up actually only giving a
small interval to the interrupt.

Differential Revision: https://reviews.llvm.org/D102085
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.cpp
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.h
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteClientBaseTest.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/unittests/tools/lldb-server/tests/TestClient.cpp
Commit b49a798e71f922a68628ad9e31ca12fdb864c2f5 by sbc
[lld][WebAssembly] Remove relocation target verification

We have this extra step in wasm-ld that doesn't exist in other lld
backend which verifies the existing contents of the relocation targets.
This was originally intended as an extra form of double checking and an
aid to compiler developers.   However it has always been somewhat
controversial and there have been suggestions in the past the we simply
remove it.

My motivation for removing it now is that its causing me a headache
when trying to fix an issue with negative addends.  In the case of
negative addends that final result can be wrapped/negative but this
checking code would require significant modification to be able to deal
with that case.  For example with some test cases I'm looking at I'm
seeing error like this:

```
wasm-ld: warning: /usr/local/google/home/sbc/dev/wasm/llvm-build/tools/lld/test/wasm/Output/merge-string.s.tmp.o:(.rodata_relocs): unexpected existing value for R_WASM_MEMORY_ADDR_I32: existing=FFFFFFFA expected=FFFFFFFFFFFFFFFA
```

Rather than try to refactor `calcExpectedValue` to somehow return two
different types of results (32 and 64-bit) depending on the relocation
type, I think we can just remove this code.

Differential Revision: https://reviews.llvm.org/D102265
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/test/wasm/reloc-addend.s
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedlld/wasm/InputChunks.cpp
Commit 731206f3684af5979e3a794970db83f9a34b4541 by riddleriver
[mlir] Move move capture in SparseElementsAttr::getValues

This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
Commit 2a73b7bd8cf7620fc0e478ac838b07ee6649dd8a by Vitaly Buka
[NFC][LSAN] Limit the number of concurrent threads is the test

Test still fails with D88184 reverted.

The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D102218
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 69069509b2d3cb0e0bcf6e38e0ab05c432adc763 by Amara Emerson
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
Commit ffbffaf6b6b0fc06abb7b43ec8de8bc61d941bc7 by albionapc
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.

Differential: https://reviews.llvm.org/D100604
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
The file was addedllvm/test/CodeGen/PowerPC/vec-extract-itofp.ll
Commit 4fb0aaf03381473ec8af727edb4b5d59b64b0d60 by Andrey.Churbanov
[OpenMP] Changes to enable MSVC ARM64 build of libomp

This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.

Differential Revision: https://reviews.llvm.org/D101173
The file was modifiedopenmp/runtime/src/kmp_platform.h
The file was modifiedopenmp/runtime/src/dllexports
The file was modifiedopenmp/runtime/src/kmp_os.h
The file was modifiedopenmp/runtime/src/z_Windows_NT-586_util.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_atomic.cpp
The file was modifiedopenmp/runtime/src/CMakeLists.txt
Commit d092dd56aed8af64425446544ca7c9a0616d86ce by craig.topper
[RISCV] Regenerate stepvector.ll. NFC

It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
Commit a7757f6c22e45e84e56da79af67fe29dd1c224f5 by eugenis
[hwasan] Stress test for thread creation.

This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.

The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.

Differential Revision: https://reviews.llvm.org/D101936
The file was addedcompiler-rt/test/hwasan/TestCases/Linux/create-thread-stress.cpp
Commit 4433f4601e8a8e36ddd9bb6f6ed394bda353b828 by Austin.Kerbow
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2

The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102252
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
Commit ebdcebfcb4b522a81290f67dcbb7222ff7f9d052 by aorlov
Removed unnecessary introduction of semi-colons.
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Commit a9bbbaaa8810b22c9672694d576e3a0a210af54a by riddleriver
[mlir] Elide large elements attrs when printing Operations in diagnostics

Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.

Differential Revision: https://reviews.llvm.org/D102272
The file was modifiedmlir/lib/IR/Diagnostics.cpp
Commit 764ad3b3fafbf57ca916715625fffb7df5dbeb92 by rob.suderman
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs

Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).

Differential Revision: https://reviews.llvm.org/D102276
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 15565403722ec37d8b1a3ee8625ee2e8efcd96ee by nikita.ppv
[InstCombine] Clean up one-hot merge optimization (NFC)

Remove the requirement that the instruction is a BinaryOperator,
make the predicate check more compact and use slightly more
meaningful naming for the and operands.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 3a64b7080d5033b3bd6f28fbac4a24d9490dc3c3 by evandro.menezes
[RISCV] Move instruction information into the RISCVII namespace (NFC)

Move instruction attributes into the `RISCVII` namespace and add associated helper functions.

Differential Revision: https://reviews.llvm.org/D102268
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Commit 489a3531a42fe97c7fa00255fc5e8d31a610492d by phosek
[llvm-cov] Support for v4 format in convert-for-testing

v4 moves function records to a dedicated section so we need to write
and read it separately.

https://reviews.llvm.org/D100535
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/tools/llvm-cov/TestingSupport.cpp
Commit d3f89d4d16883b2bcf5f032152f10e384b53d92a by congzhecao
Revert "[LoopInterchange] Fix legality for triangular loops"

This reverts commit 29342291d25b83da97e74d75004b177ba41114fc.

The test case requires an assert build. Will add REQUIRES and re-commit.
The file was removedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit 46475a79f85b230fde3e7de8966c96bef14f0d24 by wei.huang
[AIX][TLS] Diagnose use of unimplemented TLS models

Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) var_name;`

Reviewed by: aaron.ballman, nemanjai, PowerPC

Differential Revision: https://reviews.llvm.org/D102070
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was addedclang/test/Sema/aix-attr-tls_model.c
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was addedclang/test/CodeGen/aix-tls-model.cpp
Commit cbcfca343f02876cef2b5ca3f27a037bab8fa90f by Lang Hames
[JITLink] Make LinkGraph debug dumps more readable.

This commit reorders some fields and fixes the width of others to try to
maintain more consistent columns. It also switches to long-hand scope
and linkage names, since LinkGraph dumps aren't read often enough for
single-character codes to be memorable.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit 74a96b4c98434e328eeca0afc85dc7053133a7d2 by Lang Hames
[JITLink][x86-64] Add an x86_64 PointerSize constexpr.

This can be used in place of magic '8' values in generic x86-64 utilities.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/x86_64.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
Commit a0162a81b1377331c3e0ebb58ac349b2ffd7b598 by Lang Hames
[JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes.

These can be used to create eh-frame section fixing passes outside the usual
linker pipeline, which can be useful for tests and tools that just want to
verify or dump graphs.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/MachO_x86_64.h
Commit 8280ece0c972db24e51aae5074ca5433002f1071 by phosek
[Coverage] Support overriding compilation directory

When making compilation relocatable, for example in distributed
compilation scenarios, we want to set compilation dir to a relative
value like `.` but this presents a problem when generating reports
because if the file path is relative as well, for example `..`, you
may end up writing files outside of the output directory.

This change introduces a flag that allows overriding the compilation
directory that's stored inside the profile with a different value that
is absolute.

Differential Revision: https://reviews.llvm.org/D100232
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
The file was modifiedllvm/tools/llvm-cov/CoverageViewOptions.h
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.proftext
The file was modifiedllvm/tools/llvm-cov/CodeCoverage.cpp
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMapping.cpp
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMappingReader.h
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.covmapping
The file was addedllvm/test/tools/llvm-cov/compilation_dir.c
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
Commit 40e3aa39bd68b554808ddcb096a63919f53f2e43 by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions
of the loop body will be different before and after interchange,
resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
Commit 5cb17728d19408725d4ced928ff3276dd4ffd1c9 by leonardchan
[clang][Fuchsia] Introduce compat multilibs

These are GCC-compatible multilibs that use the generic Itanium C++ ABI
instead of the Fuchsia C++ ABI.

Differential Revision: https://reviews.llvm.org/D102030
The file was addedclang/test/Driver/Inputs/basic_fuchsia_tree/lib/x86_64-unknown-fuchsia/compat/libc++.so
The file was modifiedclang/test/Driver/fuchsia.cpp
The file was modifiedclang/lib/Driver/ToolChains/Fuchsia.cpp
Commit d63860a05226d89f840a665134e2cb52c30ce4c4 by Lang Hames
[JITLink] Fix bogus format string.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit fec2945998947f04d672e9c5f33b57f7177474c0 by rupprecht
Revert "[GVN] Clobber partially aliased loads."

This reverts commit 6c570442318e2d3b8b13e95c2f2f588d71491acb.

It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543:

```
$ cat repro.ll
; ModuleID = 'repro.ll'
source_filename = "repro.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.widget = type { i32 }
%struct.baz = type { i32, %struct.snork }
%struct.snork = type { %struct.spam }
%struct.spam = type { i32, i32 }

@global = external local_unnamed_addr global %struct.widget, align 4
@global.1 = external local_unnamed_addr global i8, align 1
@global.2 = external local_unnamed_addr global i32, align 4

define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 {
bb:
  %tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1
  %tmp1 = bitcast %struct.snork* %tmp to i64*
  %tmp2 = load i64, i64* %tmp1, align 4
  %tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1
  %tmp4 = icmp ugt i64 %tmp2, 4294967295
  br label %bb5

bb5:                                              ; preds = %bb14, %bb
  %tmp6 = load i32, i32* %tmp3, align 4
  %tmp7 = icmp ne i32 %tmp6, 0
  %tmp8 = select i1 %tmp7, i1 %tmp4, i1 false
  %tmp9 = zext i1 %tmp8 to i8
  store i8 %tmp9, i8* @global.1, align 1
  %tmp10 = load i32, i32* @global.2, align 4
  switch i32 %tmp10, label %bb11 [
    i32 1, label %bb12
    i32 2, label %bb12
  ]

bb11:                                             ; preds = %bb5
  br label %bb14

bb12:                                             ; preds = %bb5, %bb5
  %tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4
  br label %bb14

bb14:                                             ; preds = %bb12, %bb11
  br label %bb5
}
$ opt -O2 repro.ll -disable-output
opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output
...
```
The file was modifiedllvm/test/Transforms/GVN/PRE/rle.ll
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
The file was modifiedllvm/lib/Analysis/MemoryDependenceAnalysis.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
Commit 2bdfcf0cac148ada8d3ec36f551c45efb604ac49 by Matthew.Arsenault
GlobalISel: Move AArch64 AssignFnVarArg to base class

We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
Commit 24e2e5df0e7eb017c64142c1f5899146fa52abba by Matthew.Arsenault
GlobalISel: Split ValueHandler into assignment and emission classes

Currently the ValueHandler handles both selecting the type and
location for arguments, as well as inserting instructions needed to
handle them. Split this so that the determination of the argument
handling is independent of the function state. Currently the checks
for tail call compatibility do not follow the full assignment logic,
so it misses cases where arguments require nontrivial legalization.

This should help avoid targets ending up in a buggy state where the
argument evaluation may change in different contexts.
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
Commit 6ecbdb761ffd684dc5fe624c0058fe7527a01881 by Matthew.Arsenault
GlobalISel: Make constant fields const
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
Commit a15ed701ab30d0073f46139df850fe23b03fd3ac by Matthew.Arsenault
AMDGPU: Fix assert on constant load from addrspacecasted pointer

This was trying to create a bitcast between different address spaces.
The file was addedllvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
Commit 6f5ddf67319b50664f3f5a4001723454696594b4 by Matthew.Arsenault
GlobalISel: Don't hardcode varargs=false in resultsCompatible
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 697ac15a0fc71888c372667bdbc5583ab42d4695 by richard
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.

This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.

Differential Revision: https://reviews.llvm.org/D101968
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
Commit 3978333b71bff3516ad69aac484b808617976c7a by richard
Add test for PR50039.

I believe Clang's behavior is correct according to the standard here,
but this is an unusual situation for which we had no test coverage, so
I'm adding some.
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
Commit bb726383ac7554857c62edd2d19e83dc713165ee by richard
Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope."

This reverts commit 697ac15a0fc71888c372667bdbc5583ab42d4695, for which
review was not complete. That change was accidentally pushed when
an unrelated change was pushed.
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
Commit 19cedd3cd3ab2144f7e477bb90d5f7ba8e500abb by sbc
[lld][WebAssembly] Fix for string merging + negative addends

Don't include the relocation addend when calculating the
virtual address of a symbol.  Instead just pass the symbol's
offset and add the addend afterwards.

Without this fix we hit the `offset is outside the section`
error in MergeInputSegment::getSegmentPiece.

This fixes a real world error we were are seeing in emscripten.

Differential Revision: https://reviews.llvm.org/D102271
The file was modifiedlld/test/wasm/merge-string.s
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Symbols.h
The file was modifiedlld/wasm/Symbols.cpp
Commit 0f2eb7e6e5dc2c1b5d1080160733b3a49e00c99c by jingham
This test is failing on Linux, skip while I investigate.

The gdb-remote tests are a bit artificial, depending on
Python threading, and sleeps.  So I'm not 100% surprised it doesn't
work straight up on another XSsystem.
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit cc79aaced0a405c7448c832a0974a694494496ca by Matthew.Arsenault
AMDGPU: Fix SILoadStoreOptimizer for gfx90a

This was hardcoding the register class to use for the newly created
pointer registers, violating the aligned VGPR requirement.
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
The file was addedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
Commit 10c309ad81e2be156ab44a83ee56cddea20637cc by jingham
Removing test...

Actually, I don't think this test is going to be stable enough
to be worthwhile.  Let me see if I can think of a better way to
test this.
The file was removedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit 3f8be15f2911a3d3645030911be83a115bfe9e5c by congzhecao
[LoopInterchange] Handle lcssa PHIs with multiple predecessors

This is a bugfix in the transformation phase.

If the original outer loop header branches to both the inner loop
(header) and the outer loop latch, and if there is an lcssa PHI
node outside the loop nest, then after interchange the new outer latch
will have an lcssa PHI node inserted which has two predecessors, i.e.,
the original outer header and the original outer latch. Currently
the transformation assumes it has only one predecessor (the original
outer latch) and crashes, since the inserted lcssa PHI node does
not take both predecessors as incoming BBs.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D100792
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was modifiedllvm/test/Transforms/LoopInterchange/lcssa.ll
Commit 7d101e0f6a38b95f512dc5d78bc9b508f4ee6da0 by Vitaly Buka
[NFC][msan] Move setlocale test into sanitizer_common
The file was removedcompiler-rt/test/msan/setlocale.cpp
The file was addedcompiler-rt/test/sanitizer_common/TestCases/setlocale.cpp
Commit f653313d4aec6f92b224ef996a8ac236dbb48baf by chiahungduan
[mlir][AsmPrinter] Remove recursion while SSA naming

Address the TODO of removing recursion while SSA naming.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102226
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 04b2ada51c90a76b153eedafd8d52a2649695a7f by dvyukov
tsan: add a simple syscall test

Add a simple test that uses syscall annotations.
Just to ensure at least basic functionality works.
Also factor out annotated syscall wrappers into a separate
header file as they may be useful for future tests.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102223
The file was addedcompiler-rt/test/tsan/Linux/syscall.cpp
The file was modifiedcompiler-rt/test/tsan/Linux/fork_syscall.cpp
The file was addedcompiler-rt/test/tsan/Linux/syscall.h
Commit 5dad3d1ba9ad01152be21e94cfbbfb31659ea3e1 by dvyukov
tsan: mark sigwait as blocking

Add a test case reported in:
https://github.com/google/sanitizers/issues/1401
and fix it.
The code assumes sigwait will process other signals.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102057
The file was addedcompiler-rt/test/tsan/signal_block2.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit 6d2df181638a34f5d4ebc0c92cfb6a30abf8588d by qiucofan
[VectorComine] Restrict single-element-store index to inbounds constant

Vector single element update optimization is landed in 2db4979. But the
scope needs restriction. This patch restricts the index to inbounds and
vector must be fixed sized. In future, we may use value tracking to
relax constant restrictions.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D102146
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 8214764f35e1b764fb939e18f16e11aa43073469 by dvyukov
tsan: declare annotations in test.h

We already declare subset of annotations in test.h.
But some are duplicated and declared in tests.
Move all annotation declarations to test.h.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102152
The file was modifiedcompiler-rt/test/tsan/test.h
The file was modifiedcompiler-rt/test/tsan/benign_race.cpp
The file was modifiedcompiler-rt/test/tsan/signal_sync2.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_lock.cpp
The file was modifiedcompiler-rt/test/tsan/mutexset5.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore2.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/thread_name.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore.cpp
The file was modifiedcompiler-rt/test/tsan/annotate_happens_before.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore3.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_double_lock.cpp
The file was modifiedcompiler-rt/test/tsan/ignore_sync.cpp
Commit 53558ed8a0abaf2f457cfa3d98c85d0fa1e84b22 by dvyukov
sanitizer_common: fix SIG_DFL warning

Currently we have:

sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible
  function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’
  146 |     sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL;

We don't set SA_SIGINFO, so we need to assign to sa_handler.
And SIG_DFL is meant for sa_handler, so this gets rid of both
compiler warning, type cast and potential runtime misbehavior.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102162
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp