Changes

Summary

Commit 387927bbaf96310cfcbd4bc41c34b90739af8338 by kazu [Target] Use range-based for loops (NFC)
	llvm/lib/CodeGen/StackSlotColoring.cpp
	llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
	llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
	llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
	llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
	llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
	llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
	llvm/lib/CodeGen/ModuloSchedule.cpp
	llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
	llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
	llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
	llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit b0c742152489c55ca5976a8f25538e88e224a7d2 by kai.wang [RISCV] Emit DWARF location expression for RVV stack objects. VLENB is the length of a vector register in bytes. We use <vscale x 64 bits> to represent one vector register. The dwarf offset is VLENB * scalable_offset / 8. For the mask vector, it occupies one vector register. Differential Revision: https://reviews.llvm.org/D107432
	llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
	llvm/lib/Target/RISCV/RISCVRegisterInfo.td
	llvm/lib/Target/RISCV/RISCVSystemOperands.td
	llvm/lib/Target/RISCV/RISCVRegisterInfo.h
	llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir