UnstableChanges

Summary

  1. removing windows deployment (details)
Commit a7a5cb5face77ca247d4a3ee2c919c93645b7366 by kuhnel
removing windows deployment

It's been unmaintained for a while and it's unclear
if we need a 32bit setup at all
The file was modifiedbuildbot/google/terraform/main.tf (diff)

Summary

  1. tsan: new MemoryAccess interface (details)
  2. tsan: add AccessVptr (details)
  3. [llvm-readobj][XCOFF] Fix the error dumping for the first (details)
  4. tsan: avoid extra call indirection in unaligned access functions (details)
  5. [clang-format] don't break between function and function name in JS (details)
  6. [mlir] Fix delayed object interfaces registration (details)
  7. [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted (details)
  8. [MLIR] Add `getI8Type` to `OpBuilder` (details)
  9. [RISCV] Support simple fractional steps in matching VID sequences (details)
  10. [MLIR][OpenMP] Add support for critical construct (details)
  11. [clang] Make member var invalid when static initializer is invalid. (details)
  12. tsan: use Tid/StackID types in MBlock (details)
  13. [libc] Allow benchmarking several implementations at the same time. (details)
  14. [llvm-objcopy] IHexELFBuilder::addDataSections - fix evaluation ordering static analyzer warning (details)
  15. Make simple requirements starting with requires ill-formed in in requirement body (details)
  16. tsan: use semaphores for thread creation synchronization (details)
  17. [X86] Add title comment to separate the "CPU Families" features from the other subtarget features. NFCI. (details)
  18. This feature is not in Clang 13 and only has partial support (details)
  19. [InstCombine] Remove nnan requirement for transformation to fabs from select (details)
  20. [InstCombine] Fold phi ( inttoptr/ptrtoint x ) to phi (x) (details)
  21. Revert "[InstCombine] Remove nnan requirement for transformation to fabs from select" (details)
  22. [OpenMP] libomp: taskwait depend implementation fixed. (details)
  23. [DAG] Cleanup DAGCombiner::CombineConsecutiveLoads early-outs. NFCI. (details)
  24. [mlir][CPURunner] Avoid a crash in memrefCopy when called with empty shapes. (details)
  25. tsan: remove unused caller_pc from TsanInterceptorContext (details)
  26. tsan: remove mallopt calls (details)
  27. [clan-format] detect function definitions more conservatively (details)
  28. [scudo] Make Vector() constexpr (details)
  29. [RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG. (details)
  30. [VectorCombine] Add tests where the index is guaranteed non-poison. (details)
  31. [ELF] Add --export-dynamic-symbol-list (details)
  32. [MCA][NFC] Add tests for PR51318 and PR51322. (details)
  33. [MLIR][Linalg] Extend detensoring control flow model. (details)
  34. [llvm] Fix header guards (NFC) (details)
  35. [AArch64] Prefer fmov over orr v.16b when copying f32/f64 (details)
  36. [NFC][tsan] Rename _inl.h to .inc (details)
  37. tsan: fix a typo in debug output (details)
  38. [AArch64][SME] Fix out of date comment (details)
  39. [llvm-profgen] Support perf script without parsing MMap events (details)
  40. [NFC][MLIR] Split large fusion test file into 4 test files (details)
  41. Reorder mmt4d r.h.s operand layout (details)
  42. [runtimeunroll] A bit of style cleanup to simplify a following change [NFC] (details)
  43. [X86][AVX] Add some multiple/nested subvector insertion shuffle tests (details)
  44. [llvm-readobj] Fix UB in pointer arithmetics after D105522 (details)
Commit 831910c5c4941b7c58d4d50d9e20808c8e2c1c0b by dvyukov
tsan: new MemoryAccess interface

Currently we have MemoryAccess function that accepts
"bool kAccessIsWrite, bool kIsAtomic" and 4 wrappers:
MemoryRead/MemoryWrite/MemoryReadAtomic/MemoryWriteAtomic.

Such scheme with bool flags is not particularly scalable/extendable.
Because of that we did not have Read/Write wrappers for UnalignedMemoryAccess,
and "true, false" or "false, true" at call sites is not very readable.

Moreover, the new tsan runtime will introduce more flags
(e.g. move "freed" and "vptr access" to memory acccess flags).
We can't have 16 wrappers and each flag also takes whole
64-bit register for non-inlined calls.

Introduce AccessType enum that contains bit mask of
read/write, atomic/non-atomic, and later free/non-free,
vptr/non-vptr.
Such scheme is more scalable, more readble, more efficient
(don't consume multiple registers for these flags during calls)
and allows to cover unaligned and range variations of memory
access functions as well.

Also switch from size log to just size.
The new tsan runtime won't have the limitation of supporting
only 1/2/4/8 access sizes, so we don't need the logarithms.

Also add an inline thunk that converts the new interface to the old one.
For inlined calls it should not add any overhead because
all flags/size can be computed as compile time.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107276
The file was modifiedcompiler-rt/lib/tsan/go/tsan_go.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_external.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_fd.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
Commit 18c6ed2f0f293582570ad3f6419e10ff808ba98e by dvyukov
tsan: add AccessVptr

Add AccessVptr access type.
For now it's converted to the same thr->is_vptr_access,
but later it will be passed directly to ReportRace
and will enable efficient tail calling in MemoryAccess function
(currently __tsan_vptr_update/__tsan_vptr_read can't use
tail calls in MemoryAccess because of the trailing assignment
to thr->is_vptr_access).

Depends on D107276.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107282
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
Commit 69396896fb615067b04a3e0c220f93bc91a10eec by esme.yi
[llvm-readobj][XCOFF] Fix the error dumping for the first
item of StringTable.

Summary: For the string table in XCOFF, the first 4 bytes
contains the length of the string table, so we should
print the string entries from fifth bytes. This patch
also adds tests for llvm-readobj dumping the string
table.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D105522
The file was modifiedllvm/test/tools/yaml2obj/XCOFF/basic-doc64.yaml
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.h
The file was modifiedllvm/tools/llvm-readobj/XCOFFDumper.cpp
The file was modifiedllvm/test/tools/yaml2obj/XCOFF/long-symbol-name.yaml
The file was addedllvm/test/tools/llvm-readobj/XCOFF/string-table.yaml
The file was modifiedllvm/lib/Object/XCOFFObjectFile.cpp
Commit d77b476c1953bcb0a608b2d6a4f2dd9fe0b43967 by dvyukov
tsan: avoid extra call indirection in unaligned access functions

Currently unaligned access functions are defined in tsan_interface.cpp
and do a real call to MemoryAccess. This means we have a real call
and no read/write constant propagation.

Unaligned memory access can be quite hot for some programs
(observed on some compression algorithms with ~90% of unaligned accesses).

Move them to tsan_interface_inl.h to avoid the additional call
and enable constant propagation.
Also reorder the actual store and memory access handling for
__sanitizer_unaligned_store callbacks to enable tail calling
in MemoryAccess.

Depends on D107282.

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D107283
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
Commit 4f4f2783056fd01182740251b2ce8a77b12684b3 by krasimir
[clang-format] don't break between function and function name in JS

The patch https://reviews.llvm.org/D105964 (https://github.com/llvm/llvm-project/commit/58494c856a15f5b0e886c7baf5d505ac6c05dfe5)
updated detection of function declaration names. It had the unfortunate
consequence that it started breaking between `function` and the function
name in some cases in JavaScript code.

This patch addresses this.

Reviewed By: MyDeveloperDay, owenpan

Differential Revision: https://reviews.llvm.org/D107267
The file was modifiedclang/lib/Format/ContinuationIndenter.cpp
The file was modifiedclang/unittests/Format/FormatTestJS.cpp
Commit 9b50844fd798b5a81afd4aeb44b053d622747a42 by vlad.vinogradov
[mlir] Fix delayed object interfaces registration

Store both interfaceID and objectID as key for interface registration callback.
Otherwise the implementation allows to register only one external model per one object in the single dialect.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D107274
The file was modifiedmlir/lib/IR/Dialect.cpp
The file was modifiedmlir/unittests/IR/InterfaceAttachmentTest.cpp
The file was modifiedmlir/include/mlir/IR/Dialect.h
Commit 0d8cd4e2d5d4abb804d40984522e0413c66a3cbd by Jason Molenda
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted

Add a comment when there is a shifted value,
    add x9, x0, #291, lsl #12 ; =1191936
but not when the immediate value is unshifted,
    subs x9, x0, #256 ; =256
when the comment adds nothing additional to the reader.

Differential Revision: https://reviews.llvm.org/D107196
The file was modifiedllvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
The file was modifiedllvm/test/CodeGen/AArch64/select_const.ll
The file was modifiedllvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/AArch64/uaddo.ll
The file was modifiedllvm/test/CodeGen/AArch64/atomicrmw-O0.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/vldn_shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
The file was modifiedllvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll
The file was modifiedllvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
The file was modifiedllvm/test/CodeGen/AArch64/funnel-shift.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-atomic-128.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec-libcalls.ll
The file was modifiedllvm/test/CodeGen/AArch64/neg-abs.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fp128.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/sub1.ll
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch-nobase.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
The file was modifiedllvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vabs.ll
The file was modifiedllvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-element.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-bcc.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-sdiv.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-load-ext.ll
The file was modifiedllvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
The file was modifiedllvm/test/CodeGen/AArch64/align-down.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-cbz.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-copy.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
The file was modifiedllvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s
The file was modifiedllvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
The file was modifiedllvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
The file was modifiedllvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-ld1r.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/AArch64/shift-mod.ll
The file was modifiedllvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
The file was modifiedllvm/test/CodeGen/AArch64/sub-of-not.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
The file was modifiedllvm/test/CodeGen/AArch64/cgp-usubo.ll
The file was modifiedllvm/test/CodeGen/AArch64/usub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/signbit-shift.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-lkk.ll
The file was modifiedllvm/test/CodeGen/AArch64/extract-bits.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
The file was modifiedllvm/test/CodeGen/AArch64/signed-truncation-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
The file was modifiedllvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/logical_shifted_reg.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-bool.ll
The file was modifiedllvm/test/CodeGen/AArch64/addsub-constant-folding.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/AArch64/sdivpow2.ll
The file was modifiedllvm/test/CodeGen/AArch64/lack-of-signed-truncation-check.ll
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-ccmp.ll
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
The file was modifiedllvm/test/CodeGen/AArch64/addsub.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-nvcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/split-vector-insert.ll
The file was modifiedllvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/cmp-select-sign.ll
The file was modifiedllvm/test/CodeGen/AArch64/pr48188.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-thunk.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/sat-add.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec_uaddo.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
The file was modifiedllvm/test/CodeGen/AArch64/ls64-inline-asm.ll
The file was modifiedllvm/test/CodeGen/AArch64/extract-lowbits.ll
The file was modifiedllvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-memset-inline.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-popcnt.ll
The file was modifiedllvm/test/CodeGen/AArch64/inc-of-add.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-extract-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/pow.ll
Commit f0008a4cf43588ff695c84dbfe3b1ae89640f85c by frgossen
[MLIR] Add `getI8Type` to `OpBuilder`

Differential Revision: https://reviews.llvm.org/D107332
The file was modifiedmlir/lib/IR/Builders.cpp
The file was modifiedmlir/include/mlir/IR/Builders.h
Commit cba6aab9715988b522c21b0e04a7d9b888a81394 by fraser
[RISCV] Support simple fractional steps in matching VID sequences

This patch extends the optimization of VID-sequence BUILD_VECTORs
introduced in D104921 to include simple fractional steps composed of a
separated integer numerator and denominator.

A notable limitation in this sequence detection is that only sequences
with steps N/1 or 1/D are found, meaning that the step between elements
and the frequency with which it changes is consistent across the whole
sequence. Fractional steps such as 2/3 won't be matched as those would
involve more complex tracking of state or some level of backtracking.

As is stands, however, this patch is sufficient to match common
interleave-type shuffle indices, for example matching `<0,0,1,1>` (or
commonly `<0,u,1,u>` or `<u,0,u,1>`) to an index sequence divided by 2.

While the optimization is relatively `undef`-tolerant, due to greedy
pattern-matching there even are some simple patterns which confuse the
sequence detection into identifying either a suboptimal sequence or no
sequence at all.

Currently only fractional-step sequences identified as having a
power-of-two denominator are actually lowered to RVV instructions. This
is to avoid introducing divisions into the generated code.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106533
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 59989d68ba065b8dc1909d525dfd135d9e3c0206 by kiran.chandramohan
[MLIR][OpenMP] Add support for critical construct

This patch adds the critical construct to the OpenMP dialect. The
implementation models the definition in 2.17.1 of the OpenMP 5 standard.
A name and hint can be specified. The name is a global entity or has
external linkage, it is modelled as a FlatSymbolRefAttr. Hint is
modelled as an integer enum attribute.
Also lowering to LLVM IR using the OpenMP IRBuilder.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D107135
The file was modifiedmlir/test/Dialect/OpenMP/invalid.mlir
The file was modifiedmlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
The file was modifiedmlir/test/Dialect/OpenMP/ops.mlir
The file was modifiedmlir/test/Target/LLVMIR/openmp-llvm.mlir
The file was modifiedmlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Commit 08128fe7059e20b3f97ae5abbdeff2e6f6c711ed by adamcz
[clang] Make member var invalid when static initializer is invalid.

Previously we would show an error, but keep the member, and also the
CXXRrecordDecl, valid. This could lead to crashes when attempting to
access the record layout or size.

Differential Revision: https://reviews.llvm.org/D105478
The file was modifiedclang/test/SemaCXX/cxx11-crashes.cpp
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was addedclang/test/AST/ast-dump-undeduced-expr.cpp
The file was modifiedclang/test/SemaCXX/crash-auto-36064.cpp
Commit 559426ae7695321a4609ae6799455f86cbfc2257 by dvyukov
tsan: use Tid/StackID types in MBlock

Replace more raw types with Tid/StackID typedefs.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107335
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_defs.h
Commit e4dee762245d1fefc6bcae643ecc55063aef2e9c by gchatelet
[libc] Allow benchmarking several implementations at the same time.

Next step is to generate an archive with all implementations and a header listing them all.

Differential Revision: https://reviews.llvm.org/D107336
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.h
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.cpp
The file was modifiedlibc/benchmarks/LibcMemoryGoogleBenchmarkMain.cpp
Commit 43ff058e78d9e4fa47080b61fc3811da80db1b3f by llvm-dev
[llvm-objcopy] IHexELFBuilder::addDataSections - fix evaluation ordering static analyzer warning

As detailed on https://pvs-studio.com/en/blog/posts/cpp/0771/ and raised on D62583, the SecNo++ increment is not guaranteed to occur before the second use of SecNo in the same addSection() call.

This patch pulls out the increment (just for clarity) and replaces the second use of SecNo with a constant zero value (we're using stable_sort so the value isn't critical).

Differential Revision: https://reviews.llvm.org/D107273
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
Commit 977bdf6f44edabb857bdff9ca249aa6eccb98e96 by aaron
Make simple requirements starting with requires ill-formed in in requirement body

This patch implements P2092

Simple requirements in requirement body shall not start with requires.
A warning was already in place so we just turn this warning into an error.

In addition, we add tests to make sure typename is optional in
requirement-parameter-list as per the same paper.
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/www/cxx_status.html
The file was modifiedclang/test/Parser/cxx2a-concepts-requires-expr.cpp
The file was modifiedclang/lib/Parse/ParseExprCXX.cpp
Commit e72ad3c19a15a5716617f8c1d273ca506dc68276 by dvyukov
tsan: use semaphores for thread creation synchronization

We currently use ad-hoc spin waiting to synchronize thread creation
and thread start both ways. But spinning tend to degrade ungracefully
under high contention (lots of threads are created at the same time).
Use semaphores for synchronization instead.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107337
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit d3917bbfc6bdd0a599a4d3350a4f215a7b33cf94 by llvm-dev
[X86] Add title comment to separate the "CPU Families" features from the other subtarget features. NFCI.

Hopefully we can get rid of these some day...
The file was modifiedllvm/lib/Target/X86/X86.td
Commit 80c17bb29838bee0d67a7bc2c775a8a91d69ac2d by aaron
This feature is not in Clang 13 and only has partial support
The file was modifiedclang/www/cxx_status.html
Commit 6180ce2e2abeb6f1f1b57852773ea07b8be290fa by krishna17060
[InstCombine] Remove nnan requirement for transformation to fabs from select

In this patch, the "nnan" requirement is removed for the canonicalization of select with fcmp to fabs.
(i) FSub logic: Remove check for nnan flag presence in fsub. Example: https://alive2.llvm.org/ce/z/751svg (fsub).
(ii) FNeg logic: Remove check for the presence of nnan and nsz flag in fneg. Example: https://alive2.llvm.org/ce/z/a_fsdp (fneg).

Differential Revision: https://reviews.llvm.org/D106872
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll
Commit d99260641b30b0638c6a1e60bcb971ec09fa5368 by krishna17060
[InstCombine] Fold phi ( inttoptr/ptrtoint x ) to phi (x)

The inttoptr/ptrtoint roundtrip optimization is not always correct.
We are working towards removing this optimization and adding support to specific cases where this optimization works.

In this patch, we focus on phi-node operands with inttoptr casts.
We know that ptrtoint( inttoptr( ptrtoint x) ) is same as ptrtoint (x).
So, we want to remove this roundtrip cast which goes through phi-node.

Reviewed By: aqjune

Differential Revision: https://reviews.llvm.org/D106289
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was addedllvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
Commit 946fd4ea65bdd0a97f426c4fa4731f1620a9aa68 by krishna17060
Revert "[InstCombine] Remove nnan requirement for transformation to fabs from select"

This reverts commit 6180ce2e2abeb6f1f1b57852773ea07b8be290fa.
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 8e29b4b323b87f3855dc71abf1e3f3d48952a4e4 by Andrey.Churbanov
[OpenMP] libomp: taskwait depend implementation fixed.

Fix for https://bugs.llvm.org/show_bug.cgi?id=49723.
Eliminated references from task dependency hash to node allocated on stack,
thus eliminated accesses to stale memory. So the node now never freed.
Uncommented assertion which triggered when stale memory accessed.
Removed unneeded ref count increment for stack allocated node.

Differential Revision: https://reviews.llvm.org/D106705
The file was modifiedopenmp/runtime/src/kmp_taskdeps.cpp
The file was modifiedopenmp/runtime/src/kmp_taskdeps.h
The file was addedopenmp/runtime/test/tasking/kmp_taskwait_depend_in.c
Commit 11396641e46c22fe8fede7c2b49d6f055641a220 by llvm-dev
[DAG] Cleanup DAGCombiner::CombineConsecutiveLoads early-outs. NFCI.

We had some similar hasOneUse/isNON_EXTLoad early-outs spread out over different parts of the method - we should pull them all together.

Noticed while triaging PR45116
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 76fd3d4410c1dc637944a930a3ce760836b4d765 by akuegel
[mlir][CPURunner] Avoid a crash in memrefCopy when called with empty shapes.

Differential Revision: https://reviews.llvm.org/D107346
The file was modifiedmlir/lib/ExecutionEngine/CRunnerUtils.cpp
The file was modifiedmlir/test/mlir-cpu-runner/copy.mlir
Commit 7779f49bc1f00eff3aba590a8e960d22a595f69f by dvyukov
tsan: remove unused caller_pc from TsanInterceptorContext

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107340
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit ac2bc4e0fc4c0c9d4903b49b445451d5d42356db by dvyukov
tsan: remove mallopt calls

mallopt calls are left-over from the times we used
__libc_malloc/__libc_free for internal allocations.
Now we have own internal allocator, so this is not needed.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D107342
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit f6bc614546e169bb1b17a29c422ebace038e6c62 by krasimir
[clan-format] detect function definitions more conservatively

https://reviews.llvm.org/D105964 updated the detection of function
definitions. It had the unfortunate effect to start marking object
definitions with attribute-like macros as function definitions.

This addresses this issue.

Reviewed By: owenpan

Differential Revision: https://reviews.llvm.org/D107269
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
Commit 23a94af44939b094f9ba2d6bb969f5a48b78fa8c by kostyak
[scudo] Make Vector() constexpr

A `Vector` that doesn't require an initial `reserve()` (eg: with a
default, or small enough capacity) can have a constant initializer.

This changes the code in a few places to make that possible:
- mark a few other functions as `constexpr`
- do without any `reinterpret_cast`
- allow to skip `reserve` from `init`

Differential Revision: https://reviews.llvm.org/D107308
The file was modifiedcompiler-rt/lib/scudo/standalone/vector.h
Commit deaeb16d88e92be644a157d499e9862cde4f22aa by craig.topper
[RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG.

Return false from runOnFunction if nothing changed. Curiously
we already returned a bool from detectAndFoldOffset, but didn't
use it.

Fix a couple breaks after returns that I saw while auditing
detectAndFoldOffset.

Differential Revision: https://reviews.llvm.org/D107303
The file was modifiedllvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
Commit ccf1038a92971d9f3faa9b7940430d3891bab2b8 by flo
[VectorCombine] Add tests where the index is guaranteed non-poison.

Tests for PR50949.
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
Commit 44361e5b90986ebe64c2263cefe504bf9b170eac by i
[ELF] Add --export-dynamic-symbol-list

This is available in GNU ld 2.35 and can be seen as a shortcut for multiple
--export-dynamic-symbol, or a --dynamic-list variant without the symbolic intention.

In the long term, this option probably should be preferred over --dynamic-list.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D107317
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/test/ELF/export-dynamic-symbol.s
The file was modifiedlld/docs/ReleaseNotes.rst
The file was modifiedlld/ELF/Options.td
The file was modifiedlld/docs/ld.lld.1
Commit f0658c7a429b9e356da1670b280ab943ad0b0b94 by andrea.dibiagio
[MCA][NFC] Add tests for PR51318 and PR51322.

Also, regenerate existing X86 tests using update_mca_test.py.
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-stats-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-stats-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-views-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/option-all-views-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
The file was addedllvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
Commit f984a805f3f92ea3066ea13ba2684a7947d95225 by kareem.ergawy
[MLIR][Linalg] Extend detensoring control flow model.

This patch extends the PureControlFlowDetectionModel to consider
detensoring br and cond_br operands.

See: https://github.com/google/iree/issues/1159#issuecomment-884322687,
for a disccusion on the need for such extension.

Reviewed By: silvas

Differential Revision: https://reviews.llvm.org/D107358
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Detensorize.cpp
The file was addedmlir/test/Dialect/Linalg/detensorize_br_operands.mlir
Commit eec96db184fee4a3e67e9eb97efc29bc7452007c by kazu
[llvm] Fix header guards (NFC)

Identified with llvm-header-guard.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Shared/WrapperFunctionUtils.h
The file was modifiedllvm/include/llvm/TextAPI/TextAPIReader.h
The file was modifiedllvm/include/llvm/TextAPI/Architecture.h
The file was modifiedllvm/include/llvm/TextAPI/InterfaceFile.h
The file was modifiedllvm/include/llvm/Analysis/ObjCARCUtil.h
The file was modifiedllvm/include/llvm/TextAPI/Symbol.h
The file was modifiedllvm/include/llvm/TextAPI/TextAPIWriter.h
The file was modifiedllvm/include/llvm/AsmParser/LLLexer.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
The file was modifiedllvm/include/llvm/TextAPI/Target.h
The file was modifiedllvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
The file was modifiedllvm/include/llvm/AsmParser/LLToken.h
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
The file was modifiedllvm/include/llvm/TextAPI/ArchitectureSet.h
The file was modifiedllvm/include/llvm/TextAPI/PackedVersion.h
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/ELF_riscv.h
The file was modifiedllvm/include/llvm/TextAPI/Platform.h
Commit bd07c2e266f65acb0204198ae1a441bf10499cb2 by david.green
[AArch64] Prefer fmov over orr v.16b when copying f32/f64

This changes the lowering of f32 and f64 COPY from a 128bit vector ORR to
a fmov of the appropriate type. At least on some CPU's with 64bit NEON
data paths this is expected to be faster, and shouldn't be slower on any
CPU that treats fmov as a register rename.

Differential Revision: https://reviews.llvm.org/D106365
The file was modifiedllvm/test/CodeGen/AArch64/f16-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/fadd-combines.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/sqrt-fastmath.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-aapcs.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec-libcalls.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/mla_mls_merge.ll
The file was modifiedllvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
The file was modifiedllvm/test/CodeGen/AArch64/neon-mla-mls.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
The file was modifiedllvm/test/CodeGen/AArch64/urem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
The file was modifiedllvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
The file was modifiedllvm/test/CodeGen/AArch64/machine-combiner.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-copy.ll
The file was modifiedllvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
Commit 6538aa8ce9b0806f0d343e0029c9a982d5971092 by Vitaly Buka
[NFC][tsan] Rename _inl.h to .inc

Differential Revision: https://reviews.llvm.org/D107319
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/tsan/BUILD.gn
The file was removedcompiler-rt/lib/tsan/rtl/tsan_update_shadow_word_inl.h
The file was removedcompiler-rt/lib/tsan/rtl/tsan_interface_inl.h
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was addedcompiler-rt/lib/tsan/rtl/tsan_update_shadow_word.inc
The file was addedcompiler-rt/lib/tsan/rtl/tsan_interface.inc
Commit e34d1942a05eaf93834754d4f433ebf3afbdb4a0 by dvyukov
tsan: fix a typo in debug output

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D107368
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_java.cpp
Commit 86e4d0059374d69ddde265cf6c69d32ce4499d63 by cullen.rhodes
[AArch64][SME] Fix out of date comment

Missed in 3a349d22692c.
The file was modifiedllvm/test/MC/AArch64/SME/feature.s
Commit fe3ba90830f6ee84f9bb305606dec38451c4c884 by wlei
[llvm-profgen] Support perf script without parsing MMap events

This change supports to run without parsing MMap binary loading events instead it always assumes binary is loaded at the preferred address. This is used when we have assured no binary load address changes or we have pre-processed the addresses resolution. Warn if there's interior mmap event but without leading mmap events.

Reviewed By: hoy

Differential Revision: https://reviews.llvm.org/D107097
The file was addedllvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
The file was modifiedllvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
Commit 24b0df868604b079aebd30ca2ae2a11a30d3b97e by sumesh.uk
[NFC][MLIR] Split large fusion test file into 4 test files

mlir/test/transforms/loop-fusion.mlir is too big and is split into mlir/test/transforms/loop-fusion.mlir,  mlir/test/transforms/loop-fusion-2.mlir, mlir/test/transforms/loop-fusion-3.mlir
and mlir/test/transforms/loop-fusion-4.mlir. Further tests can be added in mlir/test/transforms/loop-fusion-4.mlir

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D106473
The file was addedmlir/test/Transforms/loop-fusion-3.mlir
The file was addedmlir/test/Transforms/loop-fusion-4.mlir
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
The file was addedmlir/test/Transforms/loop-fusion-2.mlir
Commit 53d6988171aed2c71d920b940264774f73248ca1 by ataei
Reorder mmt4d r.h.s operand layout

Switch r.h.s operand layout (n1, k1, n0, k0) -> (n1, k1, k0, n0)
which is more consistant with scalar-vector products vectorization
and elementates operand transpose.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D107307
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
Commit 223835f08b25b407e5343df76603639a36775c38 by listmail
[runtimeunroll] A bit of style cleanup to simplify a following change [NFC]

Use for-range, use the idiomatic pattern for non-loop values, etc..
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
Commit 14b71efd979ce3dacf6b3d9913df8e4f063224c5 by llvm-dev
[X86][AVX] Add some multiple/nested subvector insertion shuffle tests

As discussed on D107068 - see how well we merge INSERT_SUBVECTOR nodes and combine a shuffles using multiple ops in CONCAT_VECTORS nodes.
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
Commit 033ca45d4f097f92dd6254f29881d906f45e0c26 by Vitaly Buka
[llvm-readobj] Fix UB in pointer arithmetics after D105522
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp

Summary

  1. removing windows deployment (details)
Commit a7a5cb5face77ca247d4a3ee2c919c93645b7366 by kuhnel
removing windows deployment

It's been unmaintained for a while and it's unclear
if we need a 32bit setup at all
The file was modifiedbuildbot/google/terraform/main.tf