Commit
79debe8d7b5897d6c8efaa8cd9846a3b4533d57f
by jianzhouzh[dfsan] Turn off all dfsan test cases on non x86_64 OSs
https://reviews.llvm.org/D101666 enables sanitizer allocator. This broke all test cases on non x86-64.
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 | compiler-rt/test/dfsan/write_callback.c |
 | compiler-rt/test/dfsan/release_shadow_space.c |
 | compiler-rt/test/dfsan/flags.c |
 | compiler-rt/test/dfsan/fncall.c |
 | compiler-rt/test/dfsan/interceptors.c |
 | compiler-rt/test/dfsan/trace-cmp.c |
 | compiler-rt/test/dfsan/fast16labels.c |
 | compiler-rt/test/dfsan/struct.c |
 | compiler-rt/test/dfsan/propagate.c |
 | compiler-rt/test/dfsan/sigaction.c |
 | compiler-rt/test/dfsan/label_count.c |
 | compiler-rt/test/dfsan/threaded_flush.c |
 | compiler-rt/test/dfsan/vararg.c |
 | compiler-rt/test/dfsan/pair.cpp |
 | compiler-rt/test/dfsan/dump_labels.c |
 | compiler-rt/test/dfsan/basic.c |
 | compiler-rt/test/dfsan/event_callbacks.c |
 | compiler-rt/test/dfsan/flush.c |
Commit
9775582e347c08f79f84748d143eb8c2e4258afb
by medismail.bennani[lldb/Test] Disable testBreakpointByLineAndColumnNearestCode on Windows
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
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 | lldb/test/API/functionalities/breakpoint/breakpoint_by_line_and_column/TestBreakpointByLineAndColumn.py |
Commit
cab3c6c6c48ed0da0f047bdc1a337d991c78ad8c
by nullptr.cpp[clang][TargetCXXABI] Fix -Wreturn-type warning (NFC)
GCC warning: ``` In file included from /llvm-project/clang/include/clang/Basic/LangOptions.h:22, from /llvm-project/clang/include/clang/Frontend/CompilerInvocation.h:16, from /llvm-project/clang/lib/Frontend/CompilerInvocation.cpp:9: /llvm-project/clang/include/clang/Basic/TargetCXXABI.h: In static member function ‘static bool clang::TargetCXXABI::isSupportedCXXABI(const llvm::Triple&, clang::TargetCXXABI::Kind)’: /llvm-project/clang/include/clang/Basic/TargetCXXABI.h:114:3: warning: control reaches end of non-void function [-Wreturn-type] 114 | }; | ^ ```
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 | clang/include/clang/Basic/TargetCXXABI.h |
Commit
e510860656bb81bd90ae3cf8bb5ef4dc8cd33c18
by i[llvm-objdump] Add -M {att,intel} & deprecate --x86-asm-syntax={att,intel}
The internal `cl::opt` option --x86-asm-syntax sets the AsmParser and AsmWriter dialect. The option is used by llc and llvm-mc tests to set the AsmWriter dialect.
This patch adds -M {att,intel} as GNU objdump compatible aliases (PR43413).
Note: the dialect is initialized when the MCAsmInfo is constructed. `MCInstPrinter::applyTargetSpecificCLOption` is called too late and its MCAsmInfo reference is const, so changing the `cl::opt` in `MCInstPrinter::applyTargetSpecificCLOption` is not an option, at least without large amount of refactoring.
Reviewed By: hoy, jhenderson, thakis
Differential Revision: https://reviews.llvm.org/D101695
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 | llvm/test/tools/llvm-objdump/X86/syntax-mode.s |
 | llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbololize-operands.yaml |
 | llvm/docs/ReleaseNotes.rst |
 | llvm/tools/llvm-objdump/llvm-objdump.cpp |
 | llvm/docs/CommandGuide/llvm-objdump.rst |
Commit
001d601ac4fb1ee02d4bb3990f2f5a8afacd4932
by zinenko[mlir][ArmSVE] Add basic arithmetic operations
While we figure out how to best add Standard support for scalable vectors, these instructions provide a workaround for basic arithmetic between scalable vectors.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D100837
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 | mlir/test/Target/LLVMIR/arm-sve.mlir |
 | mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir |
 | mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp |
 | mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td |
 | mlir/test/Dialect/ArmSVE/roundtrip.mlir |
Commit
a1ed39df96bc5b98bd5a83c7d2c1a385c03133e5
by jay.foad[AMDGPU] Select V_CVT_*16_F16 more often
Improve the code generation of fp_to_sint and fp_to_uint for integer on 16-bits.
Differential Revision: https://reviews.llvm.org/D101481
Patch by Julien Pagès!
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 | llvm/test/CodeGen/AMDGPU/fptoui.f16.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h |
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/test/CodeGen/AMDGPU/fp_to_uint.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |
 | llvm/test/CodeGen/AMDGPU/fptosi.f16.ll |
Commit
cd6a52fedefe263565b81fbee9d5d3278e1e63cb
by fraser[RISCV] Cap legal fixed-length vectors to 256-element types
Previously, RISC-V would make legal all fixed-length vectors types whose size are less than or equal to some function of the minimum value of VLEN and the maximum-permissible LMUL grouping.
Due to vector legalization issues, this patch instead caps the legal fixed-length vector types to those with 256 elements. This value was chosen because it is the longest vector length which has corresponding MVTs across all supported element types.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D101839
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 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
 | llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll |