SuccessChanges

Summary

  1. Revert "[Attributor] AAPotentialValues Interface" (details)
  2. Remove unused param tag to fix Wdocumentation warning. NFC. (details)
  3. [DAG] TargetLowering::LowerAsmOutputForConstraint - pass SDLoc as const& (details)
  4. [DAG] TargetLowering::expandMUL_LOHI - pass SDLoc as const& (details)
  5. Use merge null and isa<> tests into isa_and_nonnull<>. NFCI. (details)
  6. X86InstrInfo.cpp - fix include ordering. NFCI. (details)
  7. GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT (details)
  8. [InstSimplify] add tests for max(max x,y), x) and variants; NFC (details)
  9. [InstSimplify] fold max (max X, Y), X --> max X, Y (details)
  10. [IR] Add IRBuilderBase::CreateVectorSplat(ElementCount EC) variant (details)
  11. Remove debug flags from test (NFC) (details)
  12. [AMDGPU] Regenerate tests to fix whitespace indentations (details)
  13. [X86] Add test cases for missed opportunity to use a byte test instruction instead of an xor with 0 in parity patterns. (details)
  14. [X86] Use parity flag from byte test/cmp instruction for __builtin_parity when input fits in 8 bits. (details)
Commit 376b64926b70c8b146caaf397616fb681ae329ca by okuraofvegetable
Revert "[Attributor] AAPotentialValues Interface"

The commit cause build failure.
The file was modifiedllvm/lib/IR/LLVMContextImpl.h
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was removedllvm/test/Transforms/Attributor/potential.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/include/llvm/ADT/APInt.h
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
Commit 90dab1aece7100ace855321162c0d2a09b31c1b3 by llvm-dev
Remove unused param tag to fix Wdocumentation warning. NFC.
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
Commit d14a22da5e437dfbf5fe96a6586cec2153f36861 by llvm-dev
[DAG] TargetLowering::LowerAsmOutputForConstraint - pass SDLoc as const&

Try to be more consistent with the SDLoc param in the TargetLowering methods.
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit b8ffbf0e02e24d7be3017c8ee5f17dab9e39719f by llvm-dev
[DAG] TargetLowering::expandMUL_LOHI - pass SDLoc as const&

Try to be more consistent with the SDLoc param in the TargetLowering methods.

This also exposes an issue where we were passing a SDNode as a SDLoc, relying on the implicit SDLoc(SDNode) constructor.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 7dd4f03595d3687cab555d538c82a41f1c1043ce by llvm-dev
Use merge null and isa<> tests into isa_and_nonnull<>. NFCI.
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
Commit 00d0f354f26dc725ee1ce756df383557eeb44c65 by llvm-dev
X86InstrInfo.cpp - fix include ordering. NFCI.
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
Commit 212570abcf755b8577a7aec80777503232d36d77 by Matthew.Arsenault
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT

For AMDGPU, vectors with elements < 32 bits should be indexed in
32-bit elements and the desired bits extracted from there. For
elements > 64-bits, these should be reduce to 64/32 elements to enable
the normal dynamic indexing paths.

In the dynamic index cases, this produces shorter code most of the
time. This does immediately regress the constant index cases, but this
should be fixed once we have the most basic of shift combines.

The element size > 64 case is pretty much ported from the exisiting
DAG implementation for extract element promote. The increasing element
size case is new.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
Commit e37987563ad194c41125ce836cc04df57737c698 by spatel
[InstSimplify] add tests for max(max x,y), x) and variants; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll
Commit 4abc69c6f541e7726913c9b0940728b1e0024b4a by spatel
[InstSimplify] fold max (max X, Y), X --> max X, Y

https://alive2.llvm.org/ce/z/VGgG3M
The file was modifiedllvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit e20223672100ed4826827412b80a605c759538da by llvm-dev
[IR] Add IRBuilderBase::CreateVectorSplat(ElementCount EC) variant

As discussed on D81500, this adds a more general ElementCount variant of the build helper and converts the (non-scalable) unsigned NumElts variant to use it internally.
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/unittests/Analysis/VectorUtilsTest.cpp
The file was modifiedllvm/lib/IR/IRBuilder.cpp
Commit 4091413c0047b58853b3f62dd5f36c836f75330d by joker.eph
Remove debug flags from test (NFC)
The file was modifiedmlir/test/mlir-rocm-runner/two-modules.mlir
The file was modifiedmlir/test/mlir-cuda-runner/two-modules.mlir
Commit e7a8ee00e6c3b20fc04792db1acf9d5324a1b7bb by llvm-dev
[AMDGPU] Regenerate tests to fix whitespace indentations

Noticed while updating D77804
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
Commit a258338d627170f204c40ebe93ea7fb18c7c1197 by craig.topper
[X86] Add test cases for missed opportunity to use a byte test instruction instead of an xor with 0 in parity patterns.

If the input to the ctpop fits in 8 bits, we can use the parity
flag from a TEST instruction, but we're currently XORing with 0.
The file was modifiedllvm/test/CodeGen/X86/parity.ll
Commit 64516ec7c1298a4cb16980db49c2f9466f0f3ab5 by craig.topper
[X86] Use parity flag from byte test/cmp instruction for __builtin_parity when input fits in 8 bits.

If the upper bits of the __builtin_parity idiom are known to be
0 we were previously emitting an xor with 0 to get the parity flag.
But we can use cmp/test instead which may expose opportunities for
load folding or combining an AND.
The file was modifiedllvm/test/CodeGen/X86/parity.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-xor-bool.ll